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xil_444.in @ 139

Last change on this file since 139 was 115, checked in by rolagamo, 10 years ago
Ajout des Cores utilisés dans le projet
File size: 4.1 KB

Line
1	SET_FLAG DEBUG FALSE
2	SET_FLAG MODE INTERACTIVE
3	SET_FLAG STANDALONE_MODE FALSE
4	SET_PREFERENCE devicefamily spartan6
5	SET_PREFERENCE device xc6slx45
6	SET_PREFERENCE speedgrade -3
7	SET_PREFERENCE package csg324
8	SET_PREFERENCE verilogsim false
9	SET_PREFERENCE vhdlsim true
10	SET_PREFERENCE simulationfiles Behavioral
11	SET_PREFERENCE busformat BusFormatAngleBracketNotRipped
12	SET_PREFERENCE outputdirectory D:/MPI_HCL/Test_Timer/ipcore_dir/
13	SET_PREFERENCE workingdirectory D:/MPI_HCL/Test_Timer/ipcore_dir/tmp/
14	SET_PREFERENCE subworkingdirectory D:/MPI_HCL/Test_Timer/ipcore_dir/tmp/_cg/
15	SET_PREFERENCE transientdirectory D:/MPI_HCL/Test_Timer/ipcore_dir/tmp/_cg/_dbg/
16	SET_PREFERENCE designentry VHDL
17	SET_PREFERENCE flowvendor Other
18	SET_PREFERENCE addpads false
19	SET_PREFERENCE projectname coregen
20	SET_PREFERENCE formalverification false
21	SET_PREFERENCE asysymbol false
22	SET_PREFERENCE implementationfiletype Ngc
23	SET_PREFERENCE foundationsym false
24	SET_PREFERENCE createndf false
25	SET_PREFERENCE removerpms false
26	SET_PARAMETER Component_Name mem_4k8
27	SET_PARAMETER Interface_Type Native
28	SET_PARAMETER AXI_Type AXI4_Full
29	SET_PARAMETER AXI_Slave_Type Memory_Slave
30	SET_PARAMETER Use_AXI_ID false
31	SET_PARAMETER AXI_ID_Width 4
32	SET_PARAMETER Memory_Type Simple_Dual_Port_RAM
33	SET_PARAMETER ecctype No_ECC
34	SET_PARAMETER ECC false
35	SET_PARAMETER softecc false
36	SET_PARAMETER Use_Error_Injection_Pins false
37	SET_PARAMETER Error_Injection_Type Single_Bit_Error_Injection
38	SET_PARAMETER Use_Byte_Write_Enable true
39	SET_PARAMETER Byte_Size 8
40	SET_PARAMETER Algorithm Minimum_Area
41	SET_PARAMETER Primitive 8kx2
42	SET_PARAMETER Assume_Synchronous_Clk false
43	SET_PARAMETER Write_Width_A 8
44	SET_PARAMETER Write_Depth_A 4096
45	SET_PARAMETER Read_Width_A 8
46	SET_PARAMETER Operating_Mode_A WRITE_FIRST
47	SET_PARAMETER Enable_A Use_ENA_Pin
48	SET_PARAMETER Write_Width_B 8
49	SET_PARAMETER Read_Width_B 8
50	SET_PARAMETER Operating_Mode_B WRITE_FIRST
51	SET_PARAMETER Enable_B Use_ENB_Pin
52	SET_PARAMETER Register_PortA_Output_of_Memory_Primitives false
53	SET_PARAMETER Register_PortA_Output_of_Memory_Core false
54	SET_PARAMETER Use_REGCEA_Pin false
55	SET_PARAMETER Register_PortB_Output_of_Memory_Primitives false
56	SET_PARAMETER Register_PortB_Output_of_Memory_Core false
57	SET_PARAMETER Use_REGCEB_Pin false
58	SET_PARAMETER register_porta_input_of_softecc false
59	SET_PARAMETER register_portb_output_of_softecc false
60	SET_PARAMETER Pipeline_Stages 0
61	SET_PARAMETER Load_Init_File false
62	SET_PARAMETER Coe_File no_coe_file_loaded
63	SET_PARAMETER Fill_Remaining_Memory_Locations false
64	SET_PARAMETER Remaining_Memory_Locations 0
65	SET_PARAMETER Use_RSTA_Pin false
66	SET_PARAMETER Reset_Memory_Latch_A false
67	SET_PARAMETER Reset_Priority_A CE
68	SET_PARAMETER Output_Reset_Value_A 0
69	SET_PARAMETER Use_RSTB_Pin false
70	SET_PARAMETER Reset_Memory_Latch_B false
71	SET_PARAMETER Reset_Priority_B CE
72	SET_PARAMETER Output_Reset_Value_B 0
73	SET_PARAMETER Reset_Type SYNC
74	SET_PARAMETER Additional_Inputs_for_Power_Estimation false
75	SET_PARAMETER Port_A_Clock 100
76	SET_PARAMETER Port_A_Write_Rate 50
77	SET_PARAMETER Port_B_Clock 100
78	SET_PARAMETER Port_B_Write_Rate 0
79	SET_PARAMETER Port_A_Enable_Rate 100
80	SET_PARAMETER Port_B_Enable_Rate 100
81	SET_PARAMETER Collision_Warnings ALL
82	SET_PARAMETER Disable_Collision_Warnings false
83	SET_PARAMETER Disable_Out_of_Range_Warnings false
84	SET_CORE_NAME Block Memory Generator
85	SET_CORE_VERSION 6.2
86	SET_CORE_VLNV xilinx.com:ip:blk_mem_gen:6.2
87	SET_CORE_CLASS com.xilinx.ip.blk_mem_gen_v6_2.blk_mem_gen_v6_2
88	SET_CORE_PATH C:/Xilinx/13.3/ISE_DS/ISE/coregen/ip/xilinx/primary/com/xilinx/ip/blk_mem_gen_v6_2
89	SET_CORE_GUIPATH C:/Xilinx/13.3/ISE_DS/ISE/coregen/ip/xilinx/primary/com/xilinx/ip/blk_mem_gen_v6_2/gui/blk_mem_gen_v6_2.tcl
90	SET_CORE_DATASHEET C:\Xilinx\13.3\ISE_DS\ISE\coregen\ip\xilinx\primary\com\xilinx\ip\blk_mem_gen_v6_2\doc\blk_mem_gen_ds512.pdf
91	ADD_CORE_DOCUMENT <C:\Xilinx\13.3\ISE_DS\ISE\coregen\ip\xilinx\primary\com\xilinx\ip\blk_mem_gen_v6_2\doc\blk_mem_gen_ds512.pdf><blk_mem_gen_ds512.pdf>
92	ADD_CORE_DOCUMENT <C:\Xilinx\13.3\ISE_DS\ISE\coregen\ip\xilinx\primary\com\xilinx\ip\blk_mem_gen_v6_2\doc\blk_mem_gen_v6_2_vinfo.html><blk_mem_gen_v6_2_vinfo.html>

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