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CORE_MPI.vhd @ 142

Last change on this file since 142 was 142, checked in by rolagamo, 10 years ago

File size: 33.1 KB

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1	----------------------------------------------------------------------------------
2	-- Company:
3	-- Engineer: GAMOM NGOUNOU
4	--
5	-- Create Date: 05:52:25 06/21/2011
6	-- Design Name:
7	-- Module Name: CORE_MPI - Behavioral
8	-- Project Name:
9	-- Target Devices:
10	-- Tool versions:
11	-- Description:
12	--
13	-- Dependencies:
14	--
15	-- Revision:
16	-- Revision 0.01 - File Created
17	-- Additional Comments:
18	--
19	----------------------------------------------------------------------------------
20	library IEEE;
21	Library NocLib;
22	use IEEE.STD_LOGIC_1164.ALL;
23	use IEEE.STD_LOGIC_ARITH.ALL;
24	use IEEE.STD_LOGIC_UNSIGNED.ALL;
25	use NocLib.CoreTypes.all;
26	---- Uncomment the following library declaration if instantiating
27	---- any Xilinx primitives in this code.
28	--library UNISIM;
29	--use UNISIM.VComponents.all;
30
31	entity CORE_MPI is
32	Port (
33	clk : in STD_LOGIC;
34	reset : in STD_LOGIC;
35	clkout : out std_logic;
36	instruction : in STD_LOGIC_VECTOR (Word-1 downto 0);
37	instruction_en : in STD_LOGIC; --valide l'instruction
38	instruction_fifo_full : out STD_LOGIC;
39	ram_data_in : out STD_LOGIC_VECTOR (Word-1 downto 0);
40	barrier_completed : out STD_LOGIC;
41	packet_received : out STD_LOGIC;
42	packet_ack : in std_logic;
43	PushOut : out STD_LOGIC_VECTOR (Word-1 downto 0); --le resultat de l'exécution
44	ram_we : out STD_LOGIC;
45	ram_en : out STD_LOGIC;
46	ram_address_rd : out STD_LOGIC_VECTOR (15 downto 0);
47	ram_address_wr : out STD_LOGIC_VECTOR (15 downto 0);
48	ram_data_out : in STD_LOGIC_VECTOR (Word-1 downto 0);
49	hold_req : out STD_Logic; --requete vers application
50	hold_ack : in STD_Logic; --autorisation par l'application
51	switch_port_in_cmd_en : out std_logic;
52	switch_port_out_data : in STD_LOGIC_VECTOR (Word-1 downto 0);
53	switch_port_in_wr_en : out STD_LOGIC;
54	switch_port_in_full : in STD_LOGIC;
55	switch_port_in_data : out STD_LOGIC_VECTOR (Word-1 downto 0);
56	switch_port_out_rd_en : out STD_LOGIC;
57	switch_port_in_empty : in STD_LOGIC;
58	switch_port_out_data_vailaible : in STD_LOGIC
59	);
60
61	end CORE_MPI;
62
63	architecture Structural of CORE_MPI is
64	--déclaration des types
65	type Type_Noc is
66	record
67	port_in_cmd_en : std_logic;
68	port_out_data : STD_LOGIC_VECTOR (Word-1 downto 0);
69	port_in_wr_en : STD_LOGIC;
70	port_in_empty : STD_LOGIC;
71	port_in_full : STD_LOGIC;
72	port_in_data : STD_LOGIC_VECTOR (Word-1 downto 0);
73	port_out_rd_en : STD_LOGIC;
74	port_out_data_available : STD_LOGIC;
75	end record;
76	-- déclaration des composants MPI
77
78	COMPONENT FIFO_64_FWFT
79	PORT(
80	clk : IN std_logic;
81	din : IN std_logic_vector(Word-1 downto 0);
82	rd_en : IN std_logic;
83	srst : IN std_logic;
84	wr_en : IN std_logic;
85	dout : OUT std_logic_vector(Word-1 downto 0);
86	empty : OUT std_logic;
87	full : OUT std_logic
88	);
89	END COMPONENT;
90	COMPONENT load_instr
91	Port ( Instruction : in STD_LOGIC_VECTOR (Word-1 downto 0);
92	Instruction_en : in STD_LOGIC;
93	clk : in STD_LOGIC;
94	reset : in STD_LOGIC;
95	dma_rd_grant : in STD_LOGIC;
96	dma_rd_request : out STD_LOGIC;
97	instruction_ack : out STD_LOGIC;
98	fifo_din : out STD_LOGIC_VECTOR (Word-1 downto 0);
99	fifo_wr :out std_logic;
100	fifo_full : in STD_LOGIC;
101	copying : out std_logic;
102	Ram_rd_en : out STD_LOGIC;
103	ram_address_rd : out STD_LOGIC_VECTOR (ADRLEN-1 downto 0);
104	ram_data : in STD_LOGIC_VECTOR (WORD-1 downto 0));
105	end component;
106	COMPONENT DMA_ARBITER
107	PORT(
108
109	clk : IN std_logic;
110	reset : IN std_logic;
111	dma_rd_request : IN std_logic_vector(3 downto 0);
112	data_wr_in : IN std_logic_vector(Word-1 downto 0);
113	data_rd_out : out std_logic_vector(Word-1 downto 0);
114	address_rd : IN std_logic_vector(15 downto 0);
115	address_wr : IN std_logic_vector(15 downto 0);
116
117	dma_wr_request : IN std_logic_vector(3 downto 0);
118	address_out_rd : OUT std_logic_vector(15 downto 0);
119	address_out_wr : OUT std_logic_vector(15 downto 0);
120	ram_en : OUT std_logic;
121	ram_we : OUT std_logic;
122	hold_req : out STD_Logic; --requete vers application
123	hold_ack : in STD_Logic; --autorisation par l'application
124	data_wr_mem : OUT std_logic_vector(Word-1 downto 0);
125	data_rd_mem : IN std_logic_vector(Word-1 downto 0);
126	dma_wr_grant : OUT std_logic_vector(3 downto 0);
127	dma_rd_grant : OUT std_logic_vector(3 downto 0)
128	);
129	END COMPONENT;
130
131	COMPONENT EX1_FSM
132	PORT(
133	clk : IN std_logic;
134	reset : IN std_logic;
135
136	pid : in std_logic_vector (3 downto 0); --port id
137	nprocs : in std_logic_vector (3 downto 0); -- la taille du Noc
138	instruction : in std_logic_vector(Word-1 downto 0);
139	instruction_en : in std_logic;
140	fifo_empty : IN std_logic;
141	fifo_data_out : IN std_logic_vector(Word-1 downto 0);
142	fifo_rd_en : OUT std_logic;
143	fifo_src : IN STD_LOGIC;
144	ram_data_in : IN std_logic_vector(Word-1 downto 0);
145	ram_data_out : out std_logic_vector(Word-1 downto 0);
146	dma_rd_grant : IN std_logic;
147	dma_wr_grant : IN std_logic;
148	dma_wr_request : OUT std_logic;
149	dma_rd_request : OUT std_logic;
150	ram_address : OUT std_logic_vector(15 downto 0);
151	ram_rd,ram_wr : out std_logic;
152	Snd_Data : IN Typ_PortIO(0 to 3);
153	Snd_Start : IN std_logic;
154	Snd_Ack : OUT std_logic;
155	priority_rotation : OUT std_logic;
156
157	switch_port_in_data : OUT std_logic_vector(Word-1 downto 0);
158	switch_port_in_wr_en : OUT std_logic;
159	switch_port_in_full : IN std_logic;
160	Result :out std_logic_vector(Word-1 downto 0);
161	Ready : out std_logic;
162	AppInitReq :out STD_LOGIC; -- requête d'initialisation de l'application
163	AppInitAck :in STD_LOGIC; -- Acquitement d'initialisation
164	Initialized:in std_logic -- état de la Lib
165	);
166	END COMPONENT;
167
168	COMPONENT EX2_FSM
169	PORT(
170	clk : IN std_logic;
171	reset : IN std_logic;
172
173	instruction_en: in std_logic;
174	Initialized : in std_logic;
175
176	switch_port_out_rd_en : OUT std_logic ;
177	switch_data_available : IN std_logic;
178	switch_port_out_data : IN std_logic_vector(Word-1 downto 0);
179	AppRank : in STD_LOGIC_VECTOR;
180	AppSize : in STD_LOGIC_VECTOR;
181	dma_wr_grant : IN std_logic;
182	dma_wr_request : OUT std_logic;
183	dma_rd_grant : IN std_logic;
184	dma_rd_request : OUT std_logic;
185	ram_address : OUT std_logic_vector(15 downto 0);
186	ram_rd,ram_wr : out std_logic;
187	Ram_data_out : in STD_LOGIC_VECTOR (Word-1 downto 0);
188	Ram_data_in : out STD_LOGIC_VECTOR (Word-1 downto 0);
189	fifo_full : IN std_logic;
190	Rec_Rdy : OUT std_logic;
191	Rec_Data : out Typ_PortIO(0 to 3);
192	Rec_Ack : IN std_logic;
193	fifo_data : OUT std_logic_vector(Word-1 downto 0);
194	fifo_wr_en : OUT std_logic;
195	--fifo_out : out std_logic_vector;
196	Result : out STD_LOGIC_VECTOR (Word-1 downto 0);
197	packet_received : OUT std_logic;
198	packet_ack : IN std_logic;
199	barrier_completed : OUT std_logic;
200	Ready : Out std_logic;
201	AppInitAck : in std_logic;
202	AppInitReq : out std_logic
203	);
204	END COMPONENT;
205
206
207	COMPONENT EX3_FSM
208	PORT(
209	instruction : IN std_logic_vector(Word-1 downto 0);
210	clk : IN std_logic;
211	reset : IN std_logic;
212	Ismain :in std_logic;
213	ResOut : OUT std_logic_vector(Word-1 downto 0)
214
215	);
216	END COMPONENT;
217
218	COMPONENT EX4_FSM
219	PORT(
220	Instruction : in STD_LOGIC_VECTOR (Word-1 downto 0); --permet de lire le FIFO
221	Instruction_En : in STD_LOGIC;
222	clk : in STD_LOGIC;
223	reset : in STD_LOGIC;
224	ResultOut : out STD_LOGIC_VECTOR (Word-1 downto 0);
225	Result_En : out STD_LOGIC;
226	Ready : out STD_LOGIC;
227	NocSize : out STD_LOGIC_VECTOR;
228	AppRank : out STD_LOGIC_VECTOR;
229	AppSize : out STD_LOGIC_VECTOR;
230	IsMain : out STD_LOGIC;
231	I_fifo_full :in STD_LOGIC;
232	Snd_Ack : IN std_logic;
233	Rec_Rdy : IN std_logic;
234	Rec_Data : IN Typ_PortIO(0 to 3);
235	Snd_data : OUT Typ_PortIO(0 to 3);
236	Snd_Start : out std_logic;
237	Rec_Ack : OUT std_logic;
238	I_fifo_wr_en: out STD_LOGIC;
239	I_fifo_data_in :out STD_LOGIC_vector(Word-1 downto 0);
240	Initialized : out STD_LOGIC;
241	dma_wr_request : out std_logic;
242	dma_rd_request : out std_logic;
243	dma_wr_grant : in std_logic;
244	dma_rd_grant : in std_logic;
245	Ram_address : out STD_LOGIC_VECTOR (15 downto 0); --accès au stockage
246	Ram_wr : out STD_LOGIC; --activation de l'écriture en RAM
247	Ram_Data_in : out STD_LOGIC_VECTOR (Word-1 downto 0);--données des ports
248	Ram_data_out : in STD_LOGIC_VECTOR (Word-1 downto 0);
249	AppAck : in STD_LOGIC;
250	AppReq : in STD_LOGIC;
251	PortId : out STD_LOGIC_VECTOR(3 downto 0);
252	port_in_cmd_en : out STD_LOGIC;
253	port_in_wr_en : out STD_LOGIC;
254	port_in_empty : in STD_LOGIC;
255	port_in_full : in STD_LOGIC;
256	port_in_data : out STD_LOGIC_VECTOR (Word-1 downto 0);
257	port_out_data : in STD_LOGIC_VECTOR (Word-1 downto 0);
258	port_out_rd_en : out STD_LOGIC;
259	port_out_data_available : in STD_LOGIC);
260	END COMPONENT;
261
262	COMPONENT EX0_FSM
263	PORT(
264	clk : in STD_LOGIC;
265	reset : in STD_LOGIC;
266
267	Initialized : in STD_LOGIC;
268	Instruction : in STD_LOGIC_VECTOR (Word-1 downto 0);
269	instruction_en: in STD_LOGIC;
270
271	ClkRate : in STD_LOGIC_VECTOR ;
272	uTimeResult : out STD_LOGIC_VECTOR;
273	TickResult : out STD_LOGIC_VECTOR
274	);
275	END COMPONENT;
276
277
278	COMPONENT MPI_CORE_SCHEDULER
279	PORT(
280	clk : IN std_logic;
281	reset : IN std_logic;
282	priority_rotation : IN std_logic;
283	instruction_fifo_empty : IN std_logic;
284	instruction_fifo_rd_en : OUT std_logic;
285	instruction_fifo_data : IN std_logic_vector(Word-1 downto 0);
286	instruction_available : OUT std_logic;
287
288	get_request_fifo_empty : IN std_logic;
289	get_request_fifo_rd_en : OUT std_logic;
290	get_request_fifo_data : IN std_logic_vector(Word-1 downto 0);
291
292	fifo_rd_en : IN std_logic;
293	fifo_empty : OUT std_logic;
294	fifo_selected : OUT std_logic;
295
296	data_out : OUT std_logic_vector(Word-1 downto 0)
297
298
299	);
300	END COMPONENT;
301
302	-- declaration des signaux d'interconnexion entre les modules du coresignal fifo_sel: std_logic; -- indique l'un des deux fifos d'instructions qui sont prêts
303	signal fifo_instr : std_logic; -- une instruction est prête dans les fifos d'instruction
304
305
306	signal scheduler_fifo_empty : std_logic;
307	signal scheduler_data_out : std_logic_vector(Word-1 downto 0);
308	signal dma_arbiter_data_rd_out : std_logic_vector(Word-1 downto 0);
309
310	signal scheduler_priority_rotation : std_logic;
311	signal scheduler_rd_en : std_logic;
312
313	signal dma_data_rd,dma_data_wr : std_logic_vector(Word-1 downto 0); -- bus à 3 états
314	signal dma_rd_address,dma_rd_address1,dma_rd_address2 : std_logic_vector(15 downto 0); -- ces bus doivent être gérés en logique 3 états!
315	signal dma_rd_address3 : std_logic_vector(15 downto 0);
316	signal dma_wr_address1,dma_wr_address3 : std_logic_vector(15 downto 0);
317	signal dma_wr_address2,dma_wr_address4 : std_logic_vector(15 downto 0);
318	signal dma_wr_address : std_logic_vector(15 downto 0);
319	signal switch_port_in_data_signal : std_logic_vector(Word-1 downto 0);
320	signal ram_data_out_signal : std_logic_vector(Word-1 downto 0);
321	signal weram,rdram,ram_wev,ram_env :std_logic:='0';
322
323	signal i_fifo2_signal : std_logic_vector(Word-1 downto 0);
324	signal Ex_EN : std_logic_vector(4 downto 1):=(others=>'0'); --active les sous MAE permettant de décoder les instructions MPI
325	signal Res4_en:std_logic;--acquittement du réusltat du module n°4
326	signal Ex4_en,Ex1_RDY,Ex2_RDY,EX3_RDY,EX4_RDY : std_logic:='0'; -- indique la fin de l'exécution de la MAE
327	signal ex1_ram_rd,ex2_ram_rd,ex4_ram_rd ,Exi_ram_rd: std_logic:='0' ; -- validation lecture des données en RAM
328	signal ex1_ram_wr,ex2_ram_wr,ex4_ram_wr,Exi_ram_wr : std_logic :='0'; -- validation écriture des données en RAM
329	signal Exi_busy : std_logic:='0';
330	signal Ex1_Result,Ex2_Result,Ex4_result : std_logic_vector(Word-1 downto 0);
331	signal Instr_in : STD_LOGIC_VECTOR (Word-1 downto 0);
332	--================interface DMA avec les modules ======================================
333	signal dma_data_in,Dma_data_in1,dma_data_in2,dma_data_in4 : std_logic_vector(Word-1 downto 0);
334	signal dma_data_out : std_logic_vector(Word-1 downto 0);
335	signal dma_rd_request :std_logic_vector(4 downto 1):=(others=>'0');
336	signal dma_wr_request :std_logic_vector(4 downto 1):=(others=>'0');
337	signal dma_wr_grant,dma_rd_grant:std_logic_vector(4 downto 1);
338	--
339	--======================================================================================
340	--connexion au switch
341
342	signal Noc1,NOC2,NOC3 : Type_Noc; -- regroupement des signaux qui vont au Noc
343
344	--================================================================
345	--déclaration des signaux d'état du Core
346	signal IsMain,SizeSet,RankSet,Initialized,AppReq,AppAck:std_logic;
347	signal InitReq,InitReq1,InitReq2 :std_logic:='0'; -- demande d'initialisation
348	signal InitAck,IAck,Ilatch : std_logic:='0';
349	signal MPISize,MyRank : std_logic_vector(3 downto 0);
350	signal LibState: std_logic_vector(Word-1 downto 0):=(others=>'0'); --ready,receiving,sending,spawning,rwaiting,swaiting,...
351	signal NocSize :std_logic_vector(3 downto 0):=(others=>'0');
352	Signal PortId : std_logic_vector(3 downto 0);
353	Signal uClkRate : std_logic_vector(Word-1 downto 0):="00011010"; --50 Mhz
354	signal uTimeCount :std_logic_vector(31 downto 0):=(others=>'0');
355	signal TickCount : std_logic_vector(31 downto 0):=(others=>'0');
356	signal RankSize: std_logic_vector(Word-1 downto 0):=(others=>'0');
357	--========================================================
358	--déclaration des signaux permettant d'activer le module
359	signal AdrSelect : std_logic_vector(ADRLEN-1 downto 0);
360	--========================================================
361	--signal PushOut_d,RankSize,TickUsOut:std_logic_vector; --résultat de l'execution des commandes mpi
362	--========================================================
363	--connexion avec les FIFO instructions
364	signal fifo1_wr : std_logic;
365	signal fifo1_din : std_logic_vector (Word-1 downto 0);
366	signal fifo_sel : std_logic; --permet d'arbitrer la priorité de lecture entre les deux fifos
367	signal i_fifo1_rd_en : std_logic;
368	signal fifo1_full : std_logic;
369	signal i_fifo1_empty : std_logic;
370	signal i_fifo1_data_out : std_logic_vector(Word-1 downto 0);
371	signal i_fifo2_rd_en : std_logic;
372	signal i_fifo2_data_out : std_logic_vector(Word-1 downto 0);
373	signal i_fifo2_data_in : std_logic_vector(Word-1 downto 0);
374	signal i_fifo2_wr_en : std_logic;
375	signal i_fifo2_empty : std_logic;
376	signal i_fifo2_full : std_logic;
377	signal Ex2_i_fifo2_data_in : std_logic_vector(Word-1 downto 0):=(others=>'0');
378	signal Ex2_i_fifo2_wr_en : std_logic:='0';
379	--signaux pour les données entre modules
380	signal Snd_Ack :std_logic;
381	signal Rec_Rdy : std_logic;
382	signal Rec_Data : Typ_PortIO(0 to 3);
383	signal Snd_data : Typ_PortIO(0 to 3);
384	signal Snd_Start : std_logic;
385	signal Rec_Ack : std_logic;
386	--signal i_fifo2_empty : std_logic;
387	--signal i_fifo2_full : std_logic;
388	signal Ex4_i_fifo2_data_in : std_logic_vector(Word-1 downto 0):=(others=>'0');
389	signal Ex4_i_fifo2_wr_en : std_logic:='0';
390	--signal i_fifo2_empty : std_logic;
391	--signal i_fifo2_full : std_logic;
392	-- signaux pour la gestion des MAE
393	signal n,n_i :natural range 0 to 7:=0;
394	signal St_Ex1,St_Ex2,St_Ex4:natural range 0 to 7:=0;
395	signal Next_St_Ex1,Next_St_Ex2,Next_St_Ex4:natural range 0 to 7:=0;
396	--===========================================================
397
398	begin
399	--switch_port_in_data_signal <= ;
400	--switch_port_out_data_signal <= ;
401	-- istanciation des composants du core MPI
402	Instruction_Fifo1: FIFO_64_FWFT PORT MAP(
403	clk =>clk,
404	din =>fifo1_din,
405	rd_en => i_fifo1_rd_en,
406	srst => reset,
407	wr_en => fifo1_wr,
408	dout =>i_fifo1_data_out,
409	empty => i_fifo1_empty,
410	full => fifo1_full
411	);
412
413	Instruction_Fifo2: FIFO_64_FWFT PORT MAP(
414	clk =>clk,
415	din => i_fifo2_data_in ,
416	rd_en =>i_fifo2_rd_en,
417	srst =>reset,
418	wr_en =>i_fifo2_wr_en,
419	dout =>i_fifo2_data_out,
420	empty =>i_fifo2_empty,
421	full => i_fifo2_full
422	);
423	LD_instr:load_instr PORT MAP (
424
425	Instruction =>Instruction,
426	Instruction_en =>Instruction_en,
427	clk =>clk,
428	reset =>reset,
429	dma_rd_grant =>dma_rd_grant(3),
430	dma_rd_request =>dma_rd_request(3),
431	copying=> Exi_busy,
432	instruction_ack =>iack, --indique la fin de la copie d'une instruction dans le FIFO
433	fifo_din => fifo1_din,
434	fifo_wr => fifo1_wr,
435	fifo_full =>fifo1_full,
436	Ram_rd_en=> Exi_ram_rd,
437	ram_address_rd => dma_rd_address3,
438	ram_data =>dma_data_out --sortie DMA
439	);
440
441	pushout(0)<=ILatch;
442	pushout(1)<=IsMain;
443	pushout(2)<=SizeSet;
444	pushout(3)<=Ex4_result(6); --Spawn in progress on main
445	pushout(4)<=Initialized;
446	pushout(5)<=Ex1_result(1); --
447	pushout(6)<=LibState(3); --Spawned child
448	pushout(7)<=Ex4_result(7); --Spawn complete
449	MPI_CORE_EX0_FSM: EX0_FSM PORT MAP(
450	instruction => i_fifo1_data_out,
451	instruction_en=> '1',
452	uTimeResult => uTimeCount,
453	TickResult => TickCount,
454	Initialized => Initialized, -- indique si la l'appel à init a été concluant
455	ClkRate => uClkRate,
456	clk =>clk ,
457	reset => reset
458	);
459	MPI_CORE_EX1_FSM: EX1_FSM PORT MAP(
460	clk =>clk ,
461	reset =>reset,
462	pid => MyRank, --port Id
463	nprocs=>MPISize, -- à revoir dans certains cas ou tous les PEs ne sont pas connectés
464	fifo_empty => scheduler_fifo_empty ,
465	fifo_data_out =>scheduler_data_out,
466	fifo_rd_en =>scheduler_rd_en,
467	fifo_src =>fifo_sel,
468	priority_rotation => scheduler_priority_rotation,
469
470	instruction_en=>Ex_en(1), --active le module
471	Instruction => Instruction,
472	switch_port_in_full =>Noc1.port_in_full, --ces signaux doivent être contrôlés en 3 state logic
473	switch_port_in_data =>Noc1.port_in_data,
474	switch_port_in_wr_en =>Noc1.Port_in_wr_en ,
475
476	Snd_Data =>Snd_Data,
477	Snd_Start =>Snd_start,
478	Snd_Ack =>Snd_ack,
479	Ram_rd => ex1_ram_rd,
480	Ram_wr =>ex1_ram_wr,
481	ram_data_in =>dma_data_out,
482	Ram_data_out =>dma_data_in1,
483	ram_address=>dma_wr_address1,
484	--ram_address =>dma_rd_address2, --la même adresse sert pour la lecture ou l'écriture
485	dma_rd_request =>dma_rd_request(1),
486	dma_wr_request =>dma_wr_request(1),
487	dma_rd_grant =>dma_rd_grant(1) ,
488	dma_wr_grant =>dma_wr_grant(1) ,
489
490	AppInitReq => InitReq1, -- requête d'initialisation de l'application
491	AppInitAck =>Res4_En , -- Acquitement d'initialisation
492	Initialized=>Initialized, -- état de la Lib
493	Result => Ex1_Result, -- le résultat de l'exécution
494	Ready=> Ex1_Rdy
495	);
496	instruction_fifo_full<=fifo1_full;
497	dma_rd_address1<=dma_wr_address1; --la même adresse sert pour la lecture ou l'écriture en RAM
498	Exi_sync :process(reset,clk)
499
500	begin
501	if rising_edge(clk) then
502	if reset='1' then
503	St_Ex2<=0;
504	St_Ex1<=0;
505	St_Ex4<=0;
506	Ilatch<='0';
507	n<=0;
508	else
509	St_Ex2<=Next_St_Ex2;
510	St_Ex1<=Next_St_Ex1;
511	St_Ex4<=Next_St_Ex4;
512	ILatch<=Iack;
513	n<=n_i;
514	end if;
515	end if;
516	End process Exi_sync;
517	-- détermination de l'activation des module
518	--scheduler_priority_rotation<=not(Ex1_rdy);
519	Ex1_Act:process(ST_Ex1,Initialized,reset,fifo_instr,n,InitReq,Ex4_rdy,Ex1_rdy,Ex2_rdy)--A qoui sert encore ce processus (26/10/12) ????
520	variable c_cyl:natural range 0 to 15:=0;
521	begin
522	if reset='1' then
523	Next_St_ex1<=0;
524	c_cyl:=0;
525	else -- cette machie à état permet de distinguer les activations de Ex4 et Ex1
526	Next_St_ex1<=ST_EX1;
527	case St_ex1 is
528	when 0 => if InitReq='1' and Initialized='0' then
529	Next_St_ex1<=1;
530	elsif Initialized='1' then
531	Next_St_ex1 <=2;
532	elsif fifo_instr='1' then --cas d'une instruction directe qui est présente
533	--if fifo_sel='0' then
534	Next_St_ex1 <=2;
535	--end if;
536	end if;
537
538	when 1 => if Ex4_Rdy='1' then
539	Next_St_ex1<=4;
540	end if;
541	when 2 => if Ex1_rdy='0' then --ex1 est libre et actif
542	Next_St_ex1<=3;
543	end if;
544
545	when 3 => if Ex1_rdy='1' and Initialized='0'then --ex1 est occupé et actif
546	Next_St_ex1<=0;
547	elsif Ex1_rdy='1' and Initialized='1' then
548	Next_St_ex1<=2;
549	end if;
550
551	when 4 => if Ex2_rdy='0' then --s'il y a un message du réseau
552	--compter quelques cycles d'horloges pour attendre initreq2
553	if n=4 then
554	Next_St_ex1<=0;
555	n_i<=0;
556	else
557	n_i<=n+1;
558	end if;
559	else
560	Next_St_ex1<=0;
561	end if;
562
563	when others =>
564	Next_St_ex1<=0;
565	end case;
566	end if;
567	end process ex1_Act;
568
569	ex1_v:process(St_Ex1)
570	begin
571	case St_Ex1 is
572	when 0 =>
573	Ex_en(1)<='0';
574	when 1 =>
575	Ex_en(1)<='0';
576	when 2\|3 =>
577	Ex_en(1)<='1';
578	when others =>
579	Ex_en(1)<='0';
580	end case;
581
582	end process ex1_v;
583
584	Ex2_nextState:Process(reset,st_Ex2, Ex4_rdy,Initialized,Ex2_Result,Ex2_rdy) --active la réception lorsqu' Put ou un Get ou un Init a été effectué
585	begin
586	Next_St_Ex2<=st_Ex2;
587	Case st_Ex2 is
588
589	when 0 =>
590	if Initialized='1' and Ex4_rdy='1' then --- Ex1_result(0)='1' or Ex1_result(1)='1' or Ex1_result(2)='1' then
591	Next_St_Ex2<=1; --active la réception des mesages sur le noeud.
592
593	else
594	Next_St_Ex2<=0;
595	end if;
596	When 1 =>
597	if Ex2_rdy='0' then
598	Next_St_Ex2<=2;
599	end if;
600	When 2 =>
601	if Ex2_rdy='1' then
602	Next_St_Ex2<=0;
603	end if;
604	when others =>
605	Next_St_Ex2<=0;
606	end case;
607	end process;
608	Ex2_val:Process(st_Ex2,Ex4_result,reset) --
609
610	begin
611	Case st_Ex2 is
612
613	when 0 =>
614	Ex_en(2)<='0';
615	--LibState(3)<='0';
616	when 1\|2 =>
617	Ex_en(2) <='1';
618	when 3\|4\|5\|6\|7 =>
619	Ex_en(2)<='0';
620	when others=>
621	Ex_en(2)<='0';
622	end case;
623	if rising_edge(Ex4_result(1)) then
624	LibState(3)<='1'; --spawn a été détecté.
625	elsif reset='1' then
626	LibState(3)<='0';
627	end if;
628	end process;
629
630	Ex_en_proc:process (clk,reset)
631	begin
632	if rising_edge(clk) then
633	if reset='1' then
634	Ex4_en<='0';
635	else
636
637	if Ex_en(4)='1' then
638	Ex4_en<='1'; --synchro
639	else
640	Ex4_en<='0'; --synchro
641	end if;
642	end if;
643	end if;
644	end process;
645	Ex4_Active:process (St_Ex4,initreq1,initreq2,Ex1_rdy,Initialized,Res4_en)
646	begin
647
648	case St_Ex4 is
649	when 0 =>
650	if (InitReq1='1') then
651	Next_St_Ex4<=1;
652	elsif InitReq2='1' then --le module 1 n'est pas actif
653	Next_St_Ex4<=2;
654	else
655	Next_St_Ex4<=0;
656	end if;
657	when 1 =>
658	If Res4_en='1' then --fin de l'exécution du module
659	Next_St_Ex4<=3;
660	end if;
661	when 2 =>
662	if Res4_en='1' then --Ex2_result(0)='1'
663	Next_St_Ex4<=4;
664	end if;
665	when 3 =>
666	if initreq1='0' then
667	Next_St_Ex4<=5;
668	end if;
669	when 4 =>
670	if initreq2='0' then
671	Next_St_Ex4<=5;
672	end if;
673	when 5 =>
674	Next_St_Ex4<=0;
675	when others =>
676	Next_St_Ex4<=0;
677	end case;
678
679	end process Ex4_active;
680
681	Ex4_active_val:process (st_Ex4)
682	begin
683	case St_Ex4 is
684	when 0 =>
685	AppReq<='0';
686	InitReq<='0';Ex_en(4)<='0';
687	AppAck<='0';
688	when 1 =>
689	AppReq<='1';
690	InitReq<='1';
691	Ex_en(4)<='1';
692	AppAck<='0';
693	when 2 =>
694	AppReq<='1';
695	InitReq<='1';
696	Ex_en(4)<='1';
697	AppAck<='0';
698	when 3 =>
699	AppReq<='0';
700	InitReq<='0';
701	Ex_en(4)<='0';
702	AppAck<='1';
703	when 4 =>
704	AppReq<='0';
705	InitReq<='0';
706	Ex_en(4)<='0';
707	AppAck<='1';
708	when 5 =>
709	AppReq<='0';
710	InitReq<='0';Ex_en(4)<='0';
711	AppAck<='1';
712	when others =>
713	AppReq<='0';
714	InitReq<='0';
715	AppAck<='0';
716	Ex_en(4)<='0';
717	end case ;
718	-- Appreq<=Ex_en(4); --signal d'activation de la MAE Init
719	--InitReq<=(not(Initialized) and InitReq1) or InitReq2; -- deux cas permettent d'activer l'initialisation
720	--AppAck<=Ex1_result(0) or Ex2_result(0); -- signal init completed
721	end process Ex4_active_val;
722	--Ex_en(2)<=Initialized; --- Me pose des soucis en ce moment ???
723	Ex_en(3)<='0';
724	--Ex_en(4)<= '1' when InitReq='1' else '0';
725
726	-- soit une requête du PE soit une requête du Core
727
728
729	MPI_CORE_EX2_FSM: EX2_FSM PORT MAP(
730
731	clk =>clk,
732	reset =>reset,
733	instruction_en=>Ex_en(2),
734	Ready =>Ex2_rdy, --signale que le module est disponible
735	fifo_full =>i_fifo2_full,
736
737	fifo_wr_en => Ex2_i_fifo2_wr_en,
738	fifo_data => Ex2_i_fifo2_data_in,
739
740	switch_port_out_rd_en => Noc2.port_out_rd_en,
741	switch_data_available =>Noc2.port_out_data_available,
742	switch_port_out_data =>Noc2.port_out_data ,
743
744	Rec_Rdy => Rec_Rdy,
745	Rec_Data =>Rec_Data,
746	Rec_Ack =>Rec_Ack,
747	-- il manque un signal pour valider l'accès à la RAM
748	dma_wr_request =>dma_wr_request(2),
749	dma_wr_grant =>dma_wr_grant(2),
750	dma_rd_request =>dma_rd_request(2),
751	dma_rd_grant =>dma_rd_grant(2),
752	ram_address =>dma_wr_address2,
753	Ram_rd => ex2_ram_rd,
754	Ram_wr =>ex2_ram_wr,
755	Ram_data_out=> Dma_data_out,
756	Ram_data_in => Dma_data_in2,
757	packet_received =>packet_received,
758	packet_ack => packet_ack,
759	barrier_completed =>barrier_completed,
760	AppRank =>MyRank,
761	AppSize =>MPISize,
762	AppInitReq => InitReq2, -- requête d'initialisation de l'application
763	AppInitAck =>Res4_En , -- Acquitement d'initialisation
764	Initialized=>Initialized,
765	Result => Ex2_Result -- le résultat de l'exécution
766	);
767	Dma_rd_address2<=Dma_wr_address2;
768	ICI_MPI_CORE_EX3_FSM: EX3_FSM PORT MAP(
769	instruction => x"00", --pas utiliser
770	ResOut => RankSize,
771	clk =>clk ,
772	IsMain=>IsMain,
773	reset => reset
774	);
775	MPI_CORE_EX4_FSM :EX4_FSM PORT MAP (
776	Instruction => Instr_in, --STD_LOGIC_VECTOR (Word-1 downto 0);
777	Instruction_En =>Ex4_en, -- ='1' lorsque ce module est sollicité
778	clk =>clk,
779	reset =>reset,
780	ResultOut =>Ex4_Result, --STD_LOGIC_VECTOR (Word-1 downto 0);
781	Result_En =>Res4_En, -- ='1' lorsque fin de l'exécution du module
782	Ready => Ex4_Rdy,
783	NocSize =>NocSize,
784	AppRank =>MyRank,
785	AppSize =>MPISize,
786	IsMain =>IsMain,
787	Rec_Rdy => Rec_Rdy,
788	Rec_Data =>Rec_Data,
789	Rec_Ack =>Rec_Ack,
790	Snd_Ack =>Snd_ack,
791	Snd_data =>Snd_data,
792	Snd_Start =>Snd_Start,
793
794	I_fifo_full =>i_fifo2_full,
795
796	I_fifo_wr_en => Ex4_i_fifo2_wr_en,
797	I_fifo_data_in => Ex4_i_fifo2_data_in,
798	Initialized =>Initialized,
799	Ram_data_out => Dma_data_out,
800	Ram_address =>dma_wr_Address4, --accès au stockage
801	Ram_wr =>Ex4_Ram_wr, --activation de l'écriture en RAM
802	Ram_data_in =>Dma_data_in4, --données à écrire en RAM
803	DMA_rd_Request => dma_rd_request(4),
804	DMA_rd_grant => dma_rd_grant(4),
805	DMA_wr_Request => dma_wr_request(4),
806	DMA_wr_grant => dma_wr_grant(4),
807	AppAck =>AppAck,
808	AppReq =>InitReq,
809	PortId=>PortId,
810	port_in_cmd_en => Noc3.port_in_cmd_en,
811	port_in_wr_en =>Noc3.port_in_wr_en,
812	port_in_empty =>Noc3.port_in_empty,
813	port_in_full =>Noc3.port_in_full,
814	port_in_data =>Noc3.port_in_data,
815	port_out_data =>Noc3.port_out_data,
816	port_out_rd_en =>Noc3.port_out_rd_en,
817	port_out_data_available =>Noc3.port_out_data_available
818
819
820	);
821	--=============Mux des signaux d'accès à la RAM=========
822	ram_we<='1' when (weram='1' and ram_wev ='1') else '0'; -- le contrôleur DMA contrôle directement
823	Ram_en<= '1' when (rdram ='1' or weram='1') else '0'; -- les signaux qui vont vers la RAM
824
825	--dma_data_in <=dma_data_in1 or dma_data_in2;
826	--dma_data_out <=dma_data_out1 or dma_data_out2;
827	mux_ad_ram_rd:process (dma_rd_grant,dma_rd_address1,dma_rd_address2,dma_rd_address3,
828	ex1_ram_rd, Ex2_ram_rd, Exi_ram_rd )
829	begin
830	case dma_rd_grant is
831	when "0001" => dma_rd_address <= dma_rd_address1;
832	rdram<= ex1_ram_rd;
833	when "0010" => dma_rd_address <= dma_rd_address2;
834	rdram<= ex2_ram_rd;
835	when "0100" => dma_rd_address <= dma_rd_address3;
836	rdram<= exi_ram_rd;
837	-- when "1000" => dma_rd_address <= <input4>;
838	when others => dma_rd_address <= (others =>'0');
839	rdram<='0';
840	end case;
841	end process;
842	mux_ad_ram_wr:process (dma_wr_grant,dma_wr_address1,dma_wr_address2,dma_wr_address4,Dma_data_in1,Dma_data_in2,Dma_data_in4,
843	ex1_ram_wr,ex2_ram_wr,ex4_ram_wr)
844	begin
845	case dma_wr_grant is
846
847	when "0001" => dma_wr_address <= dma_wr_address1;
848	weram<=ex1_ram_wr ;
849	Dma_data_in<=Dma_data_in1;
850	when "0010" => dma_wr_address <= dma_wr_address2;
851	weram<=ex2_ram_wr ;
852	Dma_data_in<=Dma_data_in2;
853	when "1000" => dma_wr_address <= dma_wr_address4;
854	weram<=ex4_ram_wr;
855	Dma_data_in<=Dma_data_in4;
856	when others => dma_wr_address <= (others =>'0');
857	weram<='0';
858	end case;
859	end process;
860	--======================================================
861
862	--=================Mux des signaux qui vont au switch============
863	clkout<=clk; -- permettra le lien avec le module du switch
864
865	NOC1.port_out_data<=switch_port_out_data;
866	NOC1.port_out_data_available<=switch_port_out_data_vailaible;
867	NOC1.port_in_empty<=switch_port_in_empty;
868	NOC1.port_in_full<=switch_port_in_full;
869
870	NOC2.port_out_data<=switch_port_out_data;
871	NOC2.port_out_data_available<=switch_port_out_data_vailaible;
872	NOC2.port_in_empty<=switch_port_in_empty;
873	NOC2.port_in_full<=switch_port_in_full;
874
875	NOC3.port_out_data<=switch_port_out_data;
876	NOC3.port_out_data_available<=switch_port_out_data_vailaible;
877	NOC3.port_in_empty<=switch_port_in_empty;
878	NOC3.port_in_full<=switch_port_in_full;
879	mux_Noc:process (Ex_en,Noc1,Noc2,Noc3,switch_port_out_data_vailaible,Initialized,Initreq2,
880	ex2_i_fifo2_wr_en,ex2_i_fifo2_data_in,ex4_i_fifo2_data_in,ex4_i_fifo2_wr_en,
881	instruction,ex2_result)
882
883	begin
884	case Ex_en is
885
886	when"0001" =>
887	switch_port_in_data <=Noc1.port_in_data;
888	switch_port_out_rd_en<=NOC2.port_out_rd_en;
889	switch_port_in_wr_en <=NOC1.port_in_wr_en;
890	switch_port_in_cmd_en <='0';
891	when "0010"\|"0011" =>
892	switch_port_in_data <=Noc1.port_in_data;
893	switch_port_out_rd_en<=NOC2.port_out_rd_en;
894	switch_port_in_wr_en <=NOC1.port_in_wr_en;
895	switch_port_in_cmd_en <='0';
896	i_fifo2_wr_en<=ex2_i_fifo2_wr_en;
897	i_fifo2_data_in<=ex2_i_fifo2_data_in;
898	when"1011" => --ce cas pose problème car on ne sait ce qui se passe !!!
899	if initreq2='1' then
900	switch_port_in_data <=Noc1.port_in_data;
901	switch_port_out_rd_en<=NOC3.port_out_rd_en;
902	switch_port_in_wr_en <=NOC1.port_in_wr_en;
903	switch_port_in_cmd_en <='0';
904	else
905	switch_port_in_data <=Noc1.port_in_data;
906	switch_port_out_rd_en<=NOC2.port_out_rd_en;
907	switch_port_in_wr_en <=NOC1.port_in_wr_en;
908	switch_port_in_cmd_en <='0';
909	end if;
910	i_fifo2_wr_en<=ex2_i_fifo2_wr_en;
911	i_fifo2_data_in<=ex2_i_fifo2_data_in;
912	when "1001" => --ca où un appel à init est effectué
913	if initialized='0' then
914	switch_port_in_data <=Noc3.port_in_data;
915	switch_port_out_rd_en<=NOC3.port_out_rd_en;
916	switch_port_in_wr_en <=NOC3.port_in_wr_en;
917	switch_port_in_cmd_en <=NOC3.port_in_cmd_en;
918	else
919	switch_port_in_data <=Noc1.port_in_data;
920	switch_port_out_rd_en<=NOC3.port_out_rd_en;
921	switch_port_in_wr_en <=NOC1.port_in_wr_en;
922	end if;
923	i_fifo2_wr_en<=ex4_i_fifo2_wr_en;
924	i_fifo2_data_in<=ex4_i_fifo2_data_in;
925	when "1010" => --ca où un appel à init est effectué
926	--switch_port_in_data <=Noc3.port_in_data;
927	-- switch_port_out_rd_en<=NOC3.port_out_rd_en;
928	-- switch_port_in_wr_en <=NOC3.port_in_wr_en;
929	-- switch_port_in_cmd_en <=NOC3.port_in_cmd_en;
930	switch_port_in_data <=Noc1.port_in_data;
931	switch_port_out_rd_en<=NOC3.port_out_rd_en;
932	switch_port_in_wr_en <=NOC1.port_in_wr_en;
933	i_fifo2_wr_en<=ex4_i_fifo2_wr_en;
934	i_fifo2_data_in<=ex4_i_fifo2_data_in;
935	when others => --permet de gérer le cas où un spawn arrive par le réseau
936	switch_port_in_data <=Noc3.port_in_data;
937	switch_port_out_rd_en<=NOC3.port_out_rd_en;
938	switch_port_in_wr_en <=NOC3.port_in_wr_en;
939	switch_port_in_cmd_en <=NOC3.port_in_cmd_en;
940
941	i_fifo2_wr_en<=ex4_i_fifo2_wr_en;
942	i_fifo2_data_in<=ex4_i_fifo2_data_in;
943	end case;
944	Instr_in <=Instruction ;
945	if initreq2='1' and Ex_en(4)='1' then
946	Instr_in <=Ex2_Result ;
947	else
948	Instr_in <=Instruction ;
949	end if;
950	i_fifo2_wr_en<=ex2_i_fifo2_wr_en;
951	i_fifo2_data_in<=ex2_i_fifo2_data_in;
952	end process;
953
954
955	--===============================================================
956	MPI_CORE_DMA_ARBITER: DMA_ARBITER PORT MAP(
957	clk =>clk,
958	reset =>reset,
959
960	data_wr_mem => ram_data_in, --vers RAM
961
962	data_rd_mem => Ram_data_out, --- Vers RAM
963	address_rd =>dma_rd_address,
964	address_wr =>dma_wr_address,
965	address_out_rd =>ram_address_rd,
966	address_out_wr =>ram_address_wr,
967	ram_en => ram_env, --validation lecture
968	ram_we =>ram_wev, --validation écriture
969	hold_req=>hold_req,--demande de bus à l'application
970	hold_ack=>hold_ack, -- libération du bus RAM par l'application
971
972	data_rd_out => Dma_data_out, --vers périphérique
973	data_wr_in =>Dma_data_in, --vers périphérique
974	dma_wr_grant =>dma_wr_grant,
975	dma_rd_request => dma_rd_request,
976	dma_rd_grant => dma_rd_grant,
977	dma_wr_request => dma_wr_request
978	);
979
980
981	CORE_SCHEDULER: MPI_CORE_SCHEDULER PORT MAP( -- permet de sélectionner la source de l'instruction
982	-- qui sera exécutée par la MAE EX1
983	clk => clk,
984	reset => reset,
985	priority_rotation =>scheduler_priority_rotation,
986	instruction_fifo_empty =>i_fifo1_empty,
987	get_request_fifo_empty => i_fifo2_empty,
988	instruction_fifo_rd_en =>i_fifo1_rd_en,
989	get_request_fifo_rd_en =>i_fifo2_rd_en ,
990	instruction_fifo_data =>i_fifo1_data_out,
991	get_request_fifo_data =>i_fifo2_data_out,
992	fifo_selected =>fifo_sel,
993	instruction_available => fifo_instr,
994	fifo_empty => scheduler_fifo_empty,
995	fifo_rd_en =>scheduler_rd_en,
996	data_out => scheduler_data_out
997	);
998
999	end structural;
1000

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source: PROJECT_CORE_MPI/MPI_HCL/BRANCHES/v2.1/CORE_MPI/CORE_MPI.vhd @ 142

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