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EX1_FSM.vhd @ 142

Last change on this file since 142 was 142, checked in by rolagamo, 10 years ago

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1	----------------------------------------------------------------------------------
2	-- Company:
3	-- Engineer:GAMOM /KIEGAING
4	--
5	-- Create Date: 08:12:29 06/16/2011
6	-- Design Name:
7	-- Module Name: EX1_FSM - Behavioral
8	-- Project Name:
9	-- Target Devices:
10	-- Tool versions:
11	-- Description: Ce module est chargé de recevoir les instructions du programme MPI et
12	-- de les exécuter (PUT) il coopère avec EX2 qui reçoit les instructions venant du NoC
13	-- (GET)
14	--
15	-- Dependencies:
16	--
17	-- Revision: 09/07/2012
18	-- Revision 0.03 - File updated
19	-- Additional Comments:
20	--
21	----------------------------------------------------------------------------------
22	library IEEE;
23	use IEEE.STD_LOGIC_1164.ALL;
24	--use IEEE.STD_LOGIC_ARITH.ALL;
25	use IEEE.STD_LOGIC_UNSIGNED.ALL;
26	library NocLib ;
27	use Work.Packet_type.ALL;
28	USE ieee.numeric_std.ALL;
29
30
31	use NocLib.CoreTypes.all;
32	---- Uncomment the following library declaration if instantiating
33	---- any Xilinx primitives in this code.
34	--library UNISIM;
35	--use UNISIM.VComponents.all;
36
37	entity EX1_FSM is
38	-- parametres generiques du module :
39
40
41	Port (
42	--instruction_available : in STD_LOGIC;
43	clk : in STD_LOGIC;
44	reset : in STD_LOGIC;
45	instruction : in std_logic_vector(Word-1 downto 0);
46	instruction_en : in std_logic:='0'; -- active le module instruction
47	pid : in std_logic_vector(3 downto 0) ; -- id du processeur
48	nprocs : in std_logic_vector(3 downto 0);-- nombre de processeur du MPSOC - 1
49	Result : out STD_LOGIC_VECTOR (7 downto 0):=(others=>'0'); -- le résultat de l'exécution de ce module
50	Ready : out std_logic; --indique la fin de l'éxécution d'une instruction
51	AppInitReq :out STD_LOGIC:='0'; -- requête d'initialisation de l'application
52	AppInitAck :in STD_LOGIC; -- Acquitement d'initialisation
53	Initialized:in std_logic ; -- état de la Lib
54	-- Accès au Fifo d'instructions
55	priority_rotation : out STD_LOGIC:='0';
56	fifo_rd_en : out STD_LOGIC:='0';
57	fifo_empty : in STD_LOGIC;
58	fifo_data_out : in STD_LOGIC_VECTOR (7 downto 0);
59	fifo_src : in STD_LOGIC; --permet de désigner le fifo qui est en service
60
61
62	Snd_Data : IN Typ_PortIO(0 to 3);
63	Snd_Start : IN std_logic;
64	Snd_Ack : OUT std_logic;
65
66	-- Accès au réseau sur puce
67	switch_port_in_full : in std_logic;
68	switch_port_in_data : out STD_LOGIC_VECTOR (7 downto 0):=(others=>'0');
69	switch_port_in_wr_en : out STD_LOGIC:='0';
70	-- Accès à la mémoire RAM du PE
71	ram_data_in : in std_logic_vector(7 downto 0);
72	ram_data_out : out std_logic_vector(7 downto 0):=(others=>'0');
73	ram_rd,ram_wr : out std_logic:='0';
74	ram_address : out std_logic_vector(15 downto 0):=(others=>'0');
75
76	dma_wr_request : OUT std_logic:='0';
77	dma_rd_request : OUT std_logic:='0';
78	dma_wr_grant : in STD_LOGIC;
79	dma_rd_grant : in STD_LOGIC);
80	end EX1_FSM;
81
82	architecture Behavioral of EX1_FSM is
83
84	component proto_send is
85	generic (sizemem : natural := 64);
86	port (
87	clk,reset : in std_logic;
88	fifo_in_empty,fifo_in_full : in std_logic; --signaux pour le fifo d'entrée
89	fifo_out_empty,fifo_out_full : in std_logic; --signaux pour le fifo de sortie
90	fifo_out_wr_en : out std_logic:='0'; --écriture autorisée dans la fifo de sortie
91	fifo_in_rd_en : out std_logic:='0'; --lecture autorisée dans la fifo d'entrée
92	fifo_in_data_out : in std_logic_vector(Word-1 downto 0);
93	fifo_out_data_in : out std_logic_vector(Word-1 downto 0);
94	packet_len : in std_logic_vector(Word-1 downto 0); --la longueur du paquet
95	copy_mode : in std_logic; --Fifo_to_mem ou Fifo_to_fifo
96	snd_start : in std_logic; --début de la réception
97	snd_ack :in std_logic; -- acquittement de la réception
98	snd_comp : out std_logic; -- fin de la réception
99	mem :in memory(0 to sizemem-1)); --données à copier vers le fifo
100
101
102	end component proto_send;
103	-- definition du type etat pour le codage des etats des fsm
104	type fsm_states is (fifo_select, fetch_packet_type, decode_packet_type, fetch_addresses,
105	decode_packet_type2, read_status1,read_status2,ex1_barrier1, ex1_barrier2, ex1_barrier3, ex1_barrier4,
106	ex1_get1, ex1_get2,ex1_get3,ex1_get4, ex1_put1, ex1_put2, ex1_put3, ex1_put4,ex1_put5,
107	ex1_init1,ex1_init_run,ex1_init2,ex1_init3,ex1_spawn,ex1_ready,ex1_send_ack,ex1_Wsync);
108	-- machine a etat du module
109	signal ex1_state,Next_Ex1_state : fsm_states;
110
111	-- les variables utilisées dans la fsm
112	signal snd_start1,snd_start_sync,snd_comp,snd_ack1,push:std_logic:='0';
113	signal mem,mem_i : memory(0 to 3);
114	signal data_to_send,data_to_send_i,result_i,result1,noc_fifo_in : std_logic_vector(Word-1 downto 0);
115	signal packet_type,packet_type_i : std_logic_vector(3 downto 0);
116	--signal dpid : std_logic_vector(3 downto 0);
117	signal pid_counter,pid_counter_i : std_logic_vector(3 downto 0);
118	signal p_len,p_len_i: std_logic_vector(Word-1 downto 0);
119	signal src_address,src_address_i : std_logic_vector(ADRLEN-1 downto 0);
120	signal dma_rd,dma_wr,Wr_ok,rd_ok:std_logic:='0';
121	--signal res_address : std_logic_vector(15 downto 0);
122	signal dest_address,dest_address_i : std_logic_vector(ADRLEN-1 downto 0);
123	signal n,n_i : natural range 0 to 15;
124	signal len,len_i : natural range 0 to 255;
125	signal fifo_rd,fifo_wr,fifo_copy:std_logic:='0';
126	signal fifo_sel:std_logic:='0';
127	signal run_init,run_init_i:std_logic:='0';
128	begin
129	-- connection des signaux avec les ports
130	ram_address <= src_address;
131	result<=Result1;
132	sw_send: proto_send generic map (sizemem=>4)
133	port map (
134	clk=>clk,
135	reset=>reset,
136	fifo_in_empty=>fifo_empty,
137	fifo_in_full=>'0',--pas utilisé
138	fifo_out_empty=>'0',
139	packet_len=>p_len,
140	copy_mode=>fifo_copy,
141	fifo_out_full => switch_port_in_full,
142	fifo_in_rd_en=>fifo_rd,
143	fifo_in_data_out=>fifo_data_out,
144	fifo_out_wr_en =>fifo_wr,
145
146	fifo_out_data_in =>noc_fifo_in,
147	snd_start =>snd_start_sync,
148	snd_ack =>snd_ack1,
149	snd_comp=>snd_comp,
150	mem =>mem
151	);
152	ex1_fsm_sync:process(clk)
153
154	begin
155	if rising_edge(clk) then
156	if reset = '1' then
157	ex1_state <= fifo_select;
158	n<=0;
159	len<=0;
160	p_len<=(others=>'0');
161	snd_ack<='0';
162	src_address<=(others=>'0');
163	dest_address<=(others=>'0');
164	run_init<='0';
165	else
166	ex1_state<=next_ex1_state;
167	n<=n_i;
168	len<=len_i;
169	p_len<=p_len_i;
170	dest_address<=dest_address_i;
171	Packet_type<=Packet_type_i;
172	Pid_counter<=Pid_counter_i;
173	Data_to_send<=Data_to_send_i;
174	Result1<=Result_i;
175	run_init<=Run_init_i;
176	for i in 0 to 3 loop
177	mem(i)<=mem_i(i);
178	end loop;
179	src_address <= src_address_i;
180	snd_ack<=snd_ack1; --acquittement de l'envoie des données pour EX4
181	snd_start_sync<=snd_start1;
182	end if;
183	end if;
184	end process ex1_fsm_sync;
185	-- processus de transistion entre les etats
186	fsm_nst_logic : process(ex1_state,n,instruction_en,fifo_empty,fifo_data_out, switch_port_in_full,pid,
187	pid_counter,len,p_len,snd_start,snd_comp, ram_data_in,dma_rd_grant,dma_wr_grant,AppInitAck,src_address,
188	fifo_src,dest_address,packet_type,mem,snd_data,run_init,data_to_send)
189	variable tempval : std_logic_vector(Word-1 downto 0);
190	variable onepop,fifo_vide : std_logic:='0'; --indique que le fifo a été dépilé
191	begin
192	snd_ack1<='0';
193	fifo_copy<='0';
194	snd_start1<='0';
195	n_i<=n; --valeur par défaut
196	Next_ex1_state <=Ex1_state;
197	Src_address_i<=src_address;
198	dest_address_i<=dest_address;
199	P_len_i<=P_len;
200	Packet_type_i<=Packet_type;
201	Pid_counter_i<=Pid_counter;
202	run_init_i<=Run_init;
203	Len_i<=Len;
204	Wr_ok<='0';
205	Rd_ok<='0';
206	Data_to_send_i<=Data_to_send;
207	dma_rd<='0'; --attention ceci peut changer le code
208	dma_wr<='0'; --il faut donc le vérifier
209	for i in 0 to 3 loop
210	mem_i(i)<=mem(i);
211	end loop;
212	case ex1_state is
213	when fifo_select => if instruction_en='1' and fifo_empty ='0' then
214	Next_ex1_state <= fetch_packet_type;
215	else
216	Next_ex1_state <= fifo_select;
217	end if;
218	rd_ok<='0';
219	wr_ok<='0';
220	if instruction_en='1' and snd_start='1' then
221	run_init_i<='1';
222	Next_ex1_state<=ex1_init_run;
223	else
224	run_init_i<='0';
225	end if;
226	--lecture du registre status de la mib MPI
227	when read_status1 => if dma_rd_grant = '1' then -- fin du mpi_put
228	Next_ex1_state <= read_status2;
229	else
230	Next_ex1_state <= read_status1;
231	end if;
232	src_address_i<=std_logic_vector(to_unsigned(core_base_adr,16));
233	when read_status2 =>
234	Next_ex1_state <= fifo_select;
235	when fetch_packet_type => rd_ok<='0';
236	if fifo_empty ='1' then
237	Next_ex1_state <= fifo_select;
238	else
239	packet_type_i <= fifo_data_out(7 downto 4);
240	data_to_send_i <= fifo_data_out;
241	Next_ex1_state <= decode_packet_type;
242	rd_ok<='1';
243	end if;
244	when decode_packet_type => rd_ok<='0';
245	if fifo_empty='0' then
246	if packet_type = MPI_PUT then
247	p_len_i <= fifo_data_out + 4;
248	n_i <= 0;rd_ok<='1';
249	Next_ex1_state <= fetch_addresses;
250	elsif packet_type = MPI_GET then
251	len_i <= to_integer(unsigned(fifo_data_out));
252	p_len_i <= fifo_data_out;
253	n_i <= 0; rd_ok<='1';
254	Next_ex1_state <= fetch_addresses;
255	elsif packet_type = MPI_BARRIER_REACHED or packet_type = MPI_BARRIER_COMPLETED then
256	p_len_i <= "00000011"; -- = 3
257	pid_counter_i <= "0000";
258	rd_ok<='1';
259	Next_ex1_state <= ex1_barrier1;
260	elsif packet_type = MPI_INIT then
261	Next_ex1_state<=ex1_init1;
262	len_i <= to_integer(unsigned(fifo_data_out));
263	p_len_i<=fifo_data_out;
264	n_i<=0;rd_ok<='1';
265	elsif packet_type = MPI_ACK then
266	len_i <= to_integer(unsigned(fifo_data_out));
267	p_len_i<=fifo_data_out;
268	n_i <= 0; rd_ok<='0';
269	Next_ex1_state <= ex1_send_Ack;
270	elsif packet_type = MPI_WIN_SYNC then
271	len_i <= to_integer(unsigned(fifo_data_out));
272	p_len_i<=fifo_data_out;
273	n_i <= 0; rd_ok<='0';
274	Next_ex1_state <= ex1_WSynC;
275	elsif packet_type = MPI_SPAWN then
276	Next_ex1_state<=ex1_SPAWN;
277	len_i <= to_integer(unsigned(fifo_data_out));
278	p_len_i<=fifo_data_out;
279	onepop:='1';--il y a une donnée lue
280	src_address_i<=std_logic_vector(to_unsigned(Core_spawn_adr+1,16));
281	rd_ok<='0';
282	else -- packet non reconnu
283	--synthesis translate_off
284	report "Ex1 : ATTENTION paquet non reconnu !!!!!!!!!" ;
285	--synthesis translate_on
286	if fifo_empty = '1' then
287	Next_ex1_state <= fifo_select;
288
289	else
290	rd_ok<='1';
291	packet_type_i <= fifo_data_out(7 downto 4); --lire le prochain paquet
292	data_to_send_i <= fifo_data_out;
293	Next_ex1_state <= decode_packet_type;-- pas necessaire mais plus sure
294	end if;
295	end if;
296	end if;
297	when fetch_addresses => n_i<=n;rd_ok<='1';
298	if fifo_empty = '0' and n = 0 then
299	src_address_i(15 downto 8) <= fifo_data_out;
300	n_i <= n + 1;
301	Next_ex1_state <= fetch_addresses;
302	elsif fifo_empty = '0' and n = 1 then
303	src_address_i(7 downto 0) <= fifo_data_out;
304	n_i <= n + 1;
305	Next_ex1_state <= fetch_addresses;
306	elsif fifo_empty = '0' and n = 2 then
307	dest_address_i(15 downto 8) <= fifo_data_out;
308	n_i <= n + 1;
309	Next_ex1_state <= fetch_addresses;
310	elsif fifo_empty = '0' and n = 3 then
311	dest_address_i(7 downto 0) <= fifo_data_out;
312	n_i <= n+1;
313	elsif n=4 then
314	rd_ok<='0';
315	n_i<=0;
316	Next_ex1_state <= decode_packet_type2;
317	elsif fifo_empty='1' then
318	rd_ok<='0';
319	Next_ex1_state <= fetch_addresses; --attendre les données manquantes
320	else
321	Next_ex1_state <= fifo_select;
322	end if;
323	when decode_packet_type2 => if packet_type = MPI_PUT then
324	Next_ex1_state <= ex1_put1;
325	elsif packet_type = MPI_GET then
326	Next_ex1_state <= ex1_get1;
327	end if;
328	-- execution du mpi put
329	when ex1_put1 => if dma_rd_grant = '1' then
330	Next_ex1_state <= ex1_put2;
331	else
332	Next_ex1_state <= ex1_put1;
333	end if;
334	Wr_ok<='0';
335	when ex1_put2 =>Wr_ok<='0';
336	if switch_port_in_full = '0' and n = 0 then
337	--envoie du code MPI_PUT
338	n_i<= n + 1;
339	wr_ok<='0';
340	Next_ex1_state <= ex1_put2;
341	elsif switch_port_in_full = '0' and n = 1 then
342	data_to_send_i <= p_len;
343	n_i<= n + 1;
344	wr_ok<='1';
345	Next_ex1_state <= ex1_put2;
346	elsif switch_port_in_full = '0' and n = 2 then
347	data_to_send_i <= dest_address(15 downto 8);
348	n_i<= n + 1;
349	wr_ok<='1';
350	Next_ex1_state <= ex1_put2;
351	elsif switch_port_in_full = '0' and n = 3 then
352	data_to_send_i <= dest_address(7 downto 0);
353	n_i<= n +1;
354	wr_ok<='1';
355	Next_ex1_state <= ex1_put2;
356	elsif switch_port_in_full = '0' and n = 4 then
357	p_len_i <= p_len - 4;
358	-- Next_ex1_state <= ex1_put3;
359	Wr_ok<='0';
360	n_i<=n+1;
361	elsif n=5 and dma_rd_grant='1' then
362	Next_ex1_state <= ex1_put3;
363	n_i<=0;
364	Wr_ok<='1';
365	else
366	Next_ex1_state <= ex1_put2;
367	end if;
368	when ex1_put3 => wr_ok<='0';
369	if unsigned(p_len)>0 then
370	--if n=0 then
371	-- n_i<=1; --cycle d'attente pour la RAM
372	-- Wr_ok<='0';
373	-- elsif n=1 then
374	if switch_port_in_full = '0' then
375	if n=1 then --creer un délai sur ces signaux par rapport à src_adress
376	p_len_i <= p_len - 1;
377	Wr_Ok<='1';
378	end if;
379	n_i<=1;
380	src_address_i <= src_address+1;
381	Next_ex1_state <= ex1_put3;
382
383
384	else
385	Wr_Ok<='0';
386	src_address_i <= src_address;
387	n_i<=0;
388	end if;
389	--elsif n=2 then
390	-- n_i<=0; --cycle d'attente pour la RAM
391	-- Wr_ok<='0';
392	-- src_address_i <= src_address ; --prochaine lecture
393	--
394	-- end if;
395	else
396	Wr_Ok<='0';
397	Next_ex1_state <= ex1_put4;
398	end if;
399	when ex1_put4 =>rd_ok<='1';
400	wr_ok<='0';
401	if dma_rd_grant = '1' then -- fin du mpi_put
402	Next_ex1_state <= ex1_put5;
403	rd_ok<='0';
404	n_i<=0;
405	data_to_send_i<="00000001";
406	else
407	Next_ex1_state <= ex1_put4;
408	end if;
409
410	if fifo_src='0' then --détection Put ou Get
411	src_address_i<=std_logic_vector(to_unsigned(core_base_adr+5,16));
412	else
413	src_address_i<=std_logic_vector(to_unsigned(core_base_adr+4,16));
414	end if;
415	when ex1_put5 => if n >0 then
416
417	dma_wr<='1'; --demander un accès exclusif au bus
418	dma_rd<='1'; -- pour éviter une mauvaise mise à jour des données
419	else
420	dma_wr<='0';
421	dma_rd<='0';
422	end if;
423	rd_ok<='0';wr_ok<='0';
424	if n=0 then
425
426	n_i<=n+1;
427	elsif n=1 then
428	if dma_rd_grant='1' then
429	n_i<=n+1;
430
431	end if;
432	rd_ok<='1';
433	wr_ok<='0';
434	dma_wr<='1';
435	dma_rd<='1';
436	elsif n=2 then
437	if dma_rd_grant='1' then
438	n_i<=n+1;
439	dma_wr<='1';
440	tempval:=Ram_data_in;
441	data_to_send_i<=ram_data_in;
442	end if;
443	rd_ok<='1';
444	wr_ok<='0';
445
446	dma_rd<='1';
447	elsif n=3 then
448	dma_rd<='1';
449	if dma_rd_grant='1' and dma_wr_grant='1' then
450	n_i<=n+1;
451	tempval:=Ram_data_in;
452	data_to_send_i<=ram_data_in;
453	--src_address_i<=std_logic_vector(to_unsigned(core_base_adr+5,16));
454	tempval(5):='1'; -- SET du bit DSENT
455	data_to_send_i(5)<='1';
456	if fifo_src='0' then -- c'est un put qui est exécuté
457	tempval(5):='1'; -- SET du bit DSENT
458	--data_to_send_i<=ram_data_in or "00100000";
459	else -- c'est un Get qui est exécuté
460	--tempval(2):='1'; -- ne pas annuler le sending après un GET
461	--data_to_send_i<=ram_data_in or "00000100";
462	end if;
463	--data_to_send_i<=tempval; --A tester
464	rd_ok<='0';
465	wr_ok<='1';
466	dma_wr<='1';
467	dma_rd<='1';
468	else
469	rd_ok<='1';
470	wr_ok<='0';
471	dma_rd<='0'; --libérer le bus et revenir en arrière
472	dma_wr<='0';
473	n_i<=0;
474	end if;
475	elsif n=4 then
476	if dma_wr_grant = '1' and dma_rd_grant='1' then
477	n_i<=n+1;
478
479	--src_address_i<=std_logic_vector(to_unsigned(core_base_adr+5,16));
480	end if;
481	rd_ok<='0';
482	wr_ok<='1';
483	dma_wr<='1';
484	dma_rd<='1';
485	elsif n=5 then --accusé de réception
486	if dma_wr_grant = '1' and dma_rd_grant='1' then
487	n_i<=n+1;
488
489	src_address_i<=std_logic_vector(to_unsigned(core_put_adr+6,16));
490	data_to_send_i<="00000001";
491	end if;
492	rd_ok<='0';
493	wr_ok<='1';
494	dma_wr<='1';
495	dma_rd<='1';
496	elsif n=6 then
497	if dma_wr_grant = '1' then
498	n_i<=n+1;
499
500	-- SET du bit DSENT
501	data_to_send_i<="00000001";
502	end if;
503	rd_ok<='0';
504	wr_ok<='1';
505	dma_wr<='1';
506	dma_rd<='0';
507	elsif n=7 then
508	n_i<=0;
509	Next_ex1_state <= fifo_select;
510	rd_ok<='0';
511	wr_ok<='0';
512	dma_wr<='0';
513	dma_rd<='0';
514	end if;
515
516
517	when ex1_get1 => wr_ok<='0';
518	if switch_port_in_full = '0' and n = 0 then -- execution du mpi get
519	--écrire l'entête de la fonction
520	n_i<= n + 1;
521	Wr_ok<='0';
522	Next_ex1_state <= ex1_get1;
523	elsif switch_port_in_full = '0' and n = 1 then -- execution du mpi get
524	data_to_send_i <= "00001000"; -- longueur du paquet sur le réseau ?
525	n_i<= n + 1;
526	Wr_ok<='1';
527	Next_ex1_state <= ex1_get1;
528	elsif switch_port_in_full = '0' and n = 2 then
529	data_to_send_i <= "0000"&pid; -- Rang source
530	n_i<= n + 1;
531	Wr_ok<='1';
532	Next_ex1_state <= ex1_get1;
533	elsif switch_port_in_full = '0' and n = 3 then
534	data_to_send_i <= p_len;
535	n_i<= n + 1;
536	Wr_ok<='1';
537	Next_ex1_state <= ex1_get1;
538	elsif switch_port_in_full = '0' and n = 4 then
539	data_to_send_i <= src_address(15 downto 8);
540	n_i<= n + 1;
541	Wr_ok<='1';
542	Next_ex1_state <= ex1_get1;
543	elsif switch_port_in_full = '0' and n = 5 then
544	data_to_send_i <= src_address(7 downto 0);
545	n_i<= n + 1;
546	Wr_ok<='1';
547	Next_ex1_state <= ex1_get1;
548	elsif switch_port_in_full = '0' and n = 6 then
549	data_to_send_i <= dest_address(15 downto 8);
550	n_i<= n + 1;
551	Wr_ok<='1';
552	Next_ex1_state <= ex1_get1;
553	elsif switch_port_in_full = '0' and n = 7 then
554	data_to_send_i <= dest_address(7 downto 0);
555	n_i<= n + 1;
556	Wr_ok<='1';
557	Next_ex1_state <= ex1_get1;
558	elsif switch_port_in_full = '0' and n = 8 then
559	Next_ex1_state <= ex1_get2;
560	n_i<=0;
561	Wr_ok<='1';
562	else
563	Next_ex1_state <= ex1_get1;
564	end if;
565	when ex1_get2 => if dma_wr_grant = '1' then
566	Next_ex1_state <= ex1_get3;
567	src_address_i<=std_logic_vector(to_unsigned(core_get_adr+6,16));
568	data_to_send_i<="00000001";
569	else
570	Next_ex1_state <= ex1_get2;
571	end if;
572	dma_wr<='1';
573	when ex1_send_ack \|ex1_Wsync=> rd_ok<='0';
574	if n = 0 then -- execution du mpi ack /ou Mpi_Win_sync
575	if switch_port_in_full = '0' then
576
577	wr_Ok<='0'; --envoie de la première donnée(code ack)
578	n_i<= n + 1;
579	onepop:='0';
580
581	end if;
582	elsif n = 1 then
583	if fifo_empty='0' and onepop='0' then
584	data_to_send_i <=p_len ;
585
586	rd_Ok<='1'; --passe la longueur
587	onepop:=not onepop; --une donnée lue il faut arrêter de dépiler
588
589	else
590	rd_Ok<='0';
591	end if;
592
593	if (switch_port_in_full = '0') and onepop='1' then wr_ok<='1';
594	onepop:=not onepop;
595	n_i<= n + 1;
596	wr_ok<='1';
597	elsif (switch_port_in_full = '1') then
598	wr_Ok<='0';
599
600	end if;
601
602	elsif (n= 2) then
603	if fifo_empty='0' and onepop='0' then
604
605	data_to_send_i <=fifo_data_out;
606	rd_Ok<='1';
607	onepop:=not onepop; --une donnée lue il faut arrêter de dépiler
608
609	else
610	rd_Ok<='0';
611	end if;
612
613	if (switch_port_in_full = '0') and onepop='1' then wr_ok<='1';
614	onepop:=not onepop;
615	n_i<= n + 1;
616	wr_ok<='1';
617	else
618	wr_Ok<='0';
619
620	end if;
621	elsif (n= 3) then
622	if fifo_empty='0' and onepop='0' then
623
624	data_to_send_i <=fifo_data_out;
625	rd_Ok<='1';
626	onepop:=not onepop; --une donnée lue il faut arrêter de dépiler
627
628	else
629	rd_Ok<='0';
630	end if;
631
632	if (switch_port_in_full = '0') and onepop='1' then wr_ok<='1';
633	onepop:=not onepop;
634	n_i<= n + 1;
635	wr_ok<='1';
636
637	else
638	wr_Ok<='0';
639
640	end if;
641	elsif n = 4 then
642	n_i<=0;
643	Wr_Ok<='1';
644	rd_ok<='0';--vider le tampon
645	Next_ex1_state <= fifo_select;
646
647	end if;
648
649	when ex1_get3 =>if n<2 then --ecriture de la fin d'envoie
650	if dma_wr_grant = '1' then -- fin du post de mpi_get
651
652	n_i<=n+1;
653	data_to_send_i<="00000001";
654	wr_ok<='1';
655	rd_ok<='0';
656	end if;
657
658	elsif n=2 then
659	n_i<=0;
660	Next_ex1_state <= ex1_get4;
661	end if;
662	src_address_i<=std_logic_vector(to_unsigned(core_get_adr+6,16));
663	when ex1_get4 => wr_ok<='0';
664	rd_ok<='0';
665	dma_wr<='1';
666	dma_rd<='1';
667	src_address_i<=std_logic_vector(to_unsigned(core_base_adr+5,16));
668
669	if n=0 then
670
671	if dma_rd_grant='1' then
672	n_i<=n+1;
673
674	end if;
675	rd_ok<='1';
676	wr_ok<='0';
677
678	elsif n=1 then
679	src_address_i<=std_logic_vector(to_unsigned(core_base_adr+5,16));
680	if dma_rd_grant='1' then
681	n_i<=n+1;
682
683	end if;
684	rd_ok<='1';
685	wr_ok<='0';
686
687	elsif n=2 then
688	if dma_rd_grant='1' then
689	n_i<=n+1;
690	rd_ok<='1';
691	src_address_i<=std_logic_vector(to_unsigned(core_base_adr+5,16));
692	else
693	n_i<=1;
694	end if;
695
696	elsif n=3 then
697	if dma_rd_grant='1' and dma_wr_grant='1' then
698	n_i<=n+1;
699	tempval:=Ram_data_in;
700	data_to_send_i<=Ram_data_in;
701	rd_ok<='1';
702	wr_ok<='0';
703	dma_wr<='1';
704	dma_rd<='1';
705	else
706	dma_wr<='0';
707	dma_rd<='0';
708	n_i<=n-1;
709	end if;
710	src_address_i<=std_logic_vector(to_unsigned(core_base_adr+5,16));
711	elsif n=4 then
712	if dma_wr_grant = '1' and dma_rd_grant='1' then
713	n_i<=n+1;
714	rd_ok<='0';
715	wr_ok<='1';
716	tempval(6):='1'; --SET du bit Windows Busy --car réception Get
717	tempval(1):='1'; -- SET du bit DReceiving
718	data_to_send_i(6)<='1';
719	data_to_send_i(1)<='1';
720	--data_to_send_i<=tempval; -- à tester absolument !!!
721	else
722	rd_ok<='0';
723	wr_ok<='1';
724	n_i<=1;
725	end if;
726	dma_wr<='1';
727	dma_rd<='1';
728	elsif n=5 then
729	wr_ok<='1';
730	if dma_wr_grant = '1' then
731	n_i<=n+1;
732	end if;
733	elsif n=6 then
734	n_i<=0;
735	Next_ex1_state <= fifo_select;
736	dma_wr<='0';
737	dma_rd<='0';
738	end if;
739
740	when ex1_spawn => rd_ok<='0';
741	if n = 0 then -- execution du mpi spawn
742	if switch_port_in_full = '0' then
743
744	wr_Ok<='0';
745	n_i<= n + 1;
746	onepop:='0';
747	--data_to_send_i<=len;
748	end if;
749	elsif n = 1 then
750	if fifo_empty='0' and onepop='0' then
751	data_to_send_i <=p_len ;
752
753	rd_Ok<='1';
754	onepop:='1'; --une donnée lue il faut arrêter de dépiler
755
756	end if;
757
758	if (switch_port_in_full = '0') and onepop='1' then wr_ok<='1';
759	onepop:='0';
760	n_i<= n + 1;
761	wr_ok<='1';
762	else
763	wr_Ok<='0';
764
765	end if;
766
767	elsif (n= 2) or (n=3) then
768	if fifo_empty='0' and onepop='0' then
769
770	data_to_send_i <=fifo_data_out;
771	rd_Ok<='1';
772	onepop:='1'; --une donnée lue il faut arrêter de dépiler
773
774	end if;
775
776	if (switch_port_in_full = '0') and onepop='1' then wr_ok<='1';
777	onepop:='0';
778	n_i<= n + 1;
779	wr_ok<='1';
780	else
781	wr_Ok<='0';
782
783	end if;
784	elsif n=4 then
785	n_i<=0;
786	Wr_Ok<='1';
787	rd_ok<='0';
788	Next_ex1_state <= fifo_select;
789	end if;
790	-- execution du barrier
791	when ex1_barrier1 => if switch_port_in_full = '0' then
792	Next_ex1_state <= ex1_barrier2;
793	else
794	Next_ex1_state <= ex1_barrier1;
795	end if;
796	when ex1_barrier2 => if switch_port_in_full = '0' then
797	Next_ex1_state <= ex1_barrier3;
798	else
799	Next_ex1_state <= ex1_barrier2;
800	end if;
801	when ex1_barrier3 => if switch_port_in_full = '0' then
802	Next_ex1_state <= ex1_barrier4;
803	else
804	Next_ex1_state <= ex1_barrier3;
805	end if;
806	when ex1_barrier4 => if packet_type = MPI_BARRIER_COMPLETED and pid_counter < nprocs then
807	pid_counter_i <= pid_counter + 1;
808	Next_ex1_state <= ex1_barrier1;
809	else
810	Next_ex1_state <= fifo_select;
811	end if;
812	when ex1_init1 => rd_ok<='0';
813	if n=0 then
814	n_i<=n+1;
815	Len_i<=len-2; --deux données a été dépilée
816	elsif n=1 then --vider le fifo instruction
817	if len>0 then
818	if fifo_empty='0' then
819	rd_ok<='1';
820	Len_i<=len-1;
821
822	else
823	rd_ok<='0';
824	Len_i<=Len;
825	end if;
826	else
827	n_i<=n+1;
828	end if;
829	elsif n=2 then --
830	n_i<=0;
831	rd_ok<='0';
832	Next_ex1_state<=ex1_init_run;
833
834	end if;
835
836	when ex1_init_run=> if n=0 then
837	if snd_start='1' then --le module ex4 veut envoyer des données
838
839	n_i<=n+1;
840
841	for i in 0 to 3 loop
842	mem_i(i)<=snd_data(i);
843	end loop;
844	if snd_data(0)(7 downto 4)=MPI_INIT or
845	snd_data(0)(7 downto 4)=MPI_SPAWN or
846	snd_data(0)(7 downto 4)=MPI_ACK then
847
848	else
849	report "Ex1 : Une instruction inconnue a été envoyé par Ex4 sur le réseau !";
850	end if;
851	P_len_i<=x"04";
852	fifo_copy<='0';
853	snd_ack1<='0';
854
855	end if;
856	if AppInitAck='1' then
857	Next_ex1_state<=ex1_init2;
858	end if;
859	elsif n=1 then
860	fifo_sel<='0';--pas de rotation du fifo instruction
861	snd_start1<='1';
862	P_len_i<=x"04";
863	fifo_copy<='0';
864	snd_ack1<='0';
865
866	n_i<=n+1;
867	elsif n=2 then
868	snd_start1<='1';
869	if snd_comp='1' then
870	snd_ack1<='1';
871
872	snd_start1<='0';
873	n_i<=n+1;
874	end if;
875	elsif n=3 then
876	snd_start1<='0';
877	snd_ack1<='1';
878	fifo_sel<='0';
879	if snd_start='0' then --attente l'annulation de l'envoie
880	n_i<=0;
881	snd_ack1<='0';
882	if run_init='1' then
883	Next_EX1_state<=fifo_select;
884	--run_init<='0';
885	end if;
886	end if;
887	end if;
888
889
890	when ex1_init2 => -- écriture dans le registre status reg.
891	src_address_i<=std_logic_vector(to_unsigned(core_base_adr,16));
892	if n=0 then --envoie du message Spawn Ack sur le réseau
893	if instruction(6)='1' then --Spawned=1 ?
894	n_i<=1; --envoie du message Spawn à main lib
895	data_to_send_i<="01010000"; --init+spawn
896	else
897	n_i<=4; --écrire le résultat de la fn
898	data_to_send_i<="00010000"; --init seul
899	end if;
900
901	elsif n=1 then
902	n_i<=n+1;
903	mem_i(0)<=MPI_INIT & x"0"; --répondre au premier
904	mem_i(1)<=x"04";
905	mem_i(2)<=x"00";
906	mem_i(3)<=INIT_SPAWN & pid;-- indiquer qui répond au
907	elsif n=2 then
908	snd_start1<='1';
909	n_i<=n+1;
910	fifo_copy<='0';
911	elsif n=3 then
912	fifo_copy<='0';
913	snd_start1<='1';
914	if snd_comp='1' then
915	snd_ack1<='1';
916	snd_start1<='0';
917	n_i<=n+1;
918	end if;
919	elsif n=4 then --écriture du registre status
920	dma_wr<='1';
921	wr_ok<='1';
922	if dma_wr_grant = '1' then -- fin du mpi_init
923	n_i<=n+1;
924	end if;
925	elsif n=5 then
926	wr_ok<='1';
927	dma_wr<='1';
928	if dma_wr_grant = '1' then -- fin du mpi_init
929	n_i<=n+1;
930	end if;
931	elsif n=6 then
932	Next_ex1_state <= ex1_init3;
933	n_i<=0;
934	wr_ok<='0';
935	end if;
936
937
938	when ex1_init3 =>--if AppInitAck='1' then
939	Next_ex1_state <= fifo_select;
940	--end if;
941	when ex1_ready => Next_ex1_state <= fifo_select;
942	when others => Next_ex1_state <= fifo_select;
943	end case;
944
945	end process;
946
947	-- sortie de la machine à etat
948	ex1_fsm_action : process(ex1_state, fifo_empty, switch_port_in_full, p_len,pid,
949	pid_counter, dma_rd,dma_wr,ram_data_in,AppInitAck,fifo_wr,noc_fifo_in,data_to_send, packet_type, wr_ok,rd_ok,
950	fifo_rd)
951	variable status_reg : std_logic_vector(word-1 downto 0):=(others=>'0');
952	begin
953	-- code fonctionnel
954	Result_i<=Result1;
955	case ex1_state is
956	when fifo_select => priority_rotation <='1'; -- on peut changer la priorité
957	fifo_rd_en <= '0';
958	switch_port_in_data <= (others =>'0');
959	switch_port_in_wr_en <= '0';
960	dma_rd_request <= '0';
961	dma_wr_request <= '0';
962	Ram_rd<='0';
963	Ram_wr<='0';
964	Ram_data_out<=(others=>'0');
965	AppInitReq<='0';
966	Result_i <=(others=>'0');
967	Ready<='1';
968	when read_status1 => priority_rotation <='0';
969	fifo_rd_en <= '0';
970	switch_port_in_data <= (others =>'0');
971	switch_port_in_wr_en <= '0';
972	dma_rd_request <= '1';
973	dma_wr_request <= '0';
974	Ram_rd<='0';
975	Ram_wr<='0';
976	Ram_data_out<=(others=>'0');
977	AppInitReq<='0';
978	Result_i <=(others=>'0');
979	Ready<='0';
980	when read_status2 => priority_rotation <='0';
981	fifo_rd_en <= '0';
982	switch_port_in_data <= (others =>'0');
983	switch_port_in_wr_en <= '0';
984	dma_rd_request <= '1';
985	dma_wr_request <= '0';
986	Ram_rd<='1';
987	Ram_wr<='0';
988	Ram_data_out<=(others=>'0');
989	AppInitReq<='0';
990	status_reg:=Ram_data_in;
991	Result_i <=(others=>'0');
992	Ready<='0';
993	when fetch_packet_type => priority_rotation <='0';
994	fifo_rd_en <= rd_ok;
995	switch_port_in_data <= (others =>'0');
996	AppInitReq<='0';
997	switch_port_in_wr_en <= '0';
998	Ram_rd<='0';
999	Ram_wr<='0';
1000	dma_rd_request <= '0';
1001	dma_wr_request <= '0';
1002	Ram_data_out<=(others=>'0');
1003	Result_i <=(others=>'0');
1004	Ready<='0';
1005
1006	when decode_packet_type => priority_rotation <='0';
1007	fifo_rd_en <= rd_ok;
1008	switch_port_in_data <= Data_To_Send;
1009	switch_port_in_wr_en <= '0';
1010	AppInitReq<='0';
1011	Ram_rd<='0';
1012	Ram_wr<='0';
1013	dma_rd_request <= '0';
1014	dma_wr_request <= '0';
1015	Ram_data_out<=(others=>'0');
1016	Result_i <=(others=>'0');
1017	Ready<='0';
1018	when fetch_addresses => priority_rotation <='0';
1019	fifo_rd_en <= rd_ok;
1020	switch_port_in_data <= (others =>'0');
1021	switch_port_in_wr_en <= '0';
1022	AppInitReq<='0';
1023	Ram_rd<='0';
1024	Ram_wr<='0';
1025	dma_rd_request <= '0';
1026	dma_wr_request <= '0';
1027	Ram_data_out<=(others=>'0');
1028	Result_i <=(others=>'0');
1029	Ready<='0';
1030	when decode_packet_type2 =>priority_rotation <='0';
1031	fifo_rd_en <= '0';
1032	switch_port_in_data <= data_to_send;
1033	switch_port_in_wr_en <= '0';
1034	AppInitReq<='0';
1035	Ram_rd<='0';
1036	Ram_wr<='0';
1037	dma_rd_request <= '0';
1038	dma_wr_request <= '0';
1039	Ram_data_out<=(others=>'0');
1040	Result_i <=(others=>'0');
1041	Ready<='0'; -- fin du module
1042
1043	when ex1_barrier1 => priority_rotation <='0';
1044	fifo_rd_en <= '0';
1045	switch_port_in_data <= packet_type & pid_counter;
1046	switch_port_in_wr_en <= not(switch_port_in_full);
1047	AppInitReq<='0';
1048	Ram_rd<='0';
1049	Ram_wr<='0';
1050	dma_rd_request <= '0';
1051	dma_wr_request <= '0';
1052	Ram_data_out<=(others=>'0');
1053	Result_i <=(others=>'0');
1054	Ready<='0'; -- fin du module
1055
1056	when ex1_barrier2 => priority_rotation <='0';
1057	fifo_rd_en <= '0';
1058	switch_port_in_data <= p_len;
1059	switch_port_in_wr_en <= not(switch_port_in_full);
1060	AppInitReq<='0';
1061	Ram_rd<='0';
1062	Ram_wr<='0';
1063	dma_rd_request <= '0';
1064	dma_wr_request <= '0';
1065	Ram_data_out<=(others=>'0');
1066	Result_i <=(others=>'0');
1067	Ready<='0'; -- fin du module
1068
1069	when ex1_barrier3 => priority_rotation <='0';
1070	fifo_rd_en <= '0';
1071	switch_port_in_data <= "0000" & pid;
1072	switch_port_in_wr_en <= not(switch_port_in_full);
1073	AppInitReq<='0';
1074	Ram_rd<='0';
1075	Ram_wr<='0';
1076	dma_rd_request <= '0';
1077	dma_wr_request <= '0';
1078	Ram_data_out<=(others=>'0');
1079	Result_i <=(others=>'0');
1080	Ready<='0'; -- fin du module
1081
1082	when ex1_barrier4 => priority_rotation <='0';
1083	fifo_rd_en <= '0';
1084	switch_port_in_data <= "0000" & pid;
1085	switch_port_in_wr_en <= '0';
1086	AppInitReq<='0';
1087	dma_rd_request <= '0';
1088	Ram_rd<='0';
1089	Ram_wr<='0';
1090	dma_wr_request <= '0';
1091	Ram_data_out<=(others=>'0');
1092	Result_i <=(others=>'0');
1093	Ready<='0'; -- fin du module
1094
1095	when ex1_get1 => priority_rotation <='0';
1096	fifo_rd_en <= '0';
1097	switch_port_in_data <= data_to_send;
1098	switch_port_in_wr_en <= Wr_ok;
1099	AppInitReq<='0';
1100	Ram_rd<='0';
1101	Ram_wr<='0';
1102	dma_rd_request <= '0';
1103	dma_wr_request <= '0';
1104	Ram_data_out<=(others=>'0');
1105	Result_i <=(others=>'0');
1106	Ready<='0'; -- fin du module
1107	when ex1_get2 => priority_rotation <='0';
1108	fifo_rd_en <= '0';
1109	switch_port_in_data <= data_to_send;
1110	switch_port_in_wr_en <='0';
1111	AppInitReq<='0';
1112	Ram_rd<='0';
1113	Ram_wr<='0';
1114	dma_rd_request <= '0';
1115	dma_wr_request <= dma_Wr;
1116	Ram_rd<='0';
1117	Ram_wr<='0';
1118	Ram_data_out<=(others=>'0');
1119	Result_i <=(others=>'0');
1120	Ready<='0'; -- fin du module
1121
1122	when ex1_get3 => priority_rotation <='0';
1123	fifo_rd_en <= '0';
1124	switch_port_in_data <= (others=>'0');---???
1125	switch_port_in_wr_en <= '0';
1126	AppInitReq<='0';
1127	dma_rd_request <= '0';
1128	dma_wr_request <= '1';
1129	Ram_rd<='0';
1130	Ram_wr<=wr_ok;
1131	Ram_data_out<=data_to_send; -- le résultat de l'exécution
1132	Ready<='0'; -- fin du module
1133	Result_i <=(2=>'1',others=>'0');--Get completed
1134	when ex1_get4 => priority_rotation <='0';
1135	fifo_rd_en <= '0';
1136	switch_port_in_data <= ram_Data_in;
1137	switch_port_in_wr_en <= '0';
1138	AppInitReq<='0';
1139	dma_rd_request <= dma_rd;
1140	dma_wr_request <= dma_wr;
1141	Ram_rd<=rd_ok;
1142	Ram_wr<=wr_ok;
1143	Ram_data_out<=data_to_send; --"00000001";
1144	Result_i <=(2=>'1',others=>'0'); --get completed
1145	Ready<='0'; -- fin du module
1146	when ex1_put1 => priority_rotation <='0';
1147	fifo_rd_en <= '0';
1148	switch_port_in_data <= data_to_send;
1149	switch_port_in_wr_en <= '0';
1150	AppInitReq<='0';
1151	dma_rd_request <= '1';
1152	dma_wr_request <= '0';
1153	Ram_rd<='0';
1154	Ram_wr<='0';
1155	Ram_data_out<=(others=>'0');
1156	Result_i <=(others=>'0');
1157	Ready<='0'; -- fin du module
1158
1159	when ex1_put2 => priority_rotation <='0';
1160	fifo_rd_en <= '0';
1161	switch_port_in_data <= data_to_send;
1162	switch_port_in_wr_en <= wr_ok;
1163	AppInitReq<='0';
1164	Ram_rd<='1';
1165	Ram_wr<='0';
1166	dma_rd_request <= '1';
1167	dma_wr_request <= '0';
1168	Ram_data_out<=(others=>'0');
1169	Result_i <=(others=>'0');
1170	Ready<='0'; -- fin du module
1171
1172	when ex1_put3 => priority_rotation <='0';
1173	fifo_rd_en <= '0';
1174	switch_port_in_data <= ram_data_in;
1175	switch_port_in_wr_en <= wr_ok;
1176	AppInitReq<='0';
1177	dma_rd_request <= '1';
1178	dma_wr_request <= '0';
1179	Ram_rd<='1';
1180	Ram_wr<='0';
1181	Ram_data_out<=(others=>'0');
1182	Result_i <=(others=>'0');
1183	Ready<='0'; -- fin du module
1184
1185	when ex1_put4 => priority_rotation <='0';
1186	fifo_rd_en <= '0';
1187	switch_port_in_data <= ram_data_in;---???
1188	switch_port_in_wr_en <= '0';
1189	AppInitReq<='0';
1190	dma_rd_request <= rd_ok;
1191	dma_wr_request <= wr_ok;
1192	Ram_rd<=rd_ok;
1193	Ram_wr<=wr_ok;
1194	Ram_data_out<=data_to_send; --"00000001"; -- le résultat de l'exécution
1195	--result(1)<='1';
1196	Result_i <=(1=>'1',others=>'0');--put completed
1197	Ready<='0'; -- fin du module
1198	when ex1_put5 => priority_rotation <='0';
1199	fifo_rd_en <= '0';
1200	switch_port_in_data <= ram_Data_in;
1201	switch_port_in_wr_en <= '0';
1202	AppInitReq<='0';
1203	dma_rd_request <= dma_rd;
1204	dma_wr_request <= dma_wr;
1205	Ram_rd<=rd_ok;
1206	Ram_wr<=wr_ok;
1207	Ram_data_out<=data_to_send; --"00000001";
1208	Result_i <=(1=>'1',others=>'0'); --put completed
1209	Ready<='0'; -- fin du module
1210	when ex1_init1 => priority_rotation <='0';
1211	if fifo_empty='0' then
1212	fifo_rd_en <= rd_ok;
1213	else
1214	fifo_rd_en<='0';
1215	end if;
1216	switch_port_in_data <= data_to_send;
1217	switch_port_in_wr_en <= wr_ok;
1218	dma_rd_request <= '0';
1219	dma_wr_request <= '0';
1220	Ram_rd<='0';
1221	Ram_wr<='0';
1222	Ram_data_out<=(others=>'0');
1223	AppInitReq<='1';
1224	Result_i <=(others=>'0');
1225	Ready<='0';
1226	when ex1_init_run => priority_rotation <='0';
1227
1228	fifo_rd_en <= fifo_rd;
1229
1230	switch_port_in_data <= noc_fifo_in;
1231	switch_port_in_wr_en <= fifo_wr;
1232	dma_rd_request <= '0';
1233	dma_wr_request <= '0';
1234	Ram_rd<='0';
1235	Ram_wr<='0';
1236	Ram_data_out<=(others=>'0');
1237	AppInitReq<='1';
1238	Result_i <=(others=>'0');
1239	Ready<='0';
1240
1241	when ex1_init2=> priority_rotation <='0';
1242	fifo_rd_en <= '0';
1243	switch_port_in_data <= noc_fifo_in;
1244	switch_port_in_wr_en <= fifo_wr;
1245	AppInitReq<='0';
1246	dma_rd_request <= '0';
1247	dma_wr_request <= '1';
1248	Ram_rd<='0';
1249	Ram_wr<=wr_ok;
1250	Ram_data_out<=Data_to_send; -- le résultat de l'exécution
1251	Ready<='0'; -- dans le registre status
1252	Result_i <=(others=>'0');--
1253	when ex1_init3=> priority_rotation <='0';
1254	fifo_rd_en <= '0';
1255	switch_port_in_data <= ram_Data_in;
1256	switch_port_in_wr_en <= '0';
1257	AppInitReq<='0';
1258	dma_rd_request <= '0';
1259	dma_wr_request <= '1';
1260	Ram_rd<='0';
1261	Ram_wr<='1';
1262	Ram_data_out<="00010000";
1263	Ready<='0'; -- fin du module
1264	Result_i<=(0=>'1',others=>'0'); --le résultat de l'initialisation est écrit
1265
1266	when ex1_spawn => priority_rotation <='0';
1267	fifo_rd_en <= rd_ok;
1268	switch_port_in_data <= Data_to_send;
1269	switch_port_in_wr_en <= wr_ok;
1270	AppInitReq<='0';
1271	dma_rd_request <= '0';
1272	dma_wr_request <= '0';
1273	Ram_rd<='0';
1274	Ram_wr<='0';
1275	Ram_data_out<=(others=>'0');
1276	Result_i <=(others=>'0');
1277	Ready<='0';
1278	when ex1_send_ack\|ex1_Wsync => priority_rotation <='0';
1279	fifo_rd_en <= rd_ok;
1280	switch_port_in_data <= Data_to_send;
1281	switch_port_in_wr_en <= wr_ok;
1282	AppInitReq<='0';
1283	dma_rd_request <= '0';
1284	dma_wr_request <= '0';
1285	Ram_rd<='0';
1286	Ram_wr<='0';
1287	Ram_data_out<=(others=>'0');
1288	Result_i <=(others=>'0');
1289	Ready<='0';
1290	when ex1_ready =>
1291	Ready<='1'; -- fin du module
1292	priority_rotation <='0';
1293	fifo_rd_en <= '0';
1294	switch_port_in_data <= (others =>'0');
1295	switch_port_in_wr_en <= '0';
1296	dma_rd_request <= '0';
1297	dma_wr_request <= '0';
1298	Ram_rd<='0';
1299	Ram_wr<='0';
1300	Ram_data_out<=(others=>'0');
1301	AppInitReq<='0';
1302	Ready<='0';
1303
1304	when others => priority_rotation <='0';
1305	fifo_rd_en <= '0';
1306	switch_port_in_data <= (others =>'0');
1307	switch_port_in_wr_en <= '0';
1308	dma_rd_request <= '0';
1309	dma_wr_request <= '0';
1310	Ram_rd<='0';
1311	Ram_wr<='0';
1312	Ram_data_out<=(others=>'0');
1313	AppInitReq<='0';
1314	Result_i <=(others=>'0');
1315	Ready<='0';
1316	end case;
1317
1318	end process;
1319
1320	end Behavioral;
1321

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source: PROJECT_CORE_MPI/MPI_HCL/BRANCHES/v2.1/CORE_MPI/EX1_FSM.vhd @ 142

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