[142] | 1 | ---------------------------------------------------------------------------------- |
---|
| 2 | -- Company: |
---|
| 3 | -- Engineer: GAMOM Roland Christian |
---|
| 4 | -- |
---|
| 5 | -- Create Date: 19:16:34 05/23/2014 |
---|
| 6 | -- Design Name: |
---|
| 7 | -- Module Name: Fifo2Mem - Behavioral |
---|
| 8 | -- Project Name: |
---|
| 9 | -- Target Devices: |
---|
| 10 | -- Tool versions: |
---|
| 11 | -- Description: ce module permet de lire une fifo et d'écrire le résultat dans la mémoire Ram |
---|
| 12 | -- |
---|
| 13 | -- Dependencies: |
---|
| 14 | -- |
---|
| 15 | -- Revision: |
---|
| 16 | -- Revision 0.01 - File Created |
---|
| 17 | -- Additional Comments: |
---|
| 18 | -- |
---|
| 19 | ---------------------------------------------------------------------------------- |
---|
| 20 | library IEEE; |
---|
| 21 | use IEEE.STD_LOGIC_1164.ALL; |
---|
| 22 | Library NocLib; |
---|
| 23 | use NoCLib.CoreTypes.all; |
---|
| 24 | -- Uncomment the following library declaration if using |
---|
| 25 | -- arithmetic functions with Signed or Unsigned values |
---|
| 26 | use IEEE.NUMERIC_STD.ALL; |
---|
| 27 | use IEEE.STD_LOGIC_UNSIGNED.ALL; |
---|
| 28 | -- Uncomment the following library declaration if instantiating |
---|
| 29 | -- any Xilinx primitives in this code. |
---|
| 30 | --library UNISIM; |
---|
| 31 | --use UNISIM.VComponents.all; |
---|
| 32 | |
---|
| 33 | entity Fifo2Mem is |
---|
| 34 | Port ( clk : in STD_LOGIC; |
---|
| 35 | reset : in STD_LOGIC; |
---|
| 36 | wr_start : in STD_LOGIC; |
---|
| 37 | fifo_data_out : in STD_LOGIC_VECTOR (Word-1 downto 0); |
---|
| 38 | fifo_data_available : in STD_LOGIC; |
---|
| 39 | datalen : in STD_LOGIC_VECTOR (Word-1 downto 0); |
---|
| 40 | fifo_data_out_en : out STD_LOGIC; |
---|
| 41 | fifo_empty : in STD_LOGIC; |
---|
| 42 | ram_busy : in STD_LOGIC; |
---|
| 43 | ram_addr_start : in STD_LOGIC_VECTOR (ADRLEN-1 downto 0); |
---|
| 44 | ram_addr : out STD_LOGIC_VECTOR (ADRLEN-1 downto 0); |
---|
| 45 | ram_data_in : out STD_LOGIC_VECTOR (Word-1 downto 0); |
---|
| 46 | ram_wr : out STD_LOGIC; |
---|
| 47 | ram_en : out STD_LOGIC; |
---|
| 48 | wr_comp :out STD_LOGIC |
---|
| 49 | |
---|
| 50 | ); |
---|
| 51 | end Fifo2Mem; |
---|
| 52 | |
---|
| 53 | architecture Behavioral of Fifo2Mem is |
---|
| 54 | type typ_wr_mem is(start,write_mem,stop); |
---|
| 55 | signal et_wr_mem , next_et_wr_mem: typ_wr_mem; |
---|
| 56 | signal data_to_ram,Data_to_ram_i : std_logic_vector(Word-1 downto 0):=(others=>'0'); |
---|
| 57 | signal P_len_i,P_len : std_logic_vector(Word-1 downto 0); |
---|
| 58 | signal dma_rd,dma_wr,rd_ok ,wr_ok:std_logic:='0'; |
---|
| 59 | signal n,n_i : natural range 0 to 15:=0; |
---|
| 60 | signal dest_address,dest_address_i,ack_address : std_logic_vector(ADRLEN-1 downto 0):=(others=>'0'); |
---|
| 61 | begin |
---|
| 62 | wr_mem_sync:process(clk) |
---|
| 63 | begin |
---|
| 64 | if rising_edge(clk) then |
---|
| 65 | if reset='1' then |
---|
| 66 | n<=0; |
---|
| 67 | P_len<=(others=>'0'); |
---|
| 68 | dest_address<=(others=>'0'); |
---|
| 69 | data_to_ram<=(others=>'0'); |
---|
| 70 | else |
---|
| 71 | dest_address<=dest_address_i; |
---|
| 72 | P_len<=P_len_i; |
---|
| 73 | Data_to_ram<=data_to_ram_i; |
---|
| 74 | et_wr_mem<=next_et_wr_mem; |
---|
| 75 | n<=n_i; |
---|
| 76 | end if; |
---|
| 77 | end if; |
---|
| 78 | end process; |
---|
| 79 | wr_mem_next:process(et_wr_mem,Fifo_data_available,P_len,wr_start,datalen,fifo_data_out, |
---|
| 80 | ram_addr_start,ram_busy,dest_address) |
---|
| 81 | variable delai :natural range 0 to 1; |
---|
| 82 | begin |
---|
| 83 | |
---|
| 84 | next_et_wr_mem<=et_wr_mem; |
---|
| 85 | P_len_i<=P_len; |
---|
| 86 | dest_address_i<=dest_address; |
---|
| 87 | case et_wr_mem is |
---|
| 88 | |
---|
| 89 | when start =>if wr_start='1' then |
---|
| 90 | next_et_wr_mem<=write_mem; |
---|
| 91 | P_len_i<=datalen; |
---|
| 92 | dest_address_i<=ram_addr_start; |
---|
| 93 | end if; |
---|
| 94 | |
---|
| 95 | when write_mem=> rd_ok<='0'; |
---|
| 96 | |
---|
| 97 | |
---|
| 98 | if unsigned( P_len)>0 and wr_start='1' then |
---|
| 99 | |
---|
| 100 | if fifo_data_available = '1' and delai=0 then |
---|
| 101 | delai:=1; --une donné lue |
---|
| 102 | P_len_i <= P_len - 1; |
---|
| 103 | next_et_wr_mem<=write_mem; |
---|
| 104 | rd_ok<='1'; |
---|
| 105 | data_to_ram_i<=fifo_data_out; |
---|
| 106 | end if; |
---|
| 107 | if ram_busy='0' and delai=1 then |
---|
| 108 | wr_ok<='1'; |
---|
| 109 | dest_address_i <= dest_address + 1; |
---|
| 110 | delai:=0;--une donnée écrite |
---|
| 111 | |
---|
| 112 | else |
---|
| 113 | dest_address_i<=dest_address; |
---|
| 114 | wr_ok<='0'; |
---|
| 115 | |
---|
| 116 | end if; |
---|
| 117 | |
---|
| 118 | next_et_wr_mem<=stop; |
---|
| 119 | |
---|
| 120 | else |
---|
| 121 | rd_ok<='0'; |
---|
| 122 | Wr_ok<='0'; |
---|
| 123 | |
---|
| 124 | if ram_busy='0' and wr_start='1' then |
---|
| 125 | |
---|
| 126 | next_et_wr_mem<=stop; |
---|
| 127 | end if; |
---|
| 128 | |
---|
| 129 | end if; |
---|
| 130 | when stop =>if wr_Start='0' then --attendre que le signal start soit ramener à 0 |
---|
| 131 | next_et_wr_mem<=start; |
---|
| 132 | end if; |
---|
| 133 | end case; |
---|
| 134 | end process; |
---|
| 135 | |
---|
| 136 | process(et_wr_mem,rd_ok,wr_ok,data_to_ram,ram_addr_start,fifo_data_out) |
---|
| 137 | begin |
---|
| 138 | case et_wr_mem is |
---|
| 139 | when start =>Ram_wr<='0'; |
---|
| 140 | Ram_en<='0'; |
---|
| 141 | Ram_data_in<=data_to_ram; |
---|
| 142 | fifo_data_out_en<='0'; |
---|
| 143 | wr_comp<='0'; |
---|
| 144 | Ram_addr<=Ram_addr_start; |
---|
| 145 | when write_mem=> |
---|
| 146 | fifo_data_out_en <=rd_ok; |
---|
| 147 | if rd_ok = '1' then |
---|
| 148 | |
---|
| 149 | Ram_data_in<=fifo_data_out; |
---|
| 150 | else |
---|
| 151 | Ram_data_in<=data_to_ram; |
---|
| 152 | end if; |
---|
| 153 | ram_addr<=dest_address; |
---|
| 154 | Ram_wr<=wr_ok; |
---|
| 155 | Ram_en<=wr_ok; |
---|
| 156 | wr_comp<='0'; |
---|
| 157 | when stop => |
---|
| 158 | Ram_wr<='0'; |
---|
| 159 | Ram_en<='0'; |
---|
| 160 | ram_addr<=dest_address; |
---|
| 161 | Ram_data_in<=data_to_ram; |
---|
| 162 | fifo_data_out_en<='0'; |
---|
| 163 | wr_comp<='1'; |
---|
| 164 | |
---|
| 165 | end case; |
---|
| 166 | end process; |
---|
| 167 | end Behavioral; |
---|
| 168 | |
---|