1 | ---------------------------------------------------------------------------------- |
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2 | -- Company: |
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3 | -- Engineer: GAMOM Roland Christian |
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4 | -- |
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5 | -- Create Date: 19:16:34 05/23/2014 |
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6 | -- Design Name: |
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7 | -- Module Name: Fifo2Mem - Behavioral |
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8 | -- Project Name: |
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9 | -- Target Devices: |
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10 | -- Tool versions: |
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11 | -- Description: ce module permet de lire une fifo et d'écrire le résultat dans la mémoire Ram |
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12 | -- |
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13 | -- Dependencies: |
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14 | -- |
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15 | -- Revision: |
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16 | -- Revision 0.01 - File Created |
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17 | -- Additional Comments: |
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18 | -- |
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19 | ---------------------------------------------------------------------------------- |
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20 | library IEEE; |
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21 | use IEEE.STD_LOGIC_1164.ALL; |
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22 | Library NocLib; |
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23 | use NoCLib.CoreTypes.all; |
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24 | -- Uncomment the following library declaration if using |
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25 | -- arithmetic functions with Signed or Unsigned values |
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26 | use IEEE.NUMERIC_STD.ALL; |
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27 | use IEEE.STD_LOGIC_UNSIGNED.ALL; |
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28 | -- Uncomment the following library declaration if instantiating |
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29 | -- any Xilinx primitives in this code. |
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30 | --library UNISIM; |
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31 | --use UNISIM.VComponents.all; |
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32 | |
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33 | entity Fifo2Mem is |
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34 | Port ( clk : in STD_LOGIC; |
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35 | reset : in STD_LOGIC; |
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36 | wr_start : in STD_LOGIC; |
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37 | fifo_data_out : in STD_LOGIC_VECTOR (Word-1 downto 0); |
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38 | fifo_data_available : in STD_LOGIC; |
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39 | datalen : in STD_LOGIC_VECTOR (Word-1 downto 0); |
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40 | fifo_data_out_en : out STD_LOGIC; |
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41 | fifo_empty : in STD_LOGIC; |
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42 | ram_busy : in STD_LOGIC; |
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43 | ram_addr_start : in STD_LOGIC_VECTOR (ADRLEN-1 downto 0); |
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44 | ram_addr : out STD_LOGIC_VECTOR (ADRLEN-1 downto 0); |
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45 | ram_data_in : out STD_LOGIC_VECTOR (Word-1 downto 0); |
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46 | ram_wr : out STD_LOGIC; |
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47 | ram_en : out STD_LOGIC; |
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48 | wr_comp :out STD_LOGIC |
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49 | |
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50 | ); |
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51 | end Fifo2Mem; |
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52 | |
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53 | architecture Behavioral of Fifo2Mem is |
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54 | type typ_wr_mem is(start,write_mem,stop); |
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55 | signal et_wr_mem , next_et_wr_mem: typ_wr_mem; |
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56 | signal data_to_ram,Data_to_ram_i : std_logic_vector(Word-1 downto 0):=(others=>'0'); |
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57 | signal P_len_i,P_len : std_logic_vector(Word-1 downto 0); |
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58 | signal dma_rd,dma_wr,rd_ok ,wr_ok:std_logic:='0'; |
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59 | signal n,n_i : natural range 0 to 15:=0; |
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60 | signal dest_address,dest_address_i,ack_address : std_logic_vector(ADRLEN-1 downto 0):=(others=>'0'); |
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61 | begin |
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62 | wr_mem_sync:process(clk) |
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63 | begin |
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64 | if rising_edge(clk) then |
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65 | if reset='1' then |
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66 | n<=0; |
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67 | P_len<=(others=>'0'); |
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68 | dest_address<=(others=>'0'); |
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69 | data_to_ram<=(others=>'0'); |
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70 | else |
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71 | dest_address<=dest_address_i; |
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72 | P_len<=P_len_i; |
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73 | Data_to_ram<=data_to_ram_i; |
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74 | et_wr_mem<=next_et_wr_mem; |
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75 | n<=n_i; |
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76 | end if; |
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77 | end if; |
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78 | end process; |
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79 | wr_mem_next:process(et_wr_mem,Fifo_data_available,P_len,wr_start,datalen,fifo_data_out, |
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80 | ram_addr_start,ram_busy,dest_address) |
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81 | variable delai :natural range 0 to 1; |
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82 | begin |
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83 | |
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84 | next_et_wr_mem<=et_wr_mem; |
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85 | P_len_i<=P_len; |
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86 | dest_address_i<=dest_address; |
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87 | case et_wr_mem is |
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88 | |
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89 | when start =>if wr_start='1' then |
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90 | next_et_wr_mem<=write_mem; |
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91 | P_len_i<=datalen; |
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92 | dest_address_i<=ram_addr_start; |
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93 | end if; |
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94 | |
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95 | when write_mem=> rd_ok<='0'; |
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96 | |
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97 | |
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98 | if unsigned( P_len)>0 and wr_start='1' then |
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99 | |
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100 | if fifo_data_available = '1' and delai=0 then |
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101 | delai:=1; --une donné lue |
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102 | P_len_i <= P_len - 1; |
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103 | next_et_wr_mem<=write_mem; |
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104 | rd_ok<='1'; |
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105 | data_to_ram_i<=fifo_data_out; |
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106 | end if; |
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107 | if ram_busy='0' and delai=1 then |
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108 | wr_ok<='1'; |
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109 | dest_address_i <= dest_address + 1; |
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110 | delai:=0;--une donnée écrite |
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111 | |
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112 | else |
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113 | dest_address_i<=dest_address; |
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114 | wr_ok<='0'; |
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115 | |
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116 | end if; |
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117 | |
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118 | next_et_wr_mem<=stop; |
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119 | |
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120 | else |
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121 | rd_ok<='0'; |
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122 | Wr_ok<='0'; |
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123 | |
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124 | if ram_busy='0' and wr_start='1' then |
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125 | |
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126 | next_et_wr_mem<=stop; |
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127 | end if; |
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128 | |
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129 | end if; |
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130 | when stop =>if wr_Start='0' then --attendre que le signal start soit ramener à 0 |
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131 | next_et_wr_mem<=start; |
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132 | end if; |
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133 | end case; |
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134 | end process; |
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135 | |
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136 | process(et_wr_mem,rd_ok,wr_ok,data_to_ram,ram_addr_start,fifo_data_out) |
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137 | begin |
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138 | case et_wr_mem is |
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139 | when start =>Ram_wr<='0'; |
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140 | Ram_en<='0'; |
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141 | Ram_data_in<=data_to_ram; |
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142 | fifo_data_out_en<='0'; |
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143 | wr_comp<='0'; |
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144 | Ram_addr<=Ram_addr_start; |
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145 | when write_mem=> |
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146 | fifo_data_out_en <=rd_ok; |
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147 | if rd_ok = '1' then |
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148 | |
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149 | Ram_data_in<=fifo_data_out; |
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150 | else |
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151 | Ram_data_in<=data_to_ram; |
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152 | end if; |
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153 | ram_addr<=dest_address; |
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154 | Ram_wr<=wr_ok; |
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155 | Ram_en<=wr_ok; |
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156 | wr_comp<='0'; |
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157 | when stop => |
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158 | Ram_wr<='0'; |
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159 | Ram_en<='0'; |
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160 | ram_addr<=dest_address; |
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161 | Ram_data_in<=data_to_ram; |
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162 | fifo_data_out_en<='0'; |
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163 | wr_comp<='1'; |
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164 | |
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165 | end case; |
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166 | end process; |
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167 | end Behavioral; |
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168 | |
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