[142] | 1 | -------------------------------------------------------------------------------- |
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| 2 | -- Company: |
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| 3 | -- Engineer: GAMOM Roland Christian |
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| 4 | -- |
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| 5 | -- Create Date: 16:44:13 08/01/2012 |
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| 6 | -- Design Name: |
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| 7 | -- Module Name: C:/Core MPI/CORE_MPI/MultiMPITest.vhd |
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| 8 | -- Project Name: MPI_CORE_COMPONENTS |
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| 9 | -- Target Device: |
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| 10 | -- Tool versions: |
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| 11 | -- Description: |
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| 12 | -- |
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| 13 | -- VHDL Test Bench Created by ISE for module: MPI_NOC |
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| 14 | -- |
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| 15 | -- Dependencies: |
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| 16 | -- |
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| 17 | -- Revision: |
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| 18 | -- Revision 0.01 - File Created |
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| 19 | -- Additional Comments: |
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| 20 | -- |
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| 21 | -- |
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| 22 | -- |
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| 23 | -------------------------------------------------------------------------------- |
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| 24 | LIBRARY ieee; |
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| 25 | USE ieee.std_logic_1164.ALL; |
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| 26 | |
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| 27 | library NocLib ; |
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| 28 | |
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| 29 | use NocLib.CoreTypes.all; |
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| 30 | LIbrary MPI_HCL; |
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| 31 | use MPI_HCL.Packet_type.all; |
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| 32 | use work.Hcl_Arch_conf.all; |
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| 33 | USE ieee.numeric_std.ALL; |
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| 34 | |
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| 35 | ENTITY Mpi_template IS |
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| 36 | --simulation translate_off |
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| 37 | port (clkm : in std_logic; |
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| 38 | reset : in std_logic; |
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| 39 | sw : in std_logic_vector(3 downto 0); --bouton bascule |
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| 40 | Led : out std_logic_vector(Word-1 downto 0)); |
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| 41 | --simulation translate_on |
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| 42 | END MPi_template; |
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| 43 | |
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| 44 | ARCHITECTURE behavior OF MPI_Template IS |
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| 45 | |
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| 46 | -- Component Declaration for the Unit Under Test (UUT) |
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| 47 | |
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| 48 | COMPONENT MPI_NOC |
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| 49 | generic (NPROC: natural:=2); |
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| 50 | PORT( |
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| 51 | MPI_Node_in : IN Ar_MPIPort_in(1 to NPROC); |
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| 52 | MPI_Node_Out : OUT Ar_MPIPort_out(1 to NPROC) |
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| 53 | ); |
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| 54 | END COMPONENT; |
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| 55 | component proto_send is |
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| 56 | generic (sizemem : natural := 64); |
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| 57 | port ( |
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| 58 | clk,reset : in std_logic; |
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| 59 | fifo_in_empty,fifo_in_full : in std_logic; --signaux pour le fifo d'entrée |
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| 60 | fifo_out_empty,fifo_out_full : in std_logic; --signaux pour le fifo de sortie |
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| 61 | fifo_out_wr_en : out std_logic:='0'; --écriture autorisée dans la fifo de sortie |
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| 62 | fifo_in_rd_en : out std_logic:='0'; --lecture autorisée dans la fifo d'entrée |
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| 63 | fifo_in_data_out : in std_logic_vector(Word-1 downto 0); |
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| 64 | fifo_out_data_in : out std_logic_vector(Word-1 downto 0); |
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| 65 | packet_len : in std_logic_vector(Word-1 downto 0); --la longueur du paquet |
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| 66 | copy_mode : in std_logic; --Fifo_to_mem ou Fifo_to_fifo |
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| 67 | snd_start : in std_logic; --début de la réception |
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| 68 | snd_ack :in std_logic; -- acquittement de la réception |
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| 69 | snd_comp : out std_logic; -- fin de la réception |
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| 70 | mem :in memory(0 to sizemem-1)); --données à copier vers le fifo |
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| 71 | end component proto_send; |
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| 72 | Component Fifo2mem is |
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| 73 | Port ( clk : in STD_LOGIC; |
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| 74 | reset : in STD_LOGIC; |
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| 75 | wr_start : in STD_LOGIC; |
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| 76 | fifo_data_out : in STD_LOGIC_VECTOR (Word-1 downto 0); |
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| 77 | fifo_data_available : in STD_LOGIC; |
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| 78 | datalen : STD_LOGIC_VECTOR (Word-1 downto 0); |
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| 79 | fifo_data_out_en : out STD_LOGIC; |
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| 80 | fifo_empty : in STD_LOGIC; |
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| 81 | ram_busy : in STD_LOGIC; |
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| 82 | ram_addr_start : in STD_LOGIC_VECTOR (ADRLEN-1 downto 0); |
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| 83 | ram_addr : out STD_LOGIC_VECTOR (ADRLEN-1 downto 0); |
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| 84 | ram_data_in : out STD_LOGIC_VECTOR (Word-1 downto 0); |
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| 85 | ram_wr : out STD_LOGIC; |
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| 86 | ram_en : out STD_LOGIC; |
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| 87 | wr_comp :out STD_LOGIC); |
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| 88 | end component fifo2mem; |
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| 89 | Component PE |
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| 90 | generic(destid : natural; |
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| 91 | use_dyn:natural); |
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| 92 | Port ( Instruction : out STD_LOGIC_VECTOR (Word-1 downto 0); |
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| 93 | Instruction_en : out STD_LOGIC; |
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| 94 | Core_PushOut : in STD_LOGIC_VECTOR (Word-1 downto 0); |
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| 95 | clk : in STD_LOGIC; |
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| 96 | reset : in STD_LOGIC; |
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| 97 | CE : in STD_LOGIC; |
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| 98 | Core_RAM_Data_Out : out STD_LOGIC_VECTOR (Word-1 downto 0); |
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| 99 | Core_RAM_Data_In : in STD_LOGIC_VECTOR (Word-1 downto 0); |
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| 100 | Core_RAM_WE : in STD_LOGIC; |
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| 101 | Core_RAM_EN : in STD_LOGIC; |
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| 102 | --Core_RAM_ENB : in STD_LOGIC; |
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| 103 | Core_RAM_ADDRESS_WR : in STD_LOGIC_VECTOR (ADRLEN-1 downto 0); |
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| 104 | Core_RAM_ADDRESS_RD : in STD_LOGIC_VECTOR (ADRLEN-1 downto 0); |
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| 105 | Core_Hold_req : in STD_LOGIC; |
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| 106 | Core_Hold_Ack : out STD_LOGIC); |
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| 107 | end Component; |
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| 108 | |
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| 109 | constant clk_period : time := 15 ns; |
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| 110 | constant PROC : positive :=NOC_SIZE; --4 |
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| 111 | -- synthesis translate_off |
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| 112 | --===================signaux pour l'horloge ============================== |
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| 113 | --signal reset,clkm : std_logic := '0'; |
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| 114 | --======================================================================== |
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| 115 | -- synthesis translate_on |
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| 116 | --signaux pour la gestion de la MAE |
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| 117 | type typ_mae is (start,Fillmem,NextFill,InitApp,InitCompleted,writeptr,InstrCopy, |
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| 118 | putdata,putdata2,putcompleted,getdata,getdata2,getcompleted,terminate,st_timeout); |
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| 119 | |
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| 120 | --groupe de signaux utilisé pour communiquer avec l'extérieur de la plateforme |
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| 121 | type arDpRam is array (natural range <>) of typ_dpRam; |
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| 122 | type typ_Pconsole is(idle,get_bus,get_ht_mem,rd_ht_mem,wr_ht_mem,et_end); |
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| 123 | signal et_Pconsole,Next_et_Pconsole : typ_pconsole; |
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| 124 | signal Pcons_ram :typ_dpram; --signaux pour accès à la ram par la console |
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| 125 | signal pcons_hold_req,pcons_hold_ack: std_logic;--pour accès à la Ram du HT |
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| 126 | signal pcons_wr_comp,pcons_wr_start : std_logic;--pour contrôler l'écriture dans la Ram du HT |
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| 127 | signal pcons_rd_comp,pcons_rd_start :std_logic; |
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| 128 | signal pcons_ram_busy : std_logic:='0'; |
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| 129 | signal pcons_ht : natural range 0 to 15;--le numéro du HT qui est sollicité |
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| 130 | signal mux_hold_req,dmux_hold_ack: std_logic_vector(1 to PROC); --multiplexer les signaux d'accès RAM HT entre Core_MPI et console |
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| 131 | signal mux_ram : Ar_DpRam(1 to PROC); |
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| 132 | signal pcons_sel:std_logic_vector(1 to PROC);--état de la sélection du MUX entre Console et Core MPI |
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| 133 | -- |
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| 134 | --signaux pour le module de communication RS232C |
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| 135 | signal rs_cmd,rs_rw,rs_comp:std_logic; |
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| 136 | signal rs_addr_start:std_logic_vector(adrlen-1 downto 0); |
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| 137 | signal rs_plen :std_logic_vector(word-1 downto 0); |
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| 138 | signal rs_fifo_data_out_en:std_logic; |
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| 139 | signal rs_fifo_data_available : std_logic; |
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| 140 | signal rs_fifo_data_out :std_logic_vector(word-1 downto 0); |
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| 141 | -- |
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| 142 | signal dcount : natural range 0 to 255:=0; --permet de compter le packet de données envoyées |
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| 143 | signal count,count_i : natural range 0 to 15:=0; |
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| 144 | |
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| 145 | signal MPI_Node_in : Ar_MPIPort_in(1 to PROC) ; |
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| 146 | signal MPI_Node_Out : Ar_MPIPort_out(1 to PROC); |
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| 147 | |
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| 148 | |
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| 149 | |
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| 150 | |
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| 151 | BEGIN |
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| 152 | SysMPI: MPI_NOC GENERIC MAP (NPROC=>NOC_SIZE) |
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| 153 | PORT MAP ( |
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| 154 | MPI_Node_in => MPI_Node_in, |
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| 155 | MPI_Node_Out => MPI_Node_Out |
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| 156 | ); |
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| 157 | |
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| 158 | res_Led_sw:process (MPi_Node_out(1).PushOut,MPi_Node_out(1).PushOut) |
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| 159 | variable p:natural range 0 to 15:=0; |
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| 160 | begin |
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| 161 | p:=to_integer(unsigned(sw)); --récupérer les switchs pour définir les entrées |
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| 162 | Led<=MPi_Node_out(p).PushOut; |
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| 163 | end process; |
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| 164 | |
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| 165 | S_Grp:for i in 1 to STATIC_HT generate |
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| 166 | S: PE Generic map (DestId=>i-1, |
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| 167 | use_dyn=>0) |
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| 168 | Port Map ( |
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| 169 | Instruction => MPi_Node_in(i).Instruction, |
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| 170 | Instruction_en => MPi_Node_in(i).Instruction_en, |
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| 171 | Core_PushOut => MPi_Node_out(i).PushOut, |
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| 172 | clk =>clkm, |
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| 173 | reset =>reset, |
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| 174 | CE => '1', |
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| 175 | Core_RAM_Data_Out =>mux_ram(i).i.Data_out, |
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| 176 | Core_RAM_Data_IN => mux_ram(i).o.data_in, |
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| 177 | Core_RAM_WE => mux_ram(i).o.we, |
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| 178 | Core_RAM_EN => mux_ram(i).o.enb, |
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| 179 | Core_RAM_Address_Wr => mux_ram(i).o.addr_wr, |
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| 180 | Core_RAM_Address_Rd => mux_ram(i).o.addr_rd, |
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| 181 | Core_Hold_req => mux_hold_req(i), |
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| 182 | Core_Hold_Ack => dmux_hold_ack(i) |
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| 183 | -- Core_RAM_Data_Out =>MPi_Node_in(i).Ram_Data_out, |
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| 184 | -- Core_RAM_Data_IN => MPI_Node_out(i).ram_data_in, |
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| 185 | -- Core_RAM_WE => MPI_Node_out(i).ram_we, |
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| 186 | -- Core_RAM_EN => MPI_Node_out(i).ram_en, |
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| 187 | -- --Core_RAM_ENB => MPI_Node_out(2).ram_en, |
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| 188 | -- Core_RAM_Address_Wr => MPI_Node_out(i).ram_address_wr, |
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| 189 | -- Core_RAM_Address_Rd => MPI_Node_out(i).ram_address_rd, |
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| 190 | -- Core_Hold_req => MPI_Node_out(i).hold_req, |
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| 191 | -- Core_Hold_Ack => MPI_Node_in(i).hold_ack |
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| 192 | ); |
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| 193 | MPI_Node_in(i).reset<=reset; |
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| 194 | MPI_Node_in(i).clk<=clkm; |
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| 195 | end generate S_Grp; |
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| 196 | dyn_mod: if dyn_allowed='1' generate |
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| 197 | D_Grp:for i in STATIC_HT+1 to NOC_SIZE generate |
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| 198 | D: PE Generic map (DestId=>i-1, |
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| 199 | use_dyn=>1) |
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| 200 | Port Map ( |
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| 201 | Instruction => MPi_Node_in(i).Instruction, |
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| 202 | Instruction_en => MPi_Node_in(i).Instruction_en, |
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| 203 | Core_PushOut => MPi_Node_out(i).PushOut, |
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| 204 | clk =>clkm, |
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| 205 | reset =>reset, |
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| 206 | CE => '0', |
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| 207 | Core_RAM_Data_Out =>mux_ram(i).i.Data_out, |
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| 208 | Core_RAM_Data_IN => mux_ram(i).o.data_in, |
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| 209 | Core_RAM_WE => mux_ram(i).o.we, |
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| 210 | Core_RAM_EN => mux_ram(i).o.enb, |
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| 211 | Core_RAM_Address_Wr => mux_ram(i).o.addr_wr, |
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| 212 | Core_RAM_Address_Rd => mux_ram(i).o.addr_rd, |
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| 213 | Core_Hold_req => mux_hold_req(i), |
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| 214 | Core_Hold_Ack => dmux_hold_ack(i) |
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| 215 | ); |
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| 216 | MPI_Node_in(i).reset<=reset; |
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| 217 | MPI_Node_in(i).clk<=clkm; |
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| 218 | end generate D_Grp; |
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| 219 | end generate dyn_mod; |
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| 220 | |
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| 221 | --lecture de la mémoire de communication de chaque tâche et envoie des données |
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| 222 | -- sur le port série |
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| 223 | Pcons_sync:process(clkm) |
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| 224 | begin |
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| 225 | if rising_edge(clkm) then |
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| 226 | if reset='1' then |
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| 227 | Et_Pconsole<=idle; |
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| 228 | else |
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| 229 | et_Pconsole<=next_et_Pconsole; |
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| 230 | |
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| 231 | end if; |
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| 232 | end if; |
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| 233 | end process; |
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| 234 | Pcons_next : process(et_Pconsole,rs_cmd) |
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| 235 | variable bus_free:std_logic:='0'; |
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| 236 | begin |
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| 237 | case et_pconsole is |
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| 238 | when idle => if rs_cmd='1' then |
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| 239 | next_et_pconsole<=get_bus; |
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| 240 | end if; |
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| 241 | when get_bus => |
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| 242 | bus_free:='0'; |
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| 243 | for i in 1 to PROC loop |
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| 244 | if MPI_Node_out(i).Hold_req='0' then |
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| 245 | Pcons_sel(i)<='1'; |
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| 246 | bus_free:='1'; |
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| 247 | else |
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| 248 | Pcons_sel(i)<='0'; |
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| 249 | end if; |
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| 250 | end loop; |
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| 251 | if bus_free='1' then |
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| 252 | next_et_pconsole<=get_ht_mem; |
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| 253 | end if; |
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| 254 | when get_ht_mem => if rs_rw='1' then |
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| 255 | next_et_pconsole<=rd_ht_mem; |
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| 256 | else --if rs_rw='1' then |
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| 257 | next_et_pconsole<=wr_ht_mem; |
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| 258 | end if; |
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| 259 | when rd_ht_mem => if pcons_rd_comp='0' then |
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| 260 | next_et_pconsole<=et_end; |
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| 261 | end if; |
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| 262 | when wr_ht_mem=> if pcons_wr_comp='1' then |
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| 263 | next_et_pconsole<=et_end; |
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| 264 | |
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| 265 | end if; |
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| 266 | when et_end => |
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| 267 | for i in 1 to PROC loop |
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| 268 | Pcons_sel(i)<='0'; |
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| 269 | end loop; |
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| 270 | if rs_cmd='0' then --atendre la fin de la cmd |
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| 271 | next_et_pconsole<=idle; |
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| 272 | end if; |
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| 273 | end case; |
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| 274 | end process; |
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| 275 | Pcons_val : process(et_Pconsole) |
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| 276 | begin |
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| 277 | pcons_rd_start<='0'; |
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| 278 | pcons_wr_start<='0'; |
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| 279 | rs_comp<='0'; |
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| 280 | case et_pconsole is |
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| 281 | when idle => |
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| 282 | when get_bus => |
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| 283 | when get_ht_mem => |
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| 284 | when rd_ht_mem => pcons_rd_start<='1'; |
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| 285 | when wr_ht_mem=> pcons_wr_start<='1'; |
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| 286 | when et_end=>rs_comp<='1'; |
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| 287 | pcons_wr_start<='0'; |
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| 288 | end case; |
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| 289 | end process; |
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| 290 | --Multiplexeur de la console pour l'accès à la RAM de chaque HT. |
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| 291 | Ram_mux: process (clkm,MPI_Node_out,pcons_sel ) |
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| 292 | begin |
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| 293 | for i in 1 to PROC loop |
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| 294 | case Pcons_sel(i) is |
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| 295 | |
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| 296 | |
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| 297 | when '1' => |
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| 298 | mux_ram(i).o.addr_wr<=pcons_ram.o.addr_wr; |
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| 299 | mux_ram(i).o.addr_rd<=pcons_ram.o.addr_rd ; |
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| 300 | mux_ram(i).o.we<=pcons_ram.o.we; |
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| 301 | mux_ram(i).o.enb<=pcons_ram.o.enb; |
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| 302 | mux_ram(i).o.data_in<=pcons_ram.o.data_in; |
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| 303 | mux_hold_req(i)<=Pcons_Hold_req; |
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| 304 | when others => |
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| 305 | mux_ram(i).o.addr_wr<=MPI_Node_out(i).Ram_address_wr; |
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| 306 | mux_ram(i).o.addr_rd<=MPI_Node_out(i).Ram_address_rd ; |
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| 307 | mux_ram(i).o.we<=MPI_Node_out(i).Ram_we; |
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| 308 | mux_ram(i).o.enb<=MPI_Node_out(i).Ram_en; |
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| 309 | mux_ram(i).o.data_in<=MPI_Node_out(i).Ram_data_in; |
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| 310 | mux_hold_req(i)<=MPI_Node_out(i).Hold_req; |
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| 311 | end case ; |
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| 312 | end loop; |
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| 313 | end process ; |
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| 314 | --écriture dans la mémoire d'une tâche matérielle |
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| 315 | Inst_Fifo2Mem: Fifo2Mem PORT MAP( |
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| 316 | clk =>clkm , |
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| 317 | reset =>reset , |
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| 318 | wr_start =>pcons_wr_start , |
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| 319 | fifo_data_out => rs_fifo_data_out, |
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| 320 | fifo_data_available =>rs_fifo_data_available , |
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| 321 | datalen =>rs_plen , |
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| 322 | fifo_data_out_en =>rs_fifo_data_out_en , |
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| 323 | fifo_empty =>'0' , |
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| 324 | ram_busy => pcons_ram_busy, --not pcons_sel(pcons_ht) , |
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| 325 | ram_addr_start =>rs_addr_start , |
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| 326 | ram_addr =>pcons_ram.o.addr_wr, |
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| 327 | ram_data_in =>pcons_ram.o.data_in , |
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| 328 | ram_wr =>pcons_ram.o.we , |
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| 329 | ram_en =>pcons_ram.o.enb , |
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| 330 | wr_comp =>pcons_wr_comp |
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| 331 | ); |
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| 332 | --démultiplexeurs de la console pour accès à la RAM de chaque Tâche matérielle. |
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| 333 | Ram_dmux : process(MPI_node_in,mux_ram,PCons_sel,pcons_ht) |
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| 334 | variable Tram_out:std_logic_vector(Word-1 downto 0):=(others=>'0'); |
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| 335 | begin |
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| 336 | for i in 1 to PROC loop |
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| 337 | case PCons_sel(i) is |
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| 338 | |
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| 339 | when '1' => if pcons_ht=i then |
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| 340 | Pcons_hold_ack<=dmux_hold_ack(i); |
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| 341 | end if; |
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| 342 | --Pcons_ram.I.data_out<=mux_ram(i).i.data_out; |
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| 343 | if i=pcons_ht then |
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| 344 | Pcons_ram.I.data_out<=mux_ram(i).i.data_out; |
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| 345 | else |
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| 346 | TRam_out:=Tram_out or mux_ram(i).i.data_out; |
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| 347 | end if; |
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| 348 | MPI_Node_in(i).hold_ack<='0'; |
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| 349 | MPI_Node_in(i).Ram_data_out<=(others=>'-'); |
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| 350 | when others => Pcons_hold_ack<='0'; |
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| 351 | --Pcons_ram.I.data_out<=(others=>'-'); |
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| 352 | TRam_out:=(others=>'-'); |
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| 353 | MPI_Node_in(i).hold_ack<=dmux_hold_ack(i); |
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| 354 | MPI_Node_in(i).Ram_data_out<=mux_ram(i).i.data_out; |
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| 355 | end case; |
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| 356 | end loop; |
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| 357 | |
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| 358 | end process; |
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| 359 | END; |
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