[142] | 1 | ---------------------------------------------------------------------------------- |
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| 2 | -- Company: |
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| 3 | -- Engineer: GAMOM NGOUNOU |
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| 4 | -- |
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| 5 | -- Create Date: 18:33:31 03/05/2012 |
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| 6 | -- Design Name: |
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| 7 | -- Module Name: RAM_32_32 - Behavioral |
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| 8 | -- Project Name: MPI_Core |
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| 9 | -- Target Devices: |
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| 10 | -- Tool versions: |
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| 11 | -- Description: permet de stocker les données locales de la librairie MPI |
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| 12 | -- |
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| 13 | -- Dependencies: |
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| 14 | -- |
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| 15 | -- Revision: |
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| 16 | -- Revision 0.01 - File Created |
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| 17 | -- Additional Comments: |
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| 18 | -- |
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| 19 | ---------------------------------------------------------------------------------- |
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| 20 | library IEEE; |
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| 21 | use IEEE.STD_LOGIC_1164.ALL; |
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| 22 | use IEEE.STD_LOGIC_ARITH.ALL; |
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| 23 | use IEEE.STD_LOGIC_UNSIGNED.ALL; |
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| 24 | -- Uncomment the following library declaration if using |
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| 25 | -- arithmetic functions with Signed or Unsigned values |
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| 26 | --use IEEE.NUMERIC_STD.ALL; |
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| 27 | |
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| 28 | -- Uncomment the following library declaration if instantiating |
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| 29 | -- any Xilinx primitives in this code. |
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| 30 | --library UNISIM; |
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| 31 | --use UNISIM.VComponents.all; |
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| 32 | |
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| 33 | entity RAM_v is |
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| 34 | generic(width : positive:=32; Size:positive:=16); |
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| 35 | Port ( clka, clkb : in std_logic; |
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| 36 | wea : in std_logic; |
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| 37 | ena, enb : in std_logic; |
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| 38 | addra, addrb : in std_logic_vector(size-1 downto 0); --cinq lignes d'adresse |
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| 39 | dia : in std_logic_vector(width-1 downto 0); |
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| 40 | dob : out std_logic_vector(width-1 downto 0)); |
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| 41 | end RAM_v; |
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| 42 | |
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| 43 | architecture Behavioral of RAM_v is |
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| 44 | attribute RAM_STYLE : string; |
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| 45 | signal Lra,Lrb :std_logic:='0'; |
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| 46 | signal sel : std_logic_vector(1 downto 0); |
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| 47 | signal read_addr:std_logic_vector(12 downto 0); |
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| 48 | signal doa,dout : std_logic_vector(width-1 downto 0); |
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| 49 | type ram_type is array (2**(size-3)-1 downto 0) of std_logic_vector (width-1 downto 0); |
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| 50 | signal RAM1,RAM2: ram_type; |
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| 51 | attribute RAM_STYLE of RAM1: signal is "BLOCK"; |
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| 52 | attribute RAM_STYLE of RAM2: signal is "BLOCK"; |
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| 53 | begin |
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| 54 | process (clka) |
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| 55 | begin |
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| 56 | if clka'event and clka = '1' then |
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| 57 | if ena = '1' then |
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| 58 | if wea = '1' then |
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| 59 | |
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| 60 | RAM1(conv_integer(addra(12 downto 0))) <= dia; |
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| 61 | -- RAM2(conv_integer(addra(12 downto 0))) <= dia; |
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| 62 | end if; |
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| 63 | end if; |
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| 64 | --if conv_integer(addrb)>8191 then |
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| 65 | -- report "Erreur d'adresse"; |
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| 66 | -- else |
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| 67 | -- doa<=RAM1(conv_integer(addrb)); |
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| 68 | -- end if; |
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| 69 | -- Lra<='1'; |
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| 70 | -- else |
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| 71 | -- if lrb='1' then |
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| 72 | -- Lra<='0'; |
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| 73 | -- end if; |
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| 74 | -- end if; |
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| 75 | if conv_integer(addra)>8191 then |
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| 76 | report "Erreur adresse Ecriture > 8191" |
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| 77 | severity warning; |
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| 78 | end if; |
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| 79 | end if; |
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| 80 | end process; |
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| 81 | |
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| 82 | |
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| 83 | process (clkb) |
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| 84 | begin |
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| 85 | if clkb'event and clkb = '1' then |
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| 86 | |
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| 87 | if enb = '1' and ena='1' and addra=addrb then |
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| 88 | --dout <= dia; --la sortie est égale à l'entrée |
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| 89 | report "Collision R/W à l'adresse " & integer'image(conv_integer(addra)) |
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| 90 | severity note; |
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| 91 | read_addr<=addrb(12 downto 0); |
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| 92 | Lra<='1'; |
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| 93 | elsif enb='1' then |
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| 94 | read_addr<=addrb(12 downto 0); |
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| 95 | Lrb<='1'; |
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| 96 | -- dout <= RAM2(conv_integer(addrb(12 downto 0))); |
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| 97 | else |
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| 98 | if Lra='1' then |
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| 99 | Lrb<='0'; |
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| 100 | end if; |
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| 101 | end if; |
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| 102 | if conv_integer(addrb)>8191 then |
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| 103 | report "Erreur adresse de lecture > 8191" |
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| 104 | severity warning; |
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| 105 | end if; |
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| 106 | end if; |
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| 107 | end process; |
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| 108 | --dob<=dout; |
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| 109 | dob <= RAM1(conv_integer(read_addr)); |
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| 110 | --sel<=(Lra,Lrb); |
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| 111 | -- With sel select |
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| 112 | -- dob <=dout when "11", |
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| 113 | -- doa when "10", |
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| 114 | -- dout when "01", |
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| 115 | -- dout when "00", |
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| 116 | -- dout when others; |
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| 117 | |
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| 118 | end Behavioral; |
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| 119 | |
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