1 | ---------------------------------------------------------------------------------- |
---|
2 | -- Company: |
---|
3 | -- Engineer: GAMOM NGOUNOU |
---|
4 | -- |
---|
5 | -- Create Date: 18:33:31 03/05/2012 |
---|
6 | -- Design Name: |
---|
7 | -- Module Name: RAM_32_32 - Behavioral |
---|
8 | -- Project Name: MPI_Core |
---|
9 | -- Target Devices: |
---|
10 | -- Tool versions: |
---|
11 | -- Description: permet de stocker les données locales de la librairie MPI |
---|
12 | -- |
---|
13 | -- Dependencies: |
---|
14 | -- |
---|
15 | -- Revision: |
---|
16 | -- Revision 0.01 - File Created |
---|
17 | -- Additional Comments: |
---|
18 | -- |
---|
19 | ---------------------------------------------------------------------------------- |
---|
20 | library IEEE; |
---|
21 | use IEEE.STD_LOGIC_1164.ALL; |
---|
22 | use IEEE.STD_LOGIC_ARITH.ALL; |
---|
23 | use IEEE.STD_LOGIC_UNSIGNED.ALL; |
---|
24 | -- Uncomment the following library declaration if using |
---|
25 | -- arithmetic functions with Signed or Unsigned values |
---|
26 | --use IEEE.NUMERIC_STD.ALL; |
---|
27 | |
---|
28 | -- Uncomment the following library declaration if instantiating |
---|
29 | -- any Xilinx primitives in this code. |
---|
30 | --library UNISIM; |
---|
31 | --use UNISIM.VComponents.all; |
---|
32 | |
---|
33 | entity RAM_v is |
---|
34 | generic(width : positive:=32; Size:positive:=16); |
---|
35 | Port ( clka, clkb : in std_logic; |
---|
36 | wea : in std_logic; |
---|
37 | ena, enb : in std_logic; |
---|
38 | addra, addrb : in std_logic_vector(size-1 downto 0); --cinq lignes d'adresse |
---|
39 | dia : in std_logic_vector(width-1 downto 0); |
---|
40 | dob : out std_logic_vector(width-1 downto 0)); |
---|
41 | end RAM_v; |
---|
42 | |
---|
43 | architecture Behavioral of RAM_v is |
---|
44 | attribute RAM_STYLE : string; |
---|
45 | signal Lra,Lrb :std_logic:='0'; |
---|
46 | signal sel : std_logic_vector(1 downto 0); |
---|
47 | signal read_addr:std_logic_vector(12 downto 0); |
---|
48 | signal doa,dout : std_logic_vector(width-1 downto 0); |
---|
49 | type ram_type is array (2**(size-3)-1 downto 0) of std_logic_vector (width-1 downto 0); |
---|
50 | signal RAM1,RAM2: ram_type; |
---|
51 | attribute RAM_STYLE of RAM1: signal is "BLOCK"; |
---|
52 | attribute RAM_STYLE of RAM2: signal is "BLOCK"; |
---|
53 | begin |
---|
54 | process (clka) |
---|
55 | begin |
---|
56 | if clka'event and clka = '1' then |
---|
57 | if ena = '1' then |
---|
58 | if wea = '1' then |
---|
59 | |
---|
60 | RAM1(conv_integer(addra(12 downto 0))) <= dia; |
---|
61 | -- RAM2(conv_integer(addra(12 downto 0))) <= dia; |
---|
62 | end if; |
---|
63 | end if; |
---|
64 | --if conv_integer(addrb)>8191 then |
---|
65 | -- report "Erreur d'adresse"; |
---|
66 | -- else |
---|
67 | -- doa<=RAM1(conv_integer(addrb)); |
---|
68 | -- end if; |
---|
69 | -- Lra<='1'; |
---|
70 | -- else |
---|
71 | -- if lrb='1' then |
---|
72 | -- Lra<='0'; |
---|
73 | -- end if; |
---|
74 | -- end if; |
---|
75 | if conv_integer(addra)>8191 then |
---|
76 | report "Erreur adresse Ecriture > 8191" |
---|
77 | severity warning; |
---|
78 | end if; |
---|
79 | end if; |
---|
80 | end process; |
---|
81 | |
---|
82 | |
---|
83 | process (clkb) |
---|
84 | begin |
---|
85 | if clkb'event and clkb = '1' then |
---|
86 | |
---|
87 | if enb = '1' and ena='1' and addra=addrb then |
---|
88 | --dout <= dia; --la sortie est égale à l'entrée |
---|
89 | report "Collision R/W à l'adresse " & integer'image(conv_integer(addra)) |
---|
90 | severity note; |
---|
91 | read_addr<=addrb(12 downto 0); |
---|
92 | Lra<='1'; |
---|
93 | elsif enb='1' then |
---|
94 | read_addr<=addrb(12 downto 0); |
---|
95 | Lrb<='1'; |
---|
96 | -- dout <= RAM2(conv_integer(addrb(12 downto 0))); |
---|
97 | else |
---|
98 | if Lra='1' then |
---|
99 | Lrb<='0'; |
---|
100 | end if; |
---|
101 | end if; |
---|
102 | if conv_integer(addrb)>8191 then |
---|
103 | report "Erreur adresse de lecture > 8191" |
---|
104 | severity warning; |
---|
105 | end if; |
---|
106 | end if; |
---|
107 | end process; |
---|
108 | --dob<=dout; |
---|
109 | dob <= RAM1(conv_integer(read_addr)); |
---|
110 | --sel<=(Lra,Lrb); |
---|
111 | -- With sel select |
---|
112 | -- dob <=dout when "11", |
---|
113 | -- doa when "10", |
---|
114 | -- dout when "01", |
---|
115 | -- dout when "00", |
---|
116 | -- dout when others; |
---|
117 | |
---|
118 | end Behavioral; |
---|
119 | |
---|