1 | library ieee; |
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2 | use ieee.std_logic_unsigned.all; |
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3 | use ieee.std_logic_1164.all; |
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4 | use ieee.std_logic_arith.all; |
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5 | |
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6 | entity com_icap is |
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7 | generic ( hexmode : boolean := true; -- false is for faster binary mode, but will not work on all machines/boards |
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8 | ComRate : integer := 217); -- ComRate = f_CLK / Boud_rate (e.g., 25 MHz/115200 Boud = 217) |
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9 | port ( |
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10 | CLK: in std_logic; |
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11 | Rx: in std_logic; --entrée série des données |
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12 | Tx: out std_logic; |
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13 | RxErr: out std_logic; --erreur de réception |
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14 | debug0: out std_logic_vector(19 downto 0); |
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15 | debug1: out std_logic_vector(19 downto 0); |
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16 | debug2: out std_logic_vector(19 downto 0); |
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17 | bs_load_start : in std_logic; --début de réception bitstream |
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18 | bs_load_comp : out std_logic; --fin de réception |
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19 | bs_load_ack : in std_logic; --acquitement bistream |
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20 | bs_load_data : out std_logic_vector(31 downto 0); |
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21 | rxWord : out std_logic_vector(7 downto 0); -- mot reçu |
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22 | RxRdy : out std_logic; --données reçues |
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23 | WriteData: out std_logic_vector(31 downto 0); |
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24 | ComActive: out std_logic; |
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25 | WriteStrobe: out std_logic; --valide l'écriture sur l'ICAP |
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26 | ReceiveLED: out std_logic); |
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27 | end com_icap; |
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28 | |
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29 | architecture a_com_icap of com_icap is |
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30 | |
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31 | constant TimeToSendValue : integer := 16777216-1; --200000000; |
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32 | constant CRC_InitValue : std_logic_vector(15 downto 0) := "1111111111111111"; |
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33 | constant TestFileChecksum : std_logic_vector(19 downto 0) := x"40351"; --à changer en fonction du bitstream |
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34 | |
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35 | function ASCII2HEX(ASCII: std_logic_vector(7 downto 0)) return std_logic_vector is |
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36 | begin |
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37 | case ASCII is |
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38 | when x"30" => return "00000"; -- 0 |
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39 | when x"31" => return "00001"; |
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40 | when x"32" => return "00010"; |
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41 | when x"33" => return "00011"; |
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42 | when x"34" => return "00100"; |
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43 | when x"35" => return "00101"; |
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44 | when x"36" => return "00110"; |
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45 | when x"37" => return "00111"; |
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46 | when x"38" => return "01000"; |
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47 | when x"39" => return "01001"; |
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48 | when x"41" => return "01010"; -- A |
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49 | when x"61" => return "01010"; -- a |
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50 | when x"42" => return "01011"; -- B |
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51 | when x"62" => return "01011"; -- b |
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52 | when x"43" => return "01100"; -- C |
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53 | when x"63" => return "01100"; -- c |
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54 | when x"44" => return "01101"; -- D |
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55 | when x"64" => return "01101"; -- d |
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56 | when x"45" => return "01110"; -- E |
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57 | when x"65" => return "01110"; -- e |
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58 | when x"46" => return "01111"; -- F |
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59 | when x"66" => return "01111"; -- f |
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60 | when others =>return "1----"; -- The MSB encodes if there was an unknown code -> error |
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61 | end case; |
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62 | end; |
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63 | |
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64 | type ReceiveStateType is (HighNibble, LowNibble); |
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65 | signal ReceiveState : ReceiveStateType; |
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66 | signal HighReg : std_logic_vector(3 downto 0); |
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67 | signal HexValue : std_logic_vector(4 downto 0); -- a '0' MSB indicates a valid value on [3..0] |
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68 | signal HexData : std_logic_vector(7 downto 0); -- the received byte in hexmode mode |
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69 | signal HexWriteStrobe : std_logic; -- we received two hex nibles and have a result byte |
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70 | signal Stop_Err,rec_ok :std_logic:='0'; |
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71 | signal ComCount : integer range 0 to 4095; |
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72 | signal ComTick : std_logic; |
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73 | type ComStateType is (WaitForStartBit, DelayAfterStartBit, GetBit0, GetBit1, GetBit2, |
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74 | GetBit3, GetBit4, GetBit5, GetBit6, GetBit7, GetStopBit); |
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75 | type loadbs_Type is(idle,read_word0,read_word1,read_word2,read_word3,check_sync,reset_reg,write_icap,end_loadbs); |
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76 | signal ComState,Next_ComState : ComStateType; |
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77 | signal et_loadbs,Next_et_loadbs:loadbs_Type; |
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78 | signal ReceivedWord,receivedSwap : std_logic_vector(7 downto 0); |
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79 | signal RxLocal : std_logic; |
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80 | |
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81 | --signal W0, W1, W2, W3, W4, W5, W6, W7 : std_logic_vector(7 downto 0); |
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82 | |
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83 | signal ID_Reg : std_logic_vector(23 downto 0); |
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84 | signal fifo_reg,fifo_reg_i : std_logic_vector(31 downto 0); --registre de détection de début du bitstream |
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85 | signal sync_ok,desync_ok,cmd_detected:std_logic; |
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86 | signal sync_ok_i,desync_ok_i,cmd_detected_i:std_logic; |
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87 | signal reading : std_logic:='0'; |
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88 | constant sync_reg : std_logic_vector(31 downto 0):=x"AA995566"; |
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89 | constant desync_cmd : std_logic_vector(31 downto 0) :=x"30008001"; |
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90 | constant desync_word : std_logic_vector(31 downto 0):=x"0000000D"; |
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91 | signal Start_Reg : std_logic_vector(31 downto 0); |
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92 | signal Size_Reg : std_logic_vector(31 downto 0); |
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93 | signal CRC_Reg : std_logic_vector(15 downto 0); |
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94 | signal Command_Reg : std_logic_vector(7 downto 0); |
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95 | signal Data_Reg : std_logic_vector(7 downto 0); |
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96 | |
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97 | signal TimeToSend : std_logic; |
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98 | signal TimeToSendCounter : integer range 0 to TimeToSendValue; |
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99 | |
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100 | type PresentType is (Idle, GetID_00, GetID_AA, GetID_FF, |
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101 | GetSize3, GetSize2, GetSize1, GetSize0, |
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102 | GetCommand, EvalCommand, |
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103 | GetData, GetFinish); |
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104 | signal PresentState : PresentType; |
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105 | |
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106 | signal scan_count : integer range 0 to 63; |
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107 | constant tast_entprell : integer := 2000000; -- 100 ms; |
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108 | signal tast_count : integer range 0 to tast_entprell; |
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109 | signal tast_trigger, tast_trigger_delay : std_logic; |
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110 | |
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111 | signal feedback_mode : std_logic := '0'; |
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112 | signal swap_mode : std_logic := '0'; |
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113 | |
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114 | signal LocalWriteStrobe : std_logic; |
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115 | |
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116 | signal local_scan_control, local_scan_control_delay : std_logic := '0'; |
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117 | signal scan_shift_strobe_from_receiver : std_logic; |
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118 | signal tx_write_strobe_from_receiver : std_logic; |
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119 | signal tx_write_strobe : std_logic; |
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120 | |
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121 | signal state_counter : integer range 0 to 127 := 0; |
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122 | signal com_en: std_logic; |
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123 | signal com_en_counter : natural range 0 to 511; |
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124 | signal com_active_counter : natural range 0 to 40000; |
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125 | signal TxOut: std_logic; |
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126 | |
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127 | signal Word_Count : std_logic_vector(31 downto 0); |
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128 | --signal ADR_Reg : std_logic_vector(31 downto 0); |
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129 | |
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130 | signal CRCReg,b_counter : std_logic_vector(19 downto 0) := TestFileChecksum; |
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131 | signal ReceivedWordDebug : std_logic_vector(7 downto 0); |
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132 | signal blink : std_logic_vector(22 downto 0) := (others => '0'); |
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133 | |
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134 | begin |
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135 | |
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136 | P_sync:process(clk) |
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137 | begin |
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138 | if clk'event AND clk='1' then |
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139 | RxLocal <= Rx; |
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140 | Tx <= TxOUT; |
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141 | end if; -- clk; |
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142 | end process; |
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143 | |
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144 | P_com_en:process(clk) |
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145 | begin |
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146 | if clk'event AND clk='1' then |
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147 | if ComState=WaitForStartBit then |
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148 | ComCount <= ComRate/2; -- @ 25 MHz --vérifier le demi-bit |
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149 | ComTick <= '0'; |
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150 | elsif ComCount=0 then |
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151 | ComCount <= ComRate; |
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152 | ComTick <= '1'; |
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153 | else |
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154 | ComCount <= ComCount - 1; |
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155 | ComTick <= '0'; |
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156 | end if; |
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157 | end if; -- clk |
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158 | end process; |
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159 | |
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160 | P_COM:process(clk) |
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161 | begin |
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162 | if clk'event AND clk='1' then |
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163 | Rec_Ok<='0'; |
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164 | case ComState is |
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165 | when WaitForStartBit => |
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166 | if RxLocal='0' then |
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167 | ComState <= DelayAfterStartBit; |
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168 | ReceivedWord <= (others => '0'); |
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169 | ReceivedSwap<= (others => '0'); |
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170 | Stop_Err<='0'; |
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171 | end if; |
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172 | when DelayAfterStartBit => |
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173 | if ComTick='1' then |
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174 | if rxLocal='0' then |
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175 | ComState <= GetBit0; |
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176 | Stop_Err<='0'; |
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177 | else |
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178 | Stop_Err<='1'; |
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179 | ComState <=WaitForStartBit; --Erreur de stop trame incorrecte ! |
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180 | end if; |
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181 | end if; |
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182 | when GetBit0 => |
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183 | if ComTick='1' then |
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184 | ComState <= GetBit1; |
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185 | ReceivedWord(0) <= RxLocal; |
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186 | ReceivedSwap(7) <= RxLocal; |
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187 | end if; |
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188 | when GetBit1 => |
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189 | if ComTick='1' then |
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190 | ComState <= GetBit2; |
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191 | ReceivedWord(1) <= RxLocal; |
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192 | ReceivedSwap(6) <= RxLocal; |
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193 | end if; |
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194 | when GetBit2 => |
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195 | if ComTick='1' then |
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196 | ComState <= GetBit3; |
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197 | ReceivedWord(2) <= RxLocal; |
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198 | ReceivedSwap(5) <= RxLocal; |
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199 | end if; |
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200 | when GetBit3 => |
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201 | if ComTick='1' then |
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202 | ComState <= GetBit4; |
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203 | ReceivedWord(3) <= RxLocal; |
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204 | ReceivedSwap(4) <= RxLocal; |
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205 | end if; |
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206 | when GetBit4 => |
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207 | if ComTick='1' then |
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208 | ComState <= GetBit5; |
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209 | ReceivedWord(4) <= RxLocal; |
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210 | ReceivedSwap(3) <= RxLocal; |
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211 | end if; |
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212 | when GetBit5 => |
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213 | if ComTick='1' then |
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214 | ComState <= GetBit6; |
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215 | ReceivedWord(5) <= RxLocal; |
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216 | ReceivedSwap(2) <= RxLocal; |
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217 | end if; |
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218 | when GetBit6 => |
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219 | if ComTick='1' then |
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220 | ComState <= GetBit7; |
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221 | ReceivedWord(6) <= RxLocal; |
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222 | ReceivedSwap(1) <= RxLocal; |
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223 | end if; |
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224 | when GetBit7 => |
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225 | if ComTick='1' then |
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226 | ComState <= GetStopBit; |
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227 | ReceivedWord(7) <= RxLocal; |
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228 | ReceivedSwap(0) <= RxLocal; |
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229 | end if; |
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230 | when GetStopBit => |
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231 | if ComTick='1' then |
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232 | ComState <= WaitForStartBit; |
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233 | end if; |
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234 | Rec_Ok<='1'; |
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235 | end case; |
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236 | end if; --clk |
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237 | end process P_COM; |
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238 | |
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239 | --Get_header:process(comState,presentState,ReceivedWord,ComTick) |
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240 | --begin |
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241 | -- |
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242 | -- if ComState=GetStopBit AND ComTick='1' then |
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243 | -- case PresentState is |
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244 | -- when GetID_00 => ID_Reg(23 downto 16) <= ReceivedWord; |
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245 | -- when GetID_AA => ID_Reg(15 downto 8) <= ReceivedWord; |
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246 | -- when GetID_FF => ID_Reg(7 downto 0) <= ReceivedWord; |
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247 | -- when GetSize0 => Size_Reg(31 downto 24) <= ReceivedWord; |
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248 | -- when GetSize1 => Size_Reg(23 downto 16) <= ReceivedWord; |
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249 | -- when GetSize2 => Size_Reg(15 downto 8) <= ReceivedWord; |
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250 | -- when GetSize3 => Size_Reg(7 downto 0) <= ReceivedWord; |
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251 | ---- when GetStart3 => Start_Reg(31 downto 24) <= ReceivedWord; |
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252 | ---- when GetStart2 => Start_Reg(23 downto 16) <= ReceivedWord; |
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253 | ---- when GetStart1 => Start_Reg(15 downto 8) <= ReceivedWord; |
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254 | ---- when GetStart0 => Start_Reg(7 downto 0) <= ReceivedWord; |
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255 | ---- when GetSize3 => Size_Reg(31 downto 24) <= ReceivedWord; |
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256 | ---- when GetSize2 => Size_Reg(23 downto 16) <= ReceivedWord; |
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257 | ---- when GetSize1 => Size_Reg(15 downto 8) <= ReceivedWord; |
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258 | ---- when GetSize0 => Size_Reg(7 downto 0) <= ReceivedWord; |
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259 | ---- when GetCRC_H => CRC_Reg(15 downto 8) <= ReceivedWord; |
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260 | ---- when GetCRC_L => CRC_Reg(7 downto 0) <= ReceivedWord; |
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261 | -- when GetCommand => Command_Reg <= ReceivedWord; |
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262 | -- when GetData => Data_Reg <= ReceivedWord; |
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263 | -- when others => |
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264 | -- end case; |
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265 | -- end if; |
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266 | --end process get_header ; |
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267 | |
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268 | --P_FSM:process(clk) |
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269 | --begin |
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270 | -- if clk'event AND clk='1' then |
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271 | -- case PresentState is |
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272 | -- when Idle => |
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273 | -- if ComState=WaitForStartBit AND RxLocal='0' then PresentState <= GetID_00; end if; |
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274 | -- when GetID_00 => |
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275 | -- if TimeToSend='1' then PresentState<=Idle; |
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276 | -- elsif ComState=GetStopBit AND ComTick='1' then PresentState <= GetID_AA; end if; |
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277 | -- when GetID_AA => |
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278 | -- if TimeToSend='1' then PresentState<=Idle; |
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279 | -- elsif ComState=GetStopBit AND ComTick='1' then PresentState <= GetID_FF; end if; |
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280 | -- when GetID_FF => |
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281 | -- if TimeToSend='1' then PresentState<=Idle; |
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282 | -- elsif ComState=GetStopBit AND ComTick='1' then PresentState <= GetSize3; end if; |
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283 | -- when GetSize3 => |
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284 | -- if TimeToSend='1' then PresentState<=Idle; |
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285 | -- elsif ComState=GetStopBit AND ComTick='1' then PresentState <= GetSize2; end if; |
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286 | -- when GetSize2 => |
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287 | -- if TimeToSend='1' then PresentState<=Idle; |
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288 | -- elsif ComState=GetStopBit AND ComTick='1' then PresentState <= GetSize1; end if; |
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289 | -- when GetSize1 => |
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290 | -- if TimeToSend='1' then PresentState<=Idle; |
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291 | -- elsif ComState=GetStopBit AND ComTick='1' then PresentState <= GetSize0; end if; |
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292 | -- when GetSize0 => |
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293 | -- if TimeToSend='1' then PresentState<=Idle; |
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294 | -- elsif ComState=GetStopBit AND ComTick='1' then PresentState <= GetCommand; end if; |
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295 | -- when GetCommand => |
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296 | -- if TimeToSend='1' then PresentState<=Idle; |
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297 | -- elsif ComState=GetStopBit AND ComTick='1' then PresentState <= EvalCommand; end if; |
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298 | -- when EvalCommand => |
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299 | -- if ID_Reg=x"00AAFF" AND (Command_Reg=x"01" OR Command_Reg=x"02")then |
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300 | -- PresentState <= GetData; |
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301 | -- else |
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302 | -- PresentState <= Idle; |
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303 | -- end if; |
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304 | -- when GetData => |
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305 | -- if TimeToSend='1' then PresentState<=Idle; |
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306 | -- elsif Word_Count=0 AND LocalWriteStrobe='1' then |
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307 | -- PresentState <= GetFinish; |
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308 | ---- elsif ComState=GetStopBit AND ComTick='1' then PresentState <= GetData2; |
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309 | -- end if; |
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310 | ---- when GetData0 => |
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311 | ---- if TimeToSend='1' then PresentState<=Idle; |
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312 | ---- elsif ComState=GetStopBit AND ComTick='1' then |
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313 | ---- if Word_Count /= 0 then |
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314 | ---- PresentState <= GetData3; |
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315 | ---- else |
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316 | ---- PresentState <= GetFinish; |
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317 | ---- end if; |
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318 | ---- end if; |
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319 | -- when GetFinish => |
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320 | -- PresentState <= Idle; |
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321 | -- end case; |
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322 | -- end if;--clk |
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323 | --end process; |
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324 | --Command <= Command_Reg; |
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325 | |
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326 | --L_hexmode : if (hexmode=true) generate |
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327 | -- |
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328 | -- HexValue <= ASCII2HEX(ReceivedWord); |
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329 | -- |
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330 | -- process(clk) |
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331 | -- begin |
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332 | -- if CLK'event AND CLK='1' then |
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333 | -- if PresentState/=GetData then |
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334 | -- ReceiveState <= HighNibble; |
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335 | -- elsif ComState=GetStopBit AND ComTick='1' AND HexValue(HexValue'high)='0' then |
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336 | -- if(ReceiveState=HighNibble) then |
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337 | -- ReceiveState <= LowNibble; |
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338 | -- else |
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339 | -- ReceiveState <= HighNibble; |
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340 | -- end if; |
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341 | -- end if; |
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342 | -- end if; -- CLK |
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343 | -- end process; |
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344 | -- |
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345 | -- process(clk) |
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346 | -- begin |
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347 | -- if CLK'event AND CLK='1' then |
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348 | -- if ComState=GetStopBit AND ComTick='1' AND HexValue(HexValue'high)='0' then |
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349 | -- if(ReceiveState=HighNibble) then |
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350 | -- HighReg <= HexValue(3 downto 0); |
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351 | -- HexWriteStrobe <= '0'; |
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352 | -- else -- LowNibble |
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353 | -- HexData <= HighReg & HexValue(3 downto 0); |
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354 | -- HexWriteStrobe <= '1'; |
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355 | -- end if; |
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356 | -- else |
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357 | -- HexWriteStrobe <= '0'; |
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358 | -- end if; |
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359 | -- end if; -- CLK |
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360 | -- end process; |
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361 | -- |
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362 | --end generate; |
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363 | debug0 <= CRCReg; |
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364 | --debug1(7 downto 0) <= ID_Reg(15 downto 8); |
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365 | --debug2(7 downto 0) <= ID_Reg(7 downto 0); |
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366 | --debug0 <= CRCReg; |
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367 | debug1(8 downto 0) <= Rec_ok & ReceivedWord ; |
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368 | debug2 <= HexValue(3 downto 0) & ReceivedWordDebug & ReceivedWord ; |
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369 | |
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370 | --P_checksum:process(clk) |
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371 | --begin |
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372 | -- if clk'event AND clk='1' then |
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373 | -- if PresentState=GetCommand then -- init before data arrives |
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374 | -- CRCReg <= (others => '0'); |
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375 | -- b_counter <= (others => '0'); |
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376 | -- elsif hexmode=true then |
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377 | -- if ComState=GetStopBit AND ComTick='1' AND HexValue(HexValue'high)='0' AND PresentState=GetData AND ReceiveState=LowNibble then |
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378 | -- CRCReg <= CRCReg + (HighReg & HexValue(3 downto 0)); |
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379 | -- b_counter <= b_counter +1; |
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380 | -- end if; |
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381 | -- else -- binary mode |
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382 | -- if ComState=GetStopBit AND ComTick='1' AND (PresentState=GetData) then |
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383 | -- CRCReg <= CRCReg + ReceivedWord; |
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384 | -- b_counter <= b_counter +1; |
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385 | -- end if; |
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386 | -- end if; -- checksum computation |
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387 | -- |
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388 | -- if (PresentState=GetData) then |
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389 | -- ReceiveLED <= '1'; -- receive process in progress |
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390 | -- elsif (PresentState=Idle) and (CRCReg/=TestFileChecksum) then |
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391 | -- ReceiveLED <= blink(blink'high); |
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392 | -- else |
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393 | -- ReceiveLED <= '0'; -- receive process was OK |
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394 | -- end if; |
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395 | -- |
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396 | -- blink <= blink -1; |
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397 | -- |
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398 | -- end if; --clk |
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399 | --end process; |
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400 | |
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401 | --P_bus:process(clk) |
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402 | --begin |
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403 | -- if clk'event AND clk='1' then |
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404 | ---- if PresentState=EvalCommand then |
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405 | ---- ADR_Reg <= Start_Reg; |
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406 | ---- elsif PresentState=GetData AND ComState=GetStopBit AND ComTick='1' then |
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407 | ---- ADR_Reg <= ADR_Reg + 1; |
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408 | ---- end if; |
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409 | -- |
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410 | ---- if PresentState=EvalCommand then |
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411 | ---- Word_Count <= Size_Reg; |
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412 | ---- LocalWriteStrobe <= '0'; |
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413 | ---- elsif PresentState=GetData AND ComState=GetStopBit AND ComTick='1' AND Word_Count /= 0 then |
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414 | ---- Word_Count <= Word_Count - 1; |
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415 | ---- LocalWriteStrobe <= '1'; |
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416 | ---- else |
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417 | ---- Word_Count <= Word_Count; |
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418 | ---- LocalWriteStrobe <= '0'; |
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419 | ---- end if; |
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420 | -- |
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421 | -- if hexmode=false then |
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422 | -- WriteStrobe <= LocalWriteStrobe ; -- delay Strobe to ensure that data is valid when applying clk |
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423 | -- -- should further prevent glitches in ICAP clk |
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424 | -- else |
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425 | -- WriteStrobe <= HexWriteStrobe ; |
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426 | -- end if; |
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427 | -- |
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428 | -- end if; -- clk |
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429 | --end process; |
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430 | |
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431 | -- ComLoaderActive <= '0'; |
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432 | --WriteData <= Data_Reg when (hexmode=false) else HexData; |
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433 | ReceivedWordDebug <= Data_Reg when (hexmode=false) else HexData; |
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434 | --ComActive <= '1' when (PresentState=GetData OR PresentState=GetFinish) else '0'; |
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435 | ComActive <= '1' when (et_loadbs=read_word0 OR |
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436 | et_loadbs=read_word1 or |
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437 | et_loadbs=read_word2 or |
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438 | et_loadbs=read_word3 or |
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439 | et_loadbs=end_loadbs ) else '0'; |
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440 | WriteStrobe <= LocalWriteStrobe; |
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441 | --P_OutReg:process(clk) |
---|
442 | --begin |
---|
443 | -- if clk'event AND clk='1' then |
---|
444 | -- if PresentState=GetFinish AND D_Reg=b"0000_0000_1010_1010_1111_1111" then |
---|
445 | -- scan_shift_strobe_from_receiver <= '1'; |
---|
446 | -- if W7(4)='1' then |
---|
447 | -- tx_write_strobe_from_receiver <= '1'; |
---|
448 | -- else |
---|
449 | -- tx_write_strobe_from_receiver <= '0'; |
---|
450 | -- end if; |
---|
451 | -- else |
---|
452 | -- scan_shift_strobe_from_receiver <= '0'; |
---|
453 | -- tx_write_strobe_from_receiver <= '0'; |
---|
454 | -- end if; -- new Package |
---|
455 | -- end if; --clk |
---|
456 | --end process; |
---|
457 | -- |
---|
458 | P_TimeOut:process(clk) |
---|
459 | -- im Moment einmal dafür benutzt rauszufinden, ob ComState 'verhungert' und |
---|
460 | -- damit die ganze Maschine stehen bleibt |
---|
461 | begin |
---|
462 | if clk'event AND clk='1' then |
---|
463 | -- if (PresentState=Idle AND ComState=WaitForStartBit AND RxLocal='0') OR |
---|
464 | if (et_loadbs=Idle) OR |
---|
465 | ComState=GetStopBit then |
---|
466 | -- Init TimeOut wenn neue Eingangs-Sequenz startet |
---|
467 | -- oder wenn wieder ein Byte empfangen wurde |
---|
468 | -- um missglückten Empfangsvorgang abzubrechen |
---|
469 | TimeToSendCounter <= TimeToSendValue; |
---|
470 | TimeToSend <= '0'; |
---|
471 | elsif TimeToSendCounter>0 then |
---|
472 | TimeToSendCounter <= TimeToSendCounter - 1; |
---|
473 | TimeToSend <= '0'; |
---|
474 | else |
---|
475 | TimeToSendCounter <= TimeToSendCounter; |
---|
476 | TimeToSend <= '1'; -- force FSM to go back to idle when inactive |
---|
477 | end if; |
---|
478 | end if; --clk |
---|
479 | end process; |
---|
480 | loadbs_sync:process(clk) |
---|
481 | begin |
---|
482 | if rising_edge(clk) then |
---|
483 | et_loadbs<=next_et_loadbs; |
---|
484 | fifo_reg<=fifo_reg_i; |
---|
485 | sync_ok<=sync_ok_i; |
---|
486 | desync_ok<=desync_ok_i; |
---|
487 | cmd_detected<=cmd_detected_i; |
---|
488 | blink <= blink -1; |
---|
489 | end if; |
---|
490 | end process; |
---|
491 | --================================================================== |
---|
492 | --**afectation des sorties de la MAE LAOD BITSTREAM |
---|
493 | --================================================================== |
---|
494 | next_loadbs:process(et_loadbs,fifo_reg,comstate,comtick,RxLocal, |
---|
495 | cmd_detected,sync_ok,desync_ok,Timetosend,bs_load_start,bs_load_ack) |
---|
496 | begin |
---|
497 | next_et_loadbs<=et_loadbs; |
---|
498 | |
---|
499 | sync_ok_i<=sync_ok; |
---|
500 | desync_ok_i<=desync_ok; |
---|
501 | cmd_detected_i<=cmd_detected; |
---|
502 | bs_load_comp<='0'; |
---|
503 | case et_loadbs is |
---|
504 | when idle => |
---|
505 | |
---|
506 | if ComState=WaitForStartBit AND RxLocal='0' and bs_load_start='1' then |
---|
507 | next_et_loadbs <= check_sync; |
---|
508 | sync_ok_i<='1'; |
---|
509 | end if; |
---|
510 | when check_sync=> |
---|
511 | |
---|
512 | if fifo_reg=sync_reg then |
---|
513 | next_et_loadbs<=write_icap; |
---|
514 | end if; |
---|
515 | if TimeToSend='1' then -- false alerte ? |
---|
516 | next_et_loadbs<=idle; |
---|
517 | end if; |
---|
518 | |
---|
519 | when write_icap => |
---|
520 | |
---|
521 | |
---|
522 | if fifo_reg=desync_word and cmd_detected='1' then |
---|
523 | desync_ok_i<='1'; |
---|
524 | cmd_detected_i<='1'; |
---|
525 | elsif desync_ok='1' then |
---|
526 | desync_ok_i<='1'; |
---|
527 | cmd_detected_i<='1'; |
---|
528 | elsif fifo_reg=desync_cmd then |
---|
529 | cmd_detected_i<='1'; |
---|
530 | desync_ok_i<='0'; |
---|
531 | else |
---|
532 | cmd_detected_i<='0'; |
---|
533 | desync_ok_i<='0'; |
---|
534 | end if; |
---|
535 | next_et_loadbs<=reset_reg; |
---|
536 | when reset_reg=> |
---|
537 | next_et_loadbs<=read_word0; |
---|
538 | when read_word0=> if ComState=GetStopBit AND ComTick='1' then |
---|
539 | |
---|
540 | next_et_loadbs<=read_word1; |
---|
541 | end if; |
---|
542 | if TimeToSend='1' then |
---|
543 | next_et_loadbs<=end_loadbs; |
---|
544 | end if; |
---|
545 | when read_word1=> if ComState=GetStopBit AND ComTick='1' then |
---|
546 | next_et_loadbs<=read_word2; |
---|
547 | else |
---|
548 | if TimeToSend='1' then |
---|
549 | next_et_loadbs<=end_loadbs; |
---|
550 | end if; |
---|
551 | end if; |
---|
552 | when read_word2=> if ComState=GetStopBit AND ComTick='1' then |
---|
553 | next_et_loadbs<=read_word3; |
---|
554 | else |
---|
555 | if TimeToSend='1' then |
---|
556 | next_et_loadbs<=end_loadbs; |
---|
557 | end if; |
---|
558 | end if; |
---|
559 | when read_word3=> if ComState=GetStopBit AND ComTick='1' then |
---|
560 | next_et_loadbs<=write_icap; |
---|
561 | if TimeToSend='1' then |
---|
562 | next_et_loadbs<=end_loadbs; |
---|
563 | end if; |
---|
564 | end if; |
---|
565 | when end_loadbs=> |
---|
566 | if bs_load_ack='1' then |
---|
567 | next_et_loadbs<=Idle; |
---|
568 | end if; |
---|
569 | bs_load_comp<='1'; |
---|
570 | end case; |
---|
571 | |
---|
572 | end process; |
---|
573 | --========================================================== |
---|
574 | --** |
---|
575 | --========================================================== |
---|
576 | val_loadbs:process(et_loadbs,receivedWord,Comstate,ComTick,fifo_reg,blink, |
---|
577 | desync_ok) |
---|
578 | begin |
---|
579 | fifo_reg_i<=fifo_reg; |
---|
580 | localwritestrobe<='0'; |
---|
581 | case et_loadbs is |
---|
582 | when idle => |
---|
583 | ReceiveLED <= '0'; |
---|
584 | when check_sync=> |
---|
585 | ReceiveLED <= '0'; |
---|
586 | if ComState=GetStopBit AND ComTick='1' then |
---|
587 | fifo_reg_i(31 downto 8)<=fifo_reg(23 downto 0); |
---|
588 | fifo_reg_i(7 downto 0)<=Receivedword; |
---|
589 | end if; |
---|
590 | when write_icap=> |
---|
591 | localWritestrobe<='1'; |
---|
592 | bs_load_data<=fifo_reg; |
---|
593 | when reset_reg=> |
---|
594 | fifo_reg_i<=(others=>'0'); --remise à zero du registre d'écriture |
---|
595 | when read_word0=>fifo_reg_i(31 downto 24)<=ReceivedWord; |
---|
596 | ReceiveLED <= '1'; |
---|
597 | when read_word1=>fifo_reg_i(23 downto 16)<=ReceivedWord; |
---|
598 | ReceiveLED <= '1'; |
---|
599 | when read_word2=>fifo_reg_i(15 downto 8)<=ReceivedWord; |
---|
600 | ReceiveLED <= '1'; |
---|
601 | when read_word3=>fifo_reg_i(7 downto 0)<=ReceivedWord; |
---|
602 | ReceiveLED <= '1'; |
---|
603 | when end_loadbs=>fifo_reg_i<=(others=>'1'); |
---|
604 | if desync_ok='0' then |
---|
605 | ReceiveLED <= blink(blink'high); |
---|
606 | else |
---|
607 | ReceiveLED <= '0'; -- receive process was OK |
---|
608 | end if; |
---|
609 | end case; |
---|
610 | |
---|
611 | |
---|
612 | |
---|
613 | end process; |
---|
614 | ---------------------------------------------------------------------------------- |
---|
615 | -- the Tx Send-Process |
---|
616 | |
---|
617 | --tx_write_strobe <= tx_write_strobe_from_receiver OR (tast_trigger AND (NOT tast_trigger_delay)); |
---|
618 | |
---|
619 | --P_com_en2:process(clk, com_en_counter) |
---|
620 | --begin |
---|
621 | -- |
---|
622 | -- if clk'event AND clk='1' then |
---|
623 | -- |
---|
624 | -- |
---|
625 | -- if (tx_write_strobe='1') OR (tx_write_strobe='0' AND com_en_counter = 0) then |
---|
626 | -- com_en_counter <= 433; --433 @ 50 MHz ###### |
---|
627 | -- else |
---|
628 | -- com_en_counter <= com_en_counter - 1; |
---|
629 | -- end if; |
---|
630 | -- |
---|
631 | -- end if; |
---|
632 | -- |
---|
633 | -- if com_en_counter = 0 then |
---|
634 | -- com_en <= '1'; |
---|
635 | -- else |
---|
636 | -- com_en <= '0'; |
---|
637 | -- end if; |
---|
638 | --end process; |
---|
639 | -- |
---|
640 | --P_SendCounter:process(clk, com_en) |
---|
641 | --begin |
---|
642 | -- if clk'event AND clk='1' then |
---|
643 | -- if tx_write_strobe='1' then -- send_to_com_strobe 10 Hz so we send new values 10 times a second |
---|
644 | -- state_counter <= 80; |
---|
645 | -- elsif state_counter>0 then |
---|
646 | -- if com_en_counter=0 then |
---|
647 | -- state_counter <= state_counter - 1 ; |
---|
648 | -- end if; |
---|
649 | -- else |
---|
650 | -- state_counter <= state_counter ; |
---|
651 | -- end if; |
---|
652 | -- end if; -- clk |
---|
653 | --end process; |
---|
654 | |
---|
655 | -- P_SendMux:process(state_counter, TxOut, clk) |
---|
656 | -- begin |
---|
657 | -- if clk'event AND clk='1' then |
---|
658 | -- case state_counter is |
---|
659 | -- when 80 => TxOut <= '0'; -- send start bit |
---|
660 | -- when 79 => TxOut <= W0(0); |
---|
661 | -- when 78 => TxOut <= W0(1); |
---|
662 | -- when 77 => TxOut <= W0(2); |
---|
663 | -- when 76 => TxOut <= W0(3); |
---|
664 | -- when 75 => TxOut <= W0(4); |
---|
665 | -- when 74 => TxOut <= W0(5); |
---|
666 | -- when 73 => TxOut <= W0(6); |
---|
667 | -- when 72 => TxOut <= W0(7); |
---|
668 | -- when 71 => TxOut <= '1'; -- send stop bit |
---|
669 | -- |
---|
670 | -- when 70 => TxOut <= '0'; -- send start bit |
---|
671 | -- when 69 => TxOut <= W1(0); |
---|
672 | -- when 68 => TxOut <= W1(1); |
---|
673 | -- when 67 => TxOut <= W1(2); |
---|
674 | -- when 66 => TxOut <= W1(3); |
---|
675 | -- when 65 => TxOut <= W1(4); |
---|
676 | -- when 64 => TxOut <= W1(5); |
---|
677 | -- when 63 => TxOut <= W1(6); |
---|
678 | -- when 62 => TxOut <= W1(7); |
---|
679 | -- when 61 => TxOut <= '1'; -- send stop bit |
---|
680 | -- |
---|
681 | -- when 60 => TxOut <= '0'; -- send start bit |
---|
682 | -- when 59 => TxOut <= W2(0); |
---|
683 | -- when 58 => TxOut <= W2(1); |
---|
684 | -- when 57 => TxOut <= W2(2); |
---|
685 | -- when 56 => TxOut <= W2(3); |
---|
686 | -- when 55 => TxOut <= W2(4); |
---|
687 | -- when 54 => TxOut <= W2(5); |
---|
688 | -- when 53 => TxOut <= W2(6); |
---|
689 | -- when 52 => TxOut <= W2(7); |
---|
690 | -- when 51 => TxOut <= '1'; -- send stop bit |
---|
691 | -- |
---|
692 | -- when 50 => TxOut <= '0'; -- send start bit |
---|
693 | -- when 49 => TxOut <= W3(0); |
---|
694 | -- when 48 => TxOut <= W3(1); |
---|
695 | -- when 47 => TxOut <= W3(2); |
---|
696 | -- when 46 => TxOut <= W3(3); |
---|
697 | -- when 45 => TxOut <= W3(4); |
---|
698 | -- when 44 => TxOut <= W3(5); |
---|
699 | -- when 43 => TxOut <= W3(6); |
---|
700 | -- when 42 => TxOut <= W3(7); |
---|
701 | -- when 41 => TxOut <= '1'; -- send stop bit |
---|
702 | -- |
---|
703 | -- when 40 => TxOut <= '0'; -- send start bit |
---|
704 | -- when 39 => TxOut <= W4(0); |
---|
705 | -- when 38 => TxOut <= W4(1); |
---|
706 | -- when 37 => TxOut <= W4(2); |
---|
707 | -- when 36 => TxOut <= W4(3); |
---|
708 | -- when 35 => TxOut <= W4(4); |
---|
709 | -- when 34 => TxOut <= W4(5); |
---|
710 | -- when 33 => TxOut <= W4(6); |
---|
711 | -- when 32 => TxOut <= W4(7); |
---|
712 | -- when 31 => TxOut <= '1'; -- send stop bit |
---|
713 | -- |
---|
714 | -- when 30 => TxOut <= '0'; -- send start bit |
---|
715 | -- when 29 => TxOut <= W5(0); |
---|
716 | -- when 28 => TxOut <= W5(1); |
---|
717 | -- when 27 => TxOut <= W5(2); |
---|
718 | -- when 26 => TxOut <= W5(3); |
---|
719 | -- when 25 => TxOut <= W5(4); |
---|
720 | -- when 24 => TxOut <= W5(5); |
---|
721 | -- when 23 => TxOut <= W5(6); |
---|
722 | -- when 22 => TxOut <= W5(7); |
---|
723 | -- when 21 => TxOut <= '1'; -- send stop bit |
---|
724 | -- |
---|
725 | -- when 20 => TxOut <= '0'; -- send start bit |
---|
726 | -- when 19 => TxOut <= W6(0); |
---|
727 | -- when 18 => TxOut <= W6(1); |
---|
728 | -- when 17 => TxOut <= W6(2); |
---|
729 | -- when 16 => TxOut <= W6(3); |
---|
730 | -- when 15 => TxOut <= W6(4); |
---|
731 | -- when 14 => TxOut <= W6(5); |
---|
732 | -- when 13 => TxOut <= W6(6); |
---|
733 | -- when 12 => TxOut <= W6(7); |
---|
734 | -- when 11 => TxOut <= '1'; -- send stop bit |
---|
735 | -- |
---|
736 | -- when 10 => TxOut <= '0'; -- send start bit |
---|
737 | -- when 9 => TxOut <= W7(0); |
---|
738 | -- when 8 => TxOut <= '1'; -- finally the command ID sequence |
---|
739 | -- when 7 => TxOut <= '1'; |
---|
740 | -- when 6 => TxOut <= '0'; |
---|
741 | -- when 5 => TxOut <= swap_mode; |
---|
742 | -- when 4 => TxOut <= '0'; |
---|
743 | -- when 3 => TxOut <= '1'; |
---|
744 | -- when 2 => TxOut <= '1'; |
---|
745 | -- |
---|
746 | -- when others => TxOut <= '1'; -- send stop bit |
---|
747 | -- end case; |
---|
748 | -- end if; -- clk; |
---|
749 | -- end process; |
---|
750 | -- |
---|
751 | TxOut<=Rx; |
---|
752 | RxErr<=Stop_err; |
---|
753 | end architecture; |
---|
754 | |
---|
755 | |
---|
756 | |
---|
757 | |
---|
758 | |
---|