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load_instr.vhd.bak @ 142

Last change on this file since 142 was 142, checked in by rolagamo, 10 years ago

File size: 10.5 KB

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1	----------------------------------------------------------------------------------
2	-- Company:
3	-- Engineer: GAMOM NGOUNOU
4	--
5	-- Create Date: 04:57:14 07/15/2012
6	-- Design Name:
7	-- Module Name: load_instr - Behavioral
8	-- Project Name: MPI CORE
9	-- Target Devices:
10	-- Tool versions:
11	-- Description: Ce module permet de charger une instruction dans le FIFO 1
12	--
13	-- Dependencies:
14	--
15	-- Revision:
16	-- Revision 0.01 - File Created
17	-- Additional Comments:
18	--
19	----------------------------------------------------------------------------------
20	library IEEE;
21	library NocLib;
22	use IEEE.STD_LOGIC_1164.ALL;
23
24	-- Uncomment the following library declaration if using
25	-- arithmetic functions with Signed or Unsigned values
26	use IEEE.NUMERIC_STD.ALL;
27	use NocLib.CoreTypes.all;
28	-- Uncomment the following library declaration if instantiating
29	-- any Xilinx primitives in this code.
30	--library UNISIM;
31	--use UNISIM.VComponents.all;
32
33	entity load_instr is
34	Port ( Instruction : in STD_LOGIC_VECTOR (Word-1 downto 0);
35	Instruction_en : in STD_LOGIC;
36
37	clk : in STD_LOGIC;
38	reset : in STD_LOGIC;
39	dma_rd_grant : in STD_LOGIC;
40	dma_rd_request : out STD_LOGIC:='0';
41	instruction_ack : out STD_LOGIC:='0';
42	fifo_din : out STD_LOGIC_VECTOR (Word-1 downto 0);
43	fifo_wr :out std_logic:='0';
44	copying :out std_logic:='0';
45	fifo_full : in STD_LOGIC;
46	ram_address_rd : buffer STD_LOGIC_VECTOR (ADRLEN-1 downto 0);
47	ram_data : in STD_LOGIC_VECTOR (WORD-1 downto 0);
48	Ram_rd_en : out std_logic);
49	end load_instr;
50
51	architecture Behavioral of load_instr is
52	--déclaration des types manipulés
53	type typ_loadinst is (init,setadr,readptr,getbus,readmem,freebus,st_timeout);
54	--déclaration des signaux
55	signal Ram_address_i:STD_LOGIC_VECTOR (ADRLEN-1 downto 0):=(others=>'0');
56	--signal ptr, ptr_i:STD_LOGIC_VECTOR (ADRLEN-1 downto 0):=(others=>'0'); --pointeur vers l'instruction en RAM
57	signal Base_Adr , Base_Adr_i : STD_LOGIC_VECTOR (ADRLEN-1 downto 0):=(others=>'0');
58	signal adr_ptr : natural range 0 to 65536:=0;
59	signal Base_AdrSet : std_logic:='0' ; --indique l'adresse de base des instructions positionée
60	signal fifo_din_i,fifo_din_q:std_logic_vector(WORD-1 downto 0):=(others=>'-');
61	signal iLen,iLen_i : natural range 0 to 15:=0; --longueur de l'instruction à copier dans le Fifo
62	signal fifo_wr_i,fifo_wr_q :std_logic:='0';
63	signal rd_ok:std_logic:='0';
64	signal base_adrset_i : std_logic:='0';
65	signal ptr,ptr_i : std_logic_vector(ADRLEN-1 downto 0):=(others=>'0');
66	signal instruction_ack_i,instruction_ack_q :std_logic:='0';
67	signal Dma_rd_request_i,Dma_rd_request_q :std_logic:='0';
68	signal count,count_i : natural range 0 to 31:=0; --permet de faie évoluer la sous-MAE
69	signal etloadinst,next_loadinst : typ_loadinst;
70	signal timeout, timeout_i: natural range 0 to 255;
71	begin
72	SYNC_PROC: process (clk)
73	begin
74	if rising_edge(clk) then
75	if (reset = '1') or instruction_en='0' then
76	etloadinst <= init;
77	Base_adrSet<= '0';
78	dma_rd_request_q<='0';
79	instruction_ack_q<='0';
80	count<=0;
81	Ilen<=0;
82	fifo_din_q<=(others=>'0');
83	else
84	etloadinst <= next_loadinst;
85	fifo_din_q <= fifo_din_i;
86	Base_Adr<=Base_Adr_i;
87	Base_AdrSet<=Base_adrSet_i;
88	ptr<=ptr_i;
89	fifo_wr_q<=fifo_wr_i;
90	ram_address_rd<=ram_address_i;
91	adr_ptr<=to_integer(to_01(unsigned(ram_address_i)));
92	dma_rd_request_q<=dma_rd_request_i;
93	instruction_ack_q<=instruction_ack_i;
94	count<=count_i;
95	Ilen<=Ilen_i;
96	Timeout<=timeout_i;
97
98
99	end if;
100	end if;
101	end process;
102	--*****************************************
103	-- assign other outputs to internal signals
104	fifo_wr<=fifo_wr_q;
105	instruction_ack<=instruction_ack_q;
106	dma_rd_request<=dma_rd_request_q;
107	--*************************************************************************
108	OUTPUT_DECODE: process (etloadinst,fifo_din_q,Count_i,Ram_data,Dma_rd_grant,
109	Base_AdrSet,Dma_rd_request_q,instruction_ack_q,rd_ok)
110	variable Adr_inst1,adr_inst2 : natural;
111	begin
112	fifo_din_i <= fifo_din_q;
113	fifo_din<=fifo_din_q;
114	dma_rd_request_i<=dma_rd_request_q;
115	instruction_ack_i<=instruction_ack_q;
116
117	--Base_AdrSet_i<=Base_adrSet;
118	case etloadinst is
119	when init =>
120	Dma_rd_request_i<='0';
121	--fifo_wr<='0';
122	copying<='0';
123	Ram_rd_en<='0';
124	Instruction_ack_i<='0';
125	fifo_din_i<=(others=>'-');
126	--Base_AdrSet_i<='0';
127
128	when SetAdr =>
129	Dma_rd_request_i<='0';
130	Instruction_ack_i<='0';
131	--fifo_wr<='0';
132	copying<='0';
133	Ram_rd_en<='0';
134
135	fifo_din_i<=(others=>'-');
136	--Base_AdrSet_i<='1';
137
138	when getbus =>
139	--fifo_wr<='0';
140	copying<='1';
141	Ram_rd_en<='0';
142	Dma_rd_request_i<='1';
143	Instruction_ack_i<='0';
144	fifo_din_i<=(others=>'-');
145	-- Base_AdrSet_i<='1';
146	when readptr =>
147	--fifo_wr<='0';
148
149	copying<='1';
150	Ram_rd_en<=rd_ok;
151	Dma_rd_request_i<='1';
152	Instruction_ack_i<='0';
153	fifo_din_i<=(others=>'-');
154	--Base_AdrSet_i<='1';
155	when readmem =>
156	Dma_rd_request_i<='1';
157	copying<='1';
158	Ram_rd_en<=rd_ok;
159	--fifo_wr<=fifo_wr_i;
160	fifo_din_i<=Ram_data;
161	fifo_din<=Ram_data;
162	--Base_AdrSet_i<='1';
163	Instruction_ack_i<='0';
164
165	when freebus =>
166	Dma_rd_request_i<='0';
167	--fifo_wr<='0';
168	copying<='0';
169	Ram_rd_en<='0';
170	Instruction_ack_i<='1';
171	fifo_din_i<=(others=>'-');
172	--Base_AdrSet_i<='1';
173	when st_timeout =>
174	Dma_rd_request_i<='0';
175	-- fifo_wr<='0';
176	copying<='0';
177	Ram_rd_en<='0';
178	Instruction_ack_i<='0';
179	fifo_din_i<=(others=>'-');
180	--Base_AdrSet_i<='1';
181	end case;
182	end process;
183
184	NEXT_STATE_DECODE: process (etloadinst, Ram_address_rd,Base_AdrSet,Adr_Ptr,Ram_data,Instruction,instruction_en,
185	fifo_full,dma_rd_grant,count,Ilen,Base_adr,timeout,fifo_wr_q)
186
187	--variable ptr : std_logic_vector(ADRLEN-1 downto 0);
188
189	variable Base_AD,ADRtmp,iptr : natural range 0 to 65535;
190	begin
191	--declare default state for next_state to avoid latches
192	next_loadinst <= etloadinst; --default is to stay in current state
193	Ram_address_i<=Ram_address_rd;
194	--Base_Adr_i<=Base_adr;
195	ptr_i<=ptr;
196	count_i<=count;
197	Ilen_i<=Ilen;
198	AdrTmp:=Adr_ptr;
199	timeout_i<=timeout;
200	rd_ok<='0';
201	fifo_wr_i<=fifo_wr_q;
202	--below is a simple example
203	case (etloadinst) is
204	when init => if base_adrset='1' and Instruction_en='1' then
205	Ilen_i<=to_integer(unsigned(Instruction(3 downto 0)));--initialisation de longueur
206	next_loadinst<=getbus;
207	--elsif Instruction_en='1' then
208	-- next_loadinst<=Setadr;
209	--Base_Adr_i<=X"0000";
210	else
211	next_loadinst<=init;
212	--Base_Adr_i<=X"0000";
213	Ilen_i<=0;
214	end if;
215	fifo_wr_i<='0';
216	count_i<=0;
217
218	--
219	When Setadr => if Base_adrSet='0' then
220	-- Base_Adr_i<=std_logic_vector(to_unsigned(Core_upper_adr,8)) & X"00"; --récupération des bits de poids forts de l'instruction
221	--
222	end if;
223	next_loadinst<=init;
224	Ram_address_i<=(others=>'0');
225	count_i<=0;
226	when getbus =>
227	BASE_AD:=to_integer(to_01(unsigned(base_adr)));
228	if dma_rd_grant = '1' then
229	next_loadinst <= readptr;
230
231	-- prépare la prochaine lecture
232
233	else
234
235	end if;
236	Ram_address_i<=(others=>'0');
237	count_i<=0;
238	When readptr =>
239	--s'assurer que le bus est disponible
240
241	if count=0 then
242
243	Ram_address_i<=std_logic_vector(to_unsigned(BASE_AD+2,16));
244	if dma_rd_grant='1' then
245	count_i <=count+1;
246	end if;
247	elsif count=1 then-- attend que la donnée soit positionnée
248	if dma_rd_grant = '1' then
249	count_i <=count+1;
250	rd_ok<='1';
251
252	end if;
253
254	elsif count=2 then
255	if dma_rd_grant = '1' then
256	count_i <=count+1;
257	ptr_i(Word-1 downto 0)<=Ram_data;
258	rd_ok<='1';
259	else
260	count_i<=0;
261	end if;
262	Ram_address_i<=std_logic_vector(to_unsigned(BASE_AD+3,16));
263
264	elsif count=3 then
265	Ram_address_i<=std_logic_vector(to_unsigned(BASE_AD+3,16));
266	if dma_rd_grant = '1' then
267	count_i <=count+1;
268	rd_ok<='1';
269	ptr_i(Word-1 downto 0)<=Ram_data;
270	end if;
271
272	elsif count=4 then
273	if dma_rd_grant = '1' then
274	ptr_i(15 downto 8)<=Ram_data;
275	count_i<=0;
276	timeout_i<=0;
277	next_loadinst <= readmem;
278	else
279	count_i<=3;
280	end if;
281	report "Readptr " & image(ptr);
282	else
283
284	end if;
285
286	if dma_rd_grant = '0' then
287	assert true report "Mauvaise lecture" severity failure;
288	timeout_i<=timeout+1;
289	end if;
290	when readmem =>
291	if fifo_full='0' then
292	if ilen >0 then
293	if count=0 then
294	iptr:=to_integer(to_01(unsigned(ptr)));
295	AdrTmp:=iptr;
296	if dma_rd_grant = '1' then
297	count_i <=count+1;
298	fifo_wr_i<='0';
299	end if;
300	elsif count=1 then
301	if dma_rd_grant = '1' then
302	count_i <=count+1;
303	fifo_wr_i<='0';
304	rd_ok<='0';
305	end if;
306	elsif count=2 then
307	if dma_rd_grant = '1' then
308	count_i <=count+1;
309	fifo_wr_i<='0';
310	rd_ok<='1';
311	else
312	count_i<=1;
313	end if;
314	elsif count=3 then
315	count_i <=count+1;
316	AdrTmp:=Adr_Ptr+1;
317	elsif count=4 then
318	fifo_wr_i<='1'; --écriture de la donnée dans le fifo
319	Ilen_i<=Ilen-1;
320	fifo_wr_i<='0';
321	count_i<=1;
322	end if;
323	else --Ilen=0 ?
324	fifo_wr_i<='0';
325	next_loadinst<=freebus;
326	end if;
327	end if;
328
329	Ram_address_i<=STD_LOGIC_VECTOR(to_unsigned(AdrTmp,16));
330	if dma_rd_grant = '0' or Fifo_full='1' then
331	timeout_i<=timeout+1;
332	fifo_wr_i<='0';
333	Count_i<=1; --recommencer les cycles d'attente de la donnée
334	if timeout=200 then
335	next_loadinst<=st_timeout;
336	end if;
337	end if;
338
339	when freebus =>
340	fifo_wr_i<='0';
341	count_i<=0;
342	Ram_address_i<=(others=>'0');
343	if instruction_en='0' then
344	next_loadinst <= init;
345	end if;
346	when st_timeout =>
347	fifo_wr_i<='0';
348	Ram_address_i<=(others=>'0');
349	next_loadinst<=init;
350	report "Copie D'instruction *** RAM/Fifo a été indisponible pour trop longtemps !!!";
351	count_i<=0;
352	end case;
353	end process;
354	base_ad_proc:process(reset)
355	begin
356
357	if reset = '1' then
358	Base_adrSet_i<='0';
359	Base_Adr_i<=x"0000";
360	else
361	Base_adrSet_i<='1';
362	Base_Adr_i<=std_logic_vector(to_unsigned(Core_upper_adr,8)) & X"00"; --récupération des bits de poids forts de l'instruction
363	--
364
365	end if;
366
367
368	end process;
369	end Behavioral;
370

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