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load_instr.vhd @ 154

Last change on this file since 154 was 142, checked in by rolagamo, 10 years ago

File size: 10.6 KB

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1	----------------------------------------------------------------------------------
2	-- Company:
3	-- Engineer: GAMOM NGOUNOU
4	--
5	-- Create Date: 04:57:14 07/15/2012
6	-- Design Name:
7	-- Module Name: load_instr - Behavioral
8	-- Project Name: MPI CORE
9	-- Target Devices:
10	-- Tool versions:
11	-- Description: Ce module permet de charger une instruction dans le FIFO 1
12	--
13	-- Dependencies:
14	--
15	-- Revision:
16	-- Revision 0.01 - File Created
17	-- Additional Comments:
18	--
19	----------------------------------------------------------------------------------
20	library IEEE;
21	library NocLib;
22	use IEEE.STD_LOGIC_1164.ALL;
23
24	-- Uncomment the following library declaration if using
25	-- arithmetic functions with Signed or Unsigned values
26	use IEEE.NUMERIC_STD.ALL;
27	use NocLib.CoreTypes.all;
28	-- Uncomment the following library declaration if instantiating
29	-- any Xilinx primitives in this code.
30	--library UNISIM;
31	--use UNISIM.VComponents.all;
32
33	entity load_instr is
34	Port ( Instruction : in STD_LOGIC_VECTOR (Word-1 downto 0);
35	Instruction_en : in STD_LOGIC;
36
37	clk : in STD_LOGIC;
38	reset : in STD_LOGIC;
39	dma_rd_grant : in STD_LOGIC;
40	dma_rd_request : out STD_LOGIC:='0';
41	instruction_ack : out STD_LOGIC:='0';
42	fifo_din : out STD_LOGIC_VECTOR (Word-1 downto 0);
43	fifo_wr :out std_logic:='0';
44	copying :out std_logic:='0';
45	fifo_full : in STD_LOGIC;
46	ram_address_rd : out STD_LOGIC_VECTOR (ADRLEN-1 downto 0);
47	ram_data : in STD_LOGIC_VECTOR (WORD-1 downto 0);
48	Ram_rd_en : out std_logic);
49	end load_instr;
50
51	architecture Behavioral of load_instr is
52	--déclaration des types manipulés
53	type typ_loadinst is (init,setadr,readptr,getbus,readmem,freebus,st_timeout);
54	--déclaration des signaux
55	signal Ram_address_i,Ram_address_q:STD_LOGIC_VECTOR (ADRLEN-1 downto 0):=(others=>'0');
56	--signal ptr, ptr_i:STD_LOGIC_VECTOR (ADRLEN-1 downto 0):=(others=>'0'); --pointeur vers l'instruction en RAM
57	signal Base_Adr , Base_Adr_i : STD_LOGIC_VECTOR (ADRLEN-1 downto 0):=(others=>'0');
58	signal adr_ptr : natural range 0 to 65536:=0;
59	signal Base_AdrSet : std_logic:='0' ; --indique l'adresse de base des instructions positionée
60	signal fifo_din_i,fifo_din_q:std_logic_vector(WORD-1 downto 0):=(others=>'-');
61	signal iLen,iLen_i : natural range 0 to 15:=0; --longueur de l'instruction à copier dans le Fifo
62	signal fifo_wr_i,fifo_wr_q :std_logic:='0';
63	signal rd_ok:std_logic:='0';
64	signal base_adrset_i : std_logic:='0';
65	signal ptr,ptr_i : std_logic_vector(ADRLEN-1 downto 0):=(others=>'0');
66	signal instruction_ack_i,instruction_ack_q :std_logic:='0';
67	signal Dma_rd_request_i,Dma_rd_request_q :std_logic:='0';
68	signal count,count_i : natural range 0 to 31:=0; --permet de faie évoluer la sous-MAE
69	signal etloadinst,next_loadinst : typ_loadinst;
70	signal timeout, timeout_i: natural range 0 to 255;
71	begin
72	SYNC_PROC: process (clk)
73	begin
74	if rising_edge(clk) then
75	if reset = '1' then
76	etloadinst <= init;
77	Base_adrSet<= '0';
78	dma_rd_request_q<='0';
79	instruction_ack_q<='0';
80	count<=0;
81	Ilen<=0;
82	Base_adr<=x"0000";
83	fifo_din_q<=(others=>'0');
84	else
85	etloadinst <= next_loadinst;
86	fifo_din_q <= fifo_din_i;
87	Base_Adr<=Base_Adr_i;
88	Base_AdrSet<=Base_adrSet_i;
89	ptr<=ptr_i;
90	fifo_wr_q<=fifo_wr_i;
91	ram_address_q<=ram_address_i;
92	adr_ptr<=to_integer(to_01(unsigned(ram_address_i)));
93	dma_rd_request_q<=dma_rd_request_i;
94	instruction_ack_q<=instruction_ack_i;
95	count<=count_i;
96	Ilen<=Ilen_i;
97	Timeout<=timeout_i;
98
99
100	end if;
101	end if;
102	end process;
103	--*****************************************
104	-- assign other outputs to internal signals
105	fifo_wr<=fifo_wr_q;
106	instruction_ack<=instruction_ack_q;
107	dma_rd_request<=dma_rd_request_q;
108	Ram_address_rd<=Ram_address_q;
109	--*************************************************************************
110	OUTPUT_DECODE: process (etloadinst,fifo_din_q,Count_i,Ram_data,Dma_rd_grant,
111	Base_AdrSet,Dma_rd_request_q,instruction_ack_q,rd_ok)
112	variable Adr_inst1,adr_inst2 : natural;
113	begin
114	fifo_din_i <= fifo_din_q;
115	fifo_din<=fifo_din_q;
116	dma_rd_request_i<=dma_rd_request_q;
117	instruction_ack_i<=instruction_ack_q;
118
119	--Base_AdrSet_i<=Base_adrSet;
120	case etloadinst is
121	when init =>
122	Dma_rd_request_i<='0';
123	--fifo_wr<='0';
124	copying<='0';
125	Ram_rd_en<='0';
126	Instruction_ack_i<='0';
127	fifo_din_i<=(others=>'-');
128	--Base_AdrSet_i<='0';
129
130	when SetAdr =>
131	Dma_rd_request_i<='0';
132	Instruction_ack_i<='0';
133	--fifo_wr<='0';
134	copying<='0';
135	Ram_rd_en<='0';
136
137	fifo_din_i<=(others=>'-');
138	--Base_AdrSet_i<='1';
139
140	when getbus =>
141	--fifo_wr<='0';
142	copying<='1';
143	Ram_rd_en<='0';
144	Dma_rd_request_i<='1';
145	Instruction_ack_i<='0';
146	fifo_din_i<=(others=>'-');
147	-- Base_AdrSet_i<='1';
148	when readptr =>
149	--fifo_wr<='0';
150
151	copying<='1';
152	Ram_rd_en<=rd_ok;
153	Dma_rd_request_i<='1';
154	Instruction_ack_i<='0';
155	fifo_din_i<=(others=>'-');
156	--Base_AdrSet_i<='1';
157	when readmem =>
158	Dma_rd_request_i<='1';
159	copying<='1';
160	Ram_rd_en<=rd_ok;
161	--fifo_wr<=fifo_wr_i;
162	fifo_din_i<=Ram_data;
163	fifo_din<=Ram_data;
164	--Base_AdrSet_i<='1';
165	Instruction_ack_i<='0';
166
167	when freebus =>
168	Dma_rd_request_i<='0';
169	--fifo_wr<='0';
170	copying<='0';
171	Ram_rd_en<='0';
172	Instruction_ack_i<='1';
173	fifo_din_i<=(others=>'-');
174	--Base_AdrSet_i<='1';
175	when st_timeout =>
176	Dma_rd_request_i<='0';
177	-- fifo_wr<='0';
178	copying<='0';
179	Ram_rd_en<='0';
180	Instruction_ack_i<='0';
181	fifo_din_i<=(others=>'-');
182	--Base_AdrSet_i<='1';
183	end case;
184	end process;
185
186	NEXT_STATE_DECODE: process (etloadinst, Ram_address_q,Base_AdrSet,Adr_Ptr,Ram_data,Instruction,instruction_en,
187	fifo_full,dma_rd_grant,count,Ilen,Base_adr,ptr,timeout,fifo_wr_q)
188
189	--variable ptr : std_logic_vector(ADRLEN-1 downto 0);
190
191	variable Base_AD,ADRtmp,iptr : natural range 0 to 65535;
192	begin
193	--declare default state for next_state to avoid latches
194	next_loadinst <= etloadinst; --default is to stay in current state
195	Ram_address_i<=Ram_address_q;
196	--Base_Adr_i<=Base_adr;
197	ptr_i<=ptr;
198	BASE_AD:=to_integer(to_01(unsigned(base_adr))); --pour éviter le latch
199	count_i<=count;
200	Ilen_i<=Ilen;
201	AdrTmp:=Adr_ptr;
202	timeout_i<=timeout;
203	rd_ok<='0';
204	fifo_wr_i<=fifo_wr_q;
205	--below is a simple example
206	case (etloadinst) is
207	when init => if base_adrset='1' and Instruction_en='1' then
208	Ilen_i<=to_integer(unsigned(Instruction(3 downto 0)));--initialisation de longueur
209	next_loadinst<=getbus;
210	--elsif Instruction_en='1' then
211	-- next_loadinst<=Setadr;
212	--Base_Adr_i<=X"0000";
213	else
214	next_loadinst<=init;
215	--Base_Adr_i<=X"0000";
216	Ilen_i<=0;
217	end if;
218	fifo_wr_i<='0';
219	count_i<=0;
220
221	--
222	When Setadr => if Base_adrSet='0' then
223	-- Base_Adr_i<=std_logic_vector(to_unsigned(Core_upper_adr,8)) & X"00"; --récupération des bits de poids forts de l'instruction
224	--
225	end if;
226	next_loadinst<=init;
227	Ram_address_i<=(others=>'0');
228	count_i<=0;
229	when getbus =>
230	BASE_AD:=to_integer(to_01(unsigned(base_adr)));
231	if dma_rd_grant = '1' then
232	next_loadinst <= readptr;
233
234	-- prépare la prochaine lecture
235
236	else
237
238	end if;
239	Ram_address_i<=(others=>'0');
240	count_i<=0;
241	When readptr =>
242	--s'assurer que le bus est disponible
243
244	if count=0 then
245
246	Ram_address_i<=std_logic_vector(to_unsigned(BASE_AD+2,16));
247	if dma_rd_grant='1' then
248	count_i <=count+1;
249	end if;
250	elsif count=1 then-- attend que la donnée soit positionnée
251	if dma_rd_grant = '1' then
252	count_i <=count+1;
253	rd_ok<='1';
254
255	end if;
256
257	elsif count=2 then
258	if dma_rd_grant = '1' then
259	count_i <=count+1;
260	ptr_i(Word-1 downto 0)<=Ram_data;
261	rd_ok<='1';
262	else
263	count_i<=0;
264	end if;
265	Ram_address_i<=std_logic_vector(to_unsigned(BASE_AD+3,16));
266
267	elsif count=3 then
268	Ram_address_i<=std_logic_vector(to_unsigned(BASE_AD+3,16));
269	if dma_rd_grant = '1' then
270	count_i <=count+1;
271	rd_ok<='1';
272	ptr_i(Word-1 downto 0)<=Ram_data;
273	end if;
274
275	elsif count=4 then
276	if dma_rd_grant = '1' then
277	ptr_i(15 downto 8)<=Ram_data;
278	count_i<=0;
279	timeout_i<=0;
280	next_loadinst <= readmem;
281	else
282	count_i<=3;
283	end if;
284	report "Readptr " & image(ptr);
285	else
286
287	end if;
288
289	if dma_rd_grant = '0' then
290	assert true report "Mauvaise lecture" severity failure;
291	timeout_i<=timeout+1;
292	end if;
293	when readmem =>
294	if fifo_full='0' then
295	if ilen >0 then
296	if count=0 then
297	iptr:=to_integer(to_01(unsigned(ptr)));
298	AdrTmp:=iptr;
299	if dma_rd_grant = '1' then
300	count_i <=count+1;
301	fifo_wr_i<='0';
302	end if;
303	elsif count=1 then
304	if dma_rd_grant = '1' then
305	count_i <=count+1;
306	fifo_wr_i<='0';
307	rd_ok<='0';
308	end if;
309	elsif count=2 then
310	if dma_rd_grant = '1' then
311	count_i <=count+1;
312	fifo_wr_i<='0';
313	rd_ok<='1';
314	else
315	count_i<=1;
316	end if;
317	elsif count=3 then
318	count_i <=count+1;
319	AdrTmp:=Adr_Ptr+1;
320	elsif count=4 then
321	fifo_wr_i<='1'; --écriture de la donnée dans le fifo
322	Ilen_i<=Ilen-1;
323	count_i<=1;
324	end if;
325	else --Ilen=0 ?
326	fifo_wr_i<='0';
327	next_loadinst<=freebus;
328	end if;
329	end if;
330
331	Ram_address_i<=STD_LOGIC_VECTOR(to_unsigned(AdrTmp,16));
332	if dma_rd_grant = '0' or Fifo_full='1' then
333	timeout_i<=timeout+1;
334	fifo_wr_i<='0';
335	Count_i<=1; --recommencer les cycles d'attente de la donnée
336	if timeout=200 then
337	next_loadinst<=st_timeout;
338	end if;
339	end if;
340
341	when freebus =>
342	fifo_wr_i<='0';
343	count_i<=0;
344	Ram_address_i<=(others=>'0');
345	if instruction_en='0' then
346	next_loadinst <= init;
347	end if;
348	when st_timeout =>
349	fifo_wr_i<='0';
350	Ram_address_i<=(others=>'0');
351	next_loadinst<=init;
352	report "Copie D'instruction *** RAM/Fifo a été indisponible pour trop longtemps !!!";
353	count_i<=0;
354	end case;
355	end process;
356	base_ad_proc:process(reset)
357	begin
358
359	if reset = '1' then
360	Base_adrSet_i<='0';
361	Base_Adr_i<=x"0000";
362	else
363	Base_adrSet_i<='1';
364	Base_Adr_i<=std_logic_vector(to_unsigned(Core_upper_adr,8)) & X"00"; --récupération des bits de poids forts de l'instruction
365	--
366
367	end if;
368
369
370	end process;
371	end Behavioral;
372

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source: PROJECT_CORE_MPI/MPI_HCL/BRANCHES/v2.1/CORE_MPI/load_instr.vhd @ 154

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