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mem2fifo.vhd

Last change on this file was 142, checked in by rolagamo, 10 years ago

File size: 5.9 KB

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1	----------------------------------------------------------------------------------
2	-- Company:
3	-- Engineer:
4	--
5	-- Create Date: 18:01:21 28/06/2014
6	-- Design Name:
7	-- Module Name: Mem2fifo - Behavioral
8	-- Project Name:
9	-- Target Devices:
10	-- Tool versions:
11	-- Description:
12	--
13	-- Dependencies:
14	--
15	-- Revision:
16	-- Revision 0.01 - File Created
17	-- Additional Comments:
18	--
19	----------------------------------------------------------------------------------
20	library IEEE;
21	use IEEE.STD_LOGIC_1164.ALL;
22	USE ieee.numeric_std.ALL;
23	Library NoCLib;
24	use NoCLib.CoreTypes.all;
25	-- Uncomment the following library declaration if using
26	-- arithmetic functions with Signed or Unsigned values
27	--use IEEE.NUMERIC_STD.ALL;
28
29	-- Uncomment the following library declaration if instantiating
30	-- any Xilinx primitives in this code.
31	--library UNISIM;
32	--use UNISIM.VComponents.all;
33
34	entity mem2fifo_a is --copy from memory to fifo
35	port (
36	clk,reset : in std_logic;
37	copy_mode : in std_logic; --Fifo_to_mem ou Fifo_to_fifo
38	snd_start : in std_logic; --début de la réception
39	snd_ack :in std_logic; -- acquittement de la réception
40	ram_busy :in std_logic; -- mémoire occupée
41	datalen : in std_logic_vector(Word-1 downto 0); --la longueur du paquet
42	ram_addr_start :in std_logic_vector(ADRLEN-1 downto 0); --addresse de début du bloc de donnée à copier
43	fifo_out_empty,fifo_out_full : in std_logic; --signaux pour le fifo de sortie
44	fifo_out_wr_en : out std_logic; --écriture autorisée dans la fifo de sortie
45	ram_in_rd_en : out std_logic; --lecture autorisée dans la fifo d'entrée
46	ram_in_data_out : in std_logic_vector(Word-1 downto 0);
47	ram_in_addr_rd :out std_logic_vector(ADRLEN-1 downto 0); --addresse de la donnée à copier
48	fifo_out_data_in : out std_logic_vector(Word-1 downto 0);
49	snd_comp : out std_logic); -- fin de la réception
50
51	end mem2fifo_a;
52
53	architecture Behavioral of mem2fifo_a is
54	type typ_send is (s_head,s_len,s_len2,s_data,s_pulse,s_end);
55	signal etsnd : typ_send;
56	signal snd_state,next_snd_state:natural range 0 to 7:=0;
57	signal p_len,p_len_i : natural range 0 to 255;
58	signal n,n_i:natural range 0 to 255;
59	signal wr_ok,rd_ok:std_logic:='0';
60	signal wr_ok_i,rd_ok_i:std_logic:='0';
61	signal sfifo_in,Data_to_send,Data_to_send_i : std_logic_vector(Word-1 downto 0);
62	signal spush : std_logic:='0';
63	signal err : std_logic_vector(Word-1 downto 0):=(others =>'0');
64	begin
65
66	mem_copy_sync:process(clk,reset)
67
68	begin
69
70
71	if reset='1' then
72	n<=0;
73	Snd_state<=0;
74	P_len<=0;
75	Data_to_send<=(others=>'0');
76	wr_ok<='0';
77	rd_ok<='0';
78	else
79	if rising_edge(clk) then
80	Snd_state<=Next_Snd_state;
81	n<=n_i;
82	p_len<=P_len_i;
83	Data_to_send<=Data_to_send_i;
84	wr_ok<=wr_ok_i;
85	rd_ok<=rd_ok_i;
86	end if;
87	end if;
88	end process mem_copy_sync;
89	-- affectation concurentes
90	mem_copy_val:process (Snd_state,Etsnd,n,copy_mode,data_to_send,rd_ok,wr_ok,spush,
91	ram_addr_start)
92	begin
93	fifo_out_wr_en<='0';
94	ram_in_rd_en<='0';
95	fifo_out_data_in<=data_to_send;
96	ram_in_addr_rd<=std_logic_vector(to_unsigned(to_integer(unsigned(ram_addr_start)+n),ADRLEN));
97
98	if (Snd_state=1) or (snd_state=2) then
99	fifo_out_wr_en<=wr_ok;
100	ram_in_rd_en<=rd_ok;
101	fifo_out_data_in<=data_to_send;
102	ram_in_addr_rd<=std_logic_vector(to_unsigned(to_integer(unsigned(ram_addr_start)+n),ADRLEN));
103	end if;
104
105	end process mem_copy_val;
106	-- process qui envoie des données en provenance d'un Fifo vers un Fifo
107	mem_to_fifo:process(snd_state,copy_mode,snd_start,snd_ack,
108	fifo_out_full,ram_in_data_out,p_len,n,wr_ok,rd_ok,datalen,Data_to_send)
109	variable onepop:std_logic:='0';
110	begin
111	Next_snd_state<=snd_state; --valeur par defaut
112	Data_To_Send_i<=Data_to_send;
113	wr_ok_i<=wr_ok;
114	rd_ok_i<=rd_ok;
115	n_i<=n;
116	p_len_i<=p_len;
117	snd_comp<='0';
118	case snd_state is
119
120	when 0 => wr_ok_i<='0';rd_ok_i<='0';onepop:='0';
121	if snd_start='1' then
122	P_len_i<=to_integer(unsigned(datalen));
123	next_snd_state<=1;
124	n_i<=0;
125	rd_ok_i<='1';
126	end if;
127
128	snd_comp<='0';
129	when 1=> --placer la première donnée sur le bus
130	if copy_mode='1' then
131
132	data_to_send_i <=ram_in_data_out ;
133
134	else
135	data_to_send_i<=ram_in_data_out;
136	end if;
137	rd_ok_i<='1';
138	next_snd_state<=2;
139	when 2=> if P_len > 0 then
140	if copy_mode='1' then
141	if onepop='0' then
142	data_to_send_i <=ram_in_data_out ;
143	rd_Ok_i<='1';
144	onepop:='1'; --une donnée lue il faut arrêter de dépiler
145
146	else
147	rd_Ok_i<='0';
148	end if;
149	else
150	onepop:='1';rd_ok_i<='1';
151	data_to_send_i<=ram_in_data_out;
152	end if;
153
154	if (fifo_out_full = '0') and onepop='1' then
155	-- if onepop='1' then
156	wr_ok_i<='1';
157	onepop:='0';
158	p_len_i<=p_len-1;
159	n_i<=n+1; --passer à l'octet suivant
160	else
161	wr_Ok_i<='0';
162	end if;
163	else
164	rd_ok_i<='0';
165	wr_ok_i<='0';
166	next_snd_state<=3;
167	snd_comp<='0';
168	end if;
169	when 3 => --fin de la copie
170	if snd_ack='1' then
171
172	next_snd_state<=4;
173	end if;
174	wr_ok_i<='0';rd_ok_i<='0';
175	snd_comp<='1';
176
177	when 4 =>if snd_start='0' then --ces deux étapes peuvent être combinées en une seule
178	next_snd_state<=0;
179	end if;
180	snd_comp<='0';
181
182	when others => next_snd_state<=0;
183	snd_comp<='0';
184	rd_ok_i<='0';
185	wr_ok_i<='0';
186	data_to_send_i <=(others=>'U');
187	end case;
188	end process mem_to_fifo;
189
190	end Behavioral;
191

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source: PROJECT_CORE_MPI/MPI_HCL/BRANCHES/v2.1/CORE_MPI/mem2fifo.vhd

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