[142] | 1 | ---------------------------------------------------------------------------------- |
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| 2 | -- Company: |
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| 3 | -- Engineer: |
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| 4 | -- |
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| 5 | -- Create Date: 18:01:21 28/06/2014 |
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| 6 | -- Design Name: |
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| 7 | -- Module Name: Mem2fifo - Behavioral |
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| 8 | -- Project Name: |
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| 9 | -- Target Devices: |
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| 10 | -- Tool versions: |
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| 11 | -- Description: |
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| 12 | -- |
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| 13 | -- Dependencies: |
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| 14 | -- |
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| 15 | -- Revision: |
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| 16 | -- Revision 0.01 - File Created |
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| 17 | -- Additional Comments: |
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| 18 | -- |
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| 19 | ---------------------------------------------------------------------------------- |
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| 20 | library IEEE; |
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| 21 | use IEEE.STD_LOGIC_1164.ALL; |
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| 22 | USE ieee.numeric_std.ALL; |
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| 23 | Library NoCLib; |
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| 24 | use NoCLib.CoreTypes.all; |
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| 25 | -- Uncomment the following library declaration if using |
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| 26 | -- arithmetic functions with Signed or Unsigned values |
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| 27 | --use IEEE.NUMERIC_STD.ALL; |
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| 28 | |
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| 29 | -- Uncomment the following library declaration if instantiating |
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| 30 | -- any Xilinx primitives in this code. |
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| 31 | --library UNISIM; |
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| 32 | --use UNISIM.VComponents.all; |
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| 33 | |
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| 34 | entity mem2fifo_a is --copy from memory to fifo |
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| 35 | port ( |
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| 36 | clk,reset : in std_logic; |
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| 37 | copy_mode : in std_logic; --Fifo_to_mem ou Fifo_to_fifo |
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| 38 | snd_start : in std_logic; --début de la réception |
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| 39 | snd_ack :in std_logic; -- acquittement de la réception |
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| 40 | ram_busy :in std_logic; -- mémoire occupée |
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| 41 | datalen : in std_logic_vector(Word-1 downto 0); --la longueur du paquet |
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| 42 | ram_addr_start :in std_logic_vector(ADRLEN-1 downto 0); --addresse de début du bloc de donnée à copier |
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| 43 | fifo_out_empty,fifo_out_full : in std_logic; --signaux pour le fifo de sortie |
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| 44 | fifo_out_wr_en : out std_logic; --écriture autorisée dans la fifo de sortie |
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| 45 | ram_in_rd_en : out std_logic; --lecture autorisée dans la fifo d'entrée |
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| 46 | ram_in_data_out : in std_logic_vector(Word-1 downto 0); |
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| 47 | ram_in_addr_rd :out std_logic_vector(ADRLEN-1 downto 0); --addresse de la donnée à copier |
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| 48 | fifo_out_data_in : out std_logic_vector(Word-1 downto 0); |
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| 49 | snd_comp : out std_logic); -- fin de la réception |
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| 50 | |
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| 51 | end mem2fifo_a; |
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| 52 | |
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| 53 | architecture Behavioral of mem2fifo_a is |
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| 54 | type typ_send is (s_head,s_len,s_len2,s_data,s_pulse,s_end); |
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| 55 | signal etsnd : typ_send; |
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| 56 | signal snd_state,next_snd_state:natural range 0 to 7:=0; |
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| 57 | signal p_len,p_len_i : natural range 0 to 255; |
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| 58 | signal n,n_i:natural range 0 to 255; |
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| 59 | signal wr_ok,rd_ok:std_logic:='0'; |
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| 60 | signal wr_ok_i,rd_ok_i:std_logic:='0'; |
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| 61 | signal sfifo_in,Data_to_send,Data_to_send_i : std_logic_vector(Word-1 downto 0); |
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| 62 | signal spush : std_logic:='0'; |
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| 63 | signal err : std_logic_vector(Word-1 downto 0):=(others =>'0'); |
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| 64 | begin |
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| 65 | |
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| 66 | mem_copy_sync:process(clk,reset) |
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| 67 | |
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| 68 | begin |
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| 69 | |
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| 70 | |
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| 71 | if reset='1' then |
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| 72 | n<=0; |
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| 73 | Snd_state<=0; |
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| 74 | P_len<=0; |
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| 75 | Data_to_send<=(others=>'0'); |
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| 76 | wr_ok<='0'; |
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| 77 | rd_ok<='0'; |
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| 78 | else |
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| 79 | if rising_edge(clk) then |
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| 80 | Snd_state<=Next_Snd_state; |
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| 81 | n<=n_i; |
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| 82 | p_len<=P_len_i; |
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| 83 | Data_to_send<=Data_to_send_i; |
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| 84 | wr_ok<=wr_ok_i; |
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| 85 | rd_ok<=rd_ok_i; |
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| 86 | end if; |
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| 87 | end if; |
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| 88 | end process mem_copy_sync; |
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| 89 | -- affectation concurentes |
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| 90 | mem_copy_val:process (Snd_state,Etsnd,n,copy_mode,data_to_send,rd_ok,wr_ok,spush, |
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| 91 | ram_addr_start,data_to_send) |
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| 92 | begin |
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| 93 | fifo_out_wr_en<='0'; |
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| 94 | ram_in_rd_en<='0'; |
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| 95 | fifo_out_data_in<=data_to_send; |
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| 96 | ram_in_addr_rd<=std_logic_vector(to_unsigned(to_integer(unsigned(ram_addr_start)+n),ADRLEN)); |
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| 97 | |
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| 98 | if (Snd_state=1) or (snd_state=2) then |
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| 99 | fifo_out_wr_en<=wr_ok; |
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| 100 | ram_in_rd_en<=rd_ok; |
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| 101 | fifo_out_data_in<=data_to_send; |
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| 102 | ram_in_addr_rd<=std_logic_vector(to_unsigned(to_integer(unsigned(ram_addr_start)+n),ADRLEN)); |
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| 103 | end if; |
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| 104 | |
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| 105 | end process mem_copy_val; |
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| 106 | -- process qui envoie des données en provenance d'un Fifo vers un Fifo |
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| 107 | mem_to_fifo:process(snd_state,copy_mode,snd_start,snd_ack, |
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| 108 | fifo_out_full,ram_in_data_out,p_len,n,wr_ok,rd_ok,datalen) |
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| 109 | variable onepop:std_logic:='0'; |
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| 110 | begin |
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| 111 | Next_snd_state<=snd_state; --valeur par defaut |
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| 112 | Data_To_Send_i<=Data_to_send; |
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| 113 | wr_ok_i<=wr_ok; |
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| 114 | rd_ok_i<=rd_ok; |
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| 115 | n_i<=n; |
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| 116 | p_len_i<=p_len; |
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| 117 | snd_comp<='0'; |
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| 118 | case snd_state is |
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| 119 | |
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| 120 | when 0 => wr_ok_i<='0';rd_ok_i<='0';onepop:='0'; |
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| 121 | if snd_start='1' then |
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| 122 | P_len_i<=to_integer(unsigned(datalen)); |
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| 123 | next_snd_state<=1; |
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| 124 | n_i<=0; |
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| 125 | rd_ok_i<='1'; |
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| 126 | end if; |
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| 127 | |
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| 128 | snd_comp<='0'; |
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| 129 | when 1=> --placer la première donnée sur le bus |
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| 130 | if copy_mode='1' then |
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| 131 | |
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| 132 | data_to_send_i <=ram_in_data_out ; |
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| 133 | |
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| 134 | else |
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| 135 | data_to_send_i<=ram_in_data_out; |
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| 136 | end if; |
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| 137 | rd_ok_i<='1'; |
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| 138 | next_snd_state<=2; |
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| 139 | when 2=> if P_len > 0 then |
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| 140 | if copy_mode='1' then |
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| 141 | if onepop='0' then |
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| 142 | data_to_send_i <=ram_in_data_out ; |
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| 143 | rd_Ok_i<='1'; |
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| 144 | onepop:='1'; --une donnée lue il faut arrêter de dépiler |
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| 145 | |
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| 146 | else |
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| 147 | rd_Ok_i<='0'; |
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| 148 | end if; |
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| 149 | else |
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| 150 | onepop:='1';rd_ok_i<='1'; |
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| 151 | data_to_send_i<=ram_in_data_out; |
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| 152 | end if; |
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| 153 | |
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| 154 | if (fifo_out_full = '0') and onepop='1' then |
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| 155 | -- if onepop='1' then |
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| 156 | wr_ok_i<='1'; |
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| 157 | onepop:='0'; |
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| 158 | p_len_i<=p_len-1; |
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| 159 | n_i<=n+1; --passer à l'octet suivant |
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| 160 | else |
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| 161 | wr_Ok_i<='0'; |
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| 162 | end if; |
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| 163 | else |
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| 164 | rd_ok_i<='0'; |
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| 165 | wr_ok_i<='0'; |
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| 166 | next_snd_state<=3; |
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| 167 | snd_comp<='0'; |
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| 168 | end if; |
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| 169 | when 3 => --fin de la copie |
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| 170 | if snd_ack='1' then |
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| 171 | |
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| 172 | next_snd_state<=4; |
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| 173 | end if; |
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| 174 | wr_ok_i<='0';rd_ok_i<='0'; |
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| 175 | snd_comp<='1'; |
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| 176 | |
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| 177 | when 4 =>if snd_start='0' then --ces deux étapes peuvent être combinées en une seule |
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| 178 | next_snd_state<=0; |
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| 179 | end if; |
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| 180 | snd_comp<='0'; |
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| 181 | |
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| 182 | when others => next_snd_state<=0; |
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| 183 | snd_comp<='0'; |
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| 184 | rd_ok_i<='0'; |
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| 185 | wr_ok_i<='0'; |
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| 186 | data_to_send_i <=(others=>'U'); |
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| 187 | end case; |
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| 188 | end process mem_to_fifo; |
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| 189 | |
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| 190 | end Behavioral; |
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| 191 | |
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