[142] | 1 | -- |
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| 2 | -- Copyright (C) 2006 Johannes Hausensteiner (johannes.hausensteiner@pcl.at) |
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| 3 | -- |
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| 4 | -- This program is free software; you can redistribute it and/or |
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| 5 | -- modify it under the terms of the GNU General Public License |
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| 6 | -- as published by the Free Software Foundation; either version 2 |
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| 7 | -- of the License, or (at your option) any later version. |
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| 8 | -- |
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| 9 | -- This program is distributed in the hope that it will be useful, |
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| 10 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of |
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| 11 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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| 12 | -- GNU General Public License for more details. |
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| 13 | -- |
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| 14 | -- You should have received a copy of the GNU General Public License |
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| 15 | -- along with this program; if not, write to the Free Software |
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| 16 | -- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. |
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| 17 | -- |
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| 18 | -- |
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| 19 | -- Filename: spi_ctrl.vhd |
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| 20 | -- |
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| 21 | -- Function: SPI Flash controller for DIY Calculator |
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| 22 | -- |
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| 23 | -- |
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| 24 | -- Changelog |
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| 25 | -- |
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| 26 | -- 0.1 25.Sep.2006 JH new |
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| 27 | -- 0.2 15.Nov.2006 JH remove old code |
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| 28 | -- 1.0 5.Feb.2007 JH new clocking scheme |
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| 29 | -- 1.1 4.Apr.2007 JH implement high address byte |
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| 30 | -- 1.2 16.Apr.2007 JH clock enable |
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| 31 | -- 1.3 23.Apr.2007 JH remove all asynchronous elements |
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| 32 | -- 1.4 4.May 2007 JH resolve read timing |
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| 33 | -- 1.5 10.May 2007 JH remove read signal |
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| 34 | -- |
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| 35 | |
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| 36 | |
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| 37 | library ieee; |
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| 38 | use ieee.std_logic_1164.all; |
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| 39 | use ieee.std_logic_unsigned.all; |
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| 40 | |
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| 41 | entity spi_ctrl is |
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| 42 | port ( |
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| 43 | clk_in : in std_logic; |
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| 44 | rst : in std_logic; |
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| 45 | spi_clk : out std_logic; |
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| 46 | spi_cs : out std_logic; |
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| 47 | spi_din : in std_logic; |
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| 48 | spi_dout : out std_logic; |
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| 49 | sel : in std_logic; |
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| 50 | wr : in std_logic; |
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| 51 | addr : in std_logic_vector (2 downto 0); |
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| 52 | d_in : in std_logic_vector (7 downto 0); |
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| 53 | d_out : out std_logic_vector (7 downto 0) |
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| 54 | ); |
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| 55 | end spi_ctrl; |
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| 56 | |
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| 57 | architecture rtl of spi_ctrl is |
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| 58 | -- clock generator |
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| 59 | constant SYS_FREQ : integer := 25000000; -- 25MHz |
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| 60 | constant SPI_FREQ : integer := 6250000; -- 6.25MHz |
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| 61 | signal clk_en : std_logic; |
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| 62 | signal clk_cnt : integer range 0 to (SYS_FREQ/SPI_FREQ)-1; |
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| 63 | |
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| 64 | type state_t is ( |
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| 65 | IDLE, TxCMD, TxADD_H, TxADD_M, TxADD_L, TxDUMMY, TxDATA, RxDATA, |
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| 66 | WAIT1, WAIT2, WAIT3, WAIT4, WAIT6, WAIT5, WAIT7, WAIT8, CLR_CMD); |
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| 67 | signal state, next_state : state_t; |
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| 68 | |
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| 69 | -- transmitter |
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| 70 | signal tx_reg, tx_sreg : std_logic_vector (7 downto 0); |
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| 71 | signal tx_empty, tx_empty_set : std_logic; |
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| 72 | signal tx_bit_cnt : std_logic_vector (3 downto 0); |
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| 73 | |
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| 74 | -- receiver |
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| 75 | signal rx_sreg : std_logic_vector (7 downto 0); |
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| 76 | signal rx_ready, rx_ready_set, rx_bit_cnt_clr : std_logic; |
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| 77 | signal rx_bit_cnt : std_logic_vector (3 downto 0); |
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| 78 | |
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| 79 | signal wr_cmd, wr_data, wr_add_h, wr_add_m, wr_add_l : std_logic; |
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| 80 | signal rd_stat, rd_add_h, rd_add_m, rd_add_l : std_logic; |
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| 81 | signal rd_data, rd_data1, rd_data2 : std_logic; |
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| 82 | signal spi_cs_int, spi_clk_int : std_logic; |
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| 83 | |
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| 84 | -- auxiliary signals |
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| 85 | signal rx_enable, rx_empty, rx_empty_clr : std_logic; |
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| 86 | signal tx_enable, tx_enable_d : std_logic; |
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| 87 | signal tx_new_data, tx_new_data_clr, is_tx_data, is_wait6 : std_logic; |
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| 88 | signal cmd_clr, busy : std_logic; |
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| 89 | |
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| 90 | -- registers |
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| 91 | signal cmd, tx_data, rx_data : std_logic_vector (7 downto 0); |
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| 92 | signal add_h, add_m, add_l : std_logic_vector (7 downto 0); |
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| 93 | |
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| 94 | -- FLASH commands |
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| 95 | constant NOP : std_logic_vector (7 downto 0) := x"FF"; -- no cmd to execute |
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| 96 | constant WREN : std_logic_vector (7 downto 0) := x"06"; -- write enable |
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| 97 | constant WRDI : std_logic_vector (7 downto 0) := x"04"; -- write disable |
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| 98 | constant RDSR : std_logic_vector (7 downto 0) := x"05"; -- read status reg |
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| 99 | constant WRSR : std_logic_vector (7 downto 0) := x"01"; -- write stat. reg |
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| 100 | constant RDCMD: std_logic_vector (7 downto 0) := x"03"; -- read data |
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| 101 | constant F_RD : std_logic_vector (7 downto 0) := x"0B"; -- fast read data |
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| 102 | constant PP : std_logic_vector (7 downto 0) := x"02"; -- page program |
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| 103 | constant SE : std_logic_vector (7 downto 0) := x"D8"; -- sector erase |
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| 104 | constant BE : std_logic_vector (7 downto 0) := x"C7"; -- bulk erase |
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| 105 | constant DP : std_logic_vector (7 downto 0) := x"B9"; -- deep power down |
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| 106 | constant RES : std_logic_vector (7 downto 0) := x"AB"; -- read signature |
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| 107 | begin |
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| 108 | -- assign signals |
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| 109 | spi_cs <= spi_cs_int; |
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| 110 | spi_clk <= spi_clk_int; |
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| 111 | spi_dout <= tx_sreg(7); |
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| 112 | |
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| 113 | -- clock generator |
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| 114 | spi_divider : process (rst, clk_in) |
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| 115 | begin |
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| 116 | if rst = '1' then |
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| 117 | clk_cnt <= 0; |
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| 118 | clk_en <= '0'; |
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| 119 | spi_clk_int <= '1'; |
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| 120 | elsif falling_edge (clk_in) then |
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| 121 | if clk_cnt = ((SYS_FREQ / SPI_FREQ) - 2) or |
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| 122 | clk_cnt = ((SYS_FREQ / SPI_FREQ) - 3) then |
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| 123 | clk_cnt <= clk_cnt + 1; |
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| 124 | clk_en <= '0'; |
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| 125 | if tx_enable = '1' or rx_enable = '1' then |
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| 126 | spi_clk_int <= '0'; |
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| 127 | else |
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| 128 | spi_clk_int <= '1'; |
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| 129 | end if; |
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| 130 | elsif clk_cnt = ((SYS_FREQ / SPI_FREQ) - 1) then |
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| 131 | clk_cnt <= 0; |
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| 132 | clk_en <= '1'; |
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| 133 | spi_clk_int <= '1'; |
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| 134 | else |
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| 135 | clk_cnt <= clk_cnt + 1; |
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| 136 | clk_en <= '0'; |
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| 137 | spi_clk_int <= '1'; |
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| 138 | end if; |
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| 139 | end if; |
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| 140 | end process; |
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| 141 | |
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| 142 | -- address decoder |
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| 143 | process (sel, addr, wr) |
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| 144 | variable input : std_logic_vector (4 downto 0); |
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| 145 | begin |
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| 146 | input := sel & addr & wr; |
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| 147 | -- defaults |
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| 148 | wr_data <= '0'; |
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| 149 | wr_cmd <= '0'; |
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| 150 | wr_add_h <= '0'; |
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| 151 | wr_add_m <= '0'; |
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| 152 | wr_add_l <= '0'; |
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| 153 | rd_data <= '0'; |
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| 154 | rd_stat <= '0'; |
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| 155 | rd_add_h <= '0'; |
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| 156 | rd_add_m <= '0'; |
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| 157 | rd_add_l <= '0'; |
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| 158 | case input is |
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| 159 | when "10000" => rd_data <= '1'; |
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| 160 | when "10001" => wr_data <= '1'; |
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| 161 | when "10010" => rd_stat <= '1'; |
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| 162 | when "10011" => wr_cmd <= '1'; |
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| 163 | when "10100" => rd_add_l <= '1'; |
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| 164 | when "10101" => wr_add_l <= '1'; |
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| 165 | when "10110" => rd_add_m <= '1'; |
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| 166 | when "10111" => wr_add_m <= '1'; |
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| 167 | when "11000" => rd_add_h <= '1'; |
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| 168 | when "11001" => wr_add_h <= '1'; |
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| 169 | when others => null; |
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| 170 | end case; |
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| 171 | end process; |
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| 172 | |
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| 173 | -- read back registers |
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| 174 | d_out(0) <= (rx_data(0) and rd_data) |
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| 175 | or (busy and rd_stat) |
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| 176 | or (add_h(0) and rd_add_h) |
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| 177 | or (add_m(0) and rd_add_m) |
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| 178 | or (add_l(0) and rd_add_l); |
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| 179 | |
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| 180 | d_out(1) <= (rx_data(1) and rd_data) |
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| 181 | or (tx_empty and rd_stat) |
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| 182 | or (add_h(1) and rd_add_h) |
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| 183 | or (add_m(1) and rd_add_m) |
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| 184 | or (add_l(1) and rd_add_l); |
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| 185 | |
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| 186 | d_out(2) <= (rx_data(2) and rd_data) |
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| 187 | or (rx_ready and rd_stat) |
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| 188 | or (add_h(2) and rd_add_h) |
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| 189 | or (add_m(2) and rd_add_m) |
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| 190 | or (add_l(2) and rd_add_l); |
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| 191 | |
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| 192 | d_out(3) <= (rx_data(3) and rd_data) |
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| 193 | or (is_wait6 and rd_stat) |
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| 194 | or (add_h(3) and rd_add_h) |
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| 195 | or (add_m(3) and rd_add_m) |
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| 196 | or (add_l(3) and rd_add_l); |
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| 197 | |
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| 198 | d_out(4) <= (rx_data(4) and rd_data) |
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| 199 | or ('0' and rd_stat) |
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| 200 | or (add_h(4) and rd_add_h) |
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| 201 | or (add_m(4) and rd_add_m) |
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| 202 | or (add_l(4) and rd_add_l); |
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| 203 | |
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| 204 | d_out(5) <= (rx_data(5) and rd_data) |
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| 205 | or ('0' and rd_stat) |
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| 206 | or (add_h(5) and rd_add_h) |
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| 207 | or (add_m(5) and rd_add_m) |
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| 208 | or (add_l(5) and rd_add_l); |
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| 209 | |
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| 210 | d_out(6) <= (rx_data(6) and rd_data) |
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| 211 | or ('0' and rd_stat) |
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| 212 | or (add_h(6) and rd_add_h) |
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| 213 | or (add_m(6) and rd_add_m) |
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| 214 | or (add_l(6) and rd_add_l); |
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| 215 | |
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| 216 | d_out(7) <= (rx_data(7) and rd_data) |
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| 217 | or ('0' and rd_stat) |
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| 218 | or (add_h(7) and rd_add_h) |
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| 219 | or (add_m(7) and rd_add_m) |
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| 220 | or (add_l(7) and rd_add_l); |
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| 221 | |
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| 222 | -- write command register |
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| 223 | process (rst, cmd_clr, clk_in) |
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| 224 | begin |
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| 225 | if rst = '1' or cmd_clr = '1' then |
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| 226 | cmd <= NOP; |
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| 227 | elsif rising_edge (clk_in) then |
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| 228 | if wr_cmd = '1' then |
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| 229 | cmd <= d_in; |
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| 230 | end if; |
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| 231 | end if; |
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| 232 | end process; |
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| 233 | |
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| 234 | -- write address high register |
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| 235 | process (rst, clk_in) |
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| 236 | begin |
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| 237 | if rst = '1' then |
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| 238 | add_h <= x"00"; |
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| 239 | elsif rising_edge (clk_in) then |
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| 240 | if wr_add_h = '1' then |
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| 241 | add_h <= d_in; |
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| 242 | end if; |
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| 243 | end if; |
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| 244 | end process; |
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| 245 | |
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| 246 | -- write address mid register |
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| 247 | process (rst, clk_in) |
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| 248 | begin |
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| 249 | if rst = '1' then |
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| 250 | add_m <= x"00"; |
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| 251 | elsif rising_edge (clk_in) then |
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| 252 | if wr_add_m ='1' then |
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| 253 | add_m <= d_in; |
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| 254 | end if; |
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| 255 | end if; |
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| 256 | end process; |
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| 257 | |
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| 258 | -- write address low register |
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| 259 | process (rst, clk_in) |
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| 260 | begin |
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| 261 | if rst = '1' then |
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| 262 | add_l <= x"00"; |
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| 263 | elsif rising_edge (clk_in) then |
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| 264 | if wr_add_l ='1' then |
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| 265 | add_l <= d_in; |
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| 266 | end if; |
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| 267 | end if; |
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| 268 | end process; |
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| 269 | |
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| 270 | -- write tx data register |
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| 271 | process (rst, clk_in) |
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| 272 | begin |
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| 273 | if rst = '1' then |
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| 274 | tx_data <= x"00"; |
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| 275 | elsif rising_edge (clk_in) then |
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| 276 | if wr_data = '1' then |
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| 277 | tx_data <= d_in; |
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| 278 | end if; |
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| 279 | end if; |
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| 280 | end process; |
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| 281 | |
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| 282 | -- new tx data flag |
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| 283 | tx_new_data_clr <= tx_empty_set and is_tx_data; |
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| 284 | process (rst, tx_new_data_clr, clk_in) |
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| 285 | begin |
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| 286 | if rst = '1' or tx_new_data_clr = '1' then |
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| 287 | tx_new_data <= '0'; |
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| 288 | elsif rising_edge (clk_in) then |
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| 289 | if wr_data ='1' then |
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| 290 | tx_new_data <= '1'; |
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| 291 | end if; |
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| 292 | end if; |
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| 293 | end process; |
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| 294 | |
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| 295 | -- advance the state machine |
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| 296 | process (rst, clk_in) |
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| 297 | begin |
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| 298 | if rst = '1' then |
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| 299 | state <= IDLE; |
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| 300 | elsif rising_edge (clk_in) then |
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| 301 | if clk_en = '1' then |
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| 302 | state <= next_state; |
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| 303 | end if; |
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| 304 | end if; |
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| 305 | end process; |
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| 306 | |
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| 307 | -- state machine transition table |
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| 308 | process (state, cmd, tx_bit_cnt, tx_new_data, rx_bit_cnt, rx_empty) |
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| 309 | begin |
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| 310 | case state is |
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| 311 | when IDLE => |
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| 312 | case cmd is |
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| 313 | when NOP => next_state <= IDLE; |
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| 314 | when others => next_state <= TxCMD; |
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| 315 | end case; |
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| 316 | |
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| 317 | when TxCMD => |
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| 318 | if tx_bit_cnt < x"7" then |
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| 319 | next_state <= TxCMD; |
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| 320 | else |
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| 321 | case cmd is |
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| 322 | when WREN | WRDI | BE | DP => next_state <= CLR_CMD; |
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| 323 | when SE | PP | RES | RDCMD | F_RD|WRSR|RDSR => next_state <= WAIT1; |
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| 324 | when others => next_state <= CLR_CMD; |
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| 325 | end case; |
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| 326 | end if; |
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| 327 | |
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| 328 | when WAIT1 => |
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| 329 | case cmd is |
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| 330 | when WREN | WRDI | BE | DP => next_state <= CLR_CMD; |
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| 331 | when SE | PP | RES | RDCMD | F_RD => next_state <= TxADD_H; |
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| 332 | when WRSR => next_state <= TxDATA; |
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| 333 | when RDSR => next_state <= RxDATA; |
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| 334 | when others => next_state <= CLR_CMD; |
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| 335 | end case; |
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| 336 | |
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| 337 | when TxADD_H => |
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| 338 | if tx_bit_cnt < x"7" then |
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| 339 | next_state <= TxADD_H; |
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| 340 | else |
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| 341 | next_state <= WAIT2; |
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| 342 | end if; |
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| 343 | |
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| 344 | when WAIT2 => next_state <= TxADD_M; |
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| 345 | |
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| 346 | when TxADD_M => |
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| 347 | if tx_bit_cnt < x"7" then |
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| 348 | next_state <= TxADD_M; |
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| 349 | else |
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| 350 | next_state <= WAIT3; |
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| 351 | end if; |
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| 352 | |
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| 353 | when WAIT3 => next_state <= TxADD_L; |
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| 354 | |
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| 355 | when TxADD_L => |
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| 356 | if tx_bit_cnt < x"7" then |
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| 357 | next_state <= TxADD_L; |
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| 358 | else |
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| 359 | case cmd is |
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| 360 | when PP => next_state <= WAIT6; |
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| 361 | when SE | RES | RDCMD | F_RD => next_state <= WAIT4; |
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| 362 | when others => next_state <= CLR_CMD; |
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| 363 | end case; |
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| 364 | end if; |
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| 365 | |
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| 366 | when WAIT4 => |
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| 367 | case cmd is |
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| 368 | when F_RD => next_state <= TxDUMMY; |
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| 369 | when RES | RDCMD => next_state <= RxDATA; |
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| 370 | when others => next_state <= CLR_CMD; |
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| 371 | end case; |
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| 372 | |
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| 373 | when TxDUMMY => |
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| 374 | if tx_bit_cnt < x"7" then |
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| 375 | next_state <= TxDUMMY; |
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| 376 | else |
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| 377 | next_state <= WAIT8; |
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| 378 | end if; |
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| 379 | |
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| 380 | when WAIT7 => next_state <= WAIT8; |
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| 381 | |
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| 382 | when WAIT8 => |
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| 383 | case cmd is |
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| 384 | when RDCMD | F_RD => |
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| 385 | if rx_empty = '1' then |
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| 386 | next_state <= RxDATA; |
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| 387 | else |
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| 388 | next_state <= WAIT8; |
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| 389 | end if; |
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| 390 | when others => next_state <= CLR_CMD; |
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| 391 | end case; |
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| 392 | |
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| 393 | when RxDATA => |
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| 394 | if rx_bit_cnt < x"7" then |
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| 395 | next_state <= RxDATA; |
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| 396 | else |
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| 397 | case cmd is |
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| 398 | when RDCMD | F_RD => next_state <= WAIT7; |
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| 399 | when RDSR | RES => next_state <= WAIT5; |
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| 400 | when others => next_state <= CLR_CMD; |
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| 401 | end case; |
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| 402 | end if; |
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| 403 | |
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| 404 | when TxDATA => |
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| 405 | if tx_bit_cnt < x"7" then |
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| 406 | next_state <= TxDATA; |
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| 407 | else |
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| 408 | case cmd is |
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| 409 | when PP => next_state <= WAIT6; |
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| 410 | when others => next_state <= CLR_CMD; |
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| 411 | end case; |
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| 412 | end if; |
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| 413 | |
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| 414 | when WAIT6 => |
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| 415 | case cmd is |
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| 416 | when PP => |
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| 417 | if tx_new_data = '1' then |
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| 418 | next_state <= TxDATA; |
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| 419 | else |
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| 420 | next_state <= WAIT6; |
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| 421 | end if; |
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| 422 | when others => next_state <= CLR_CMD; |
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| 423 | end case; |
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| 424 | |
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| 425 | when WAIT5 => next_state <= CLR_CMD; |
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| 426 | |
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| 427 | when CLR_CMD => next_state <= IDLE; |
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| 428 | end case; |
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| 429 | end process; |
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| 430 | |
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| 431 | -- state machine output table |
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| 432 | process (state, cmd, tx_data, add_m, add_l, add_h) |
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| 433 | begin |
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| 434 | -- default values |
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| 435 | tx_enable <= '0'; |
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| 436 | rx_enable <= '0'; |
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| 437 | rx_bit_cnt_clr <= '1'; |
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| 438 | tx_reg <= x"FF"; |
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| 439 | spi_cs_int <= '0'; |
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| 440 | busy <= '1'; |
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| 441 | cmd_clr <= '0'; |
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| 442 | is_tx_data <= '0'; |
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| 443 | is_wait6 <= '0'; |
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| 444 | |
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| 445 | case state is |
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| 446 | when IDLE => |
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| 447 | busy <= '0'; |
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| 448 | when TxCMD => |
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| 449 | tx_reg <= cmd; |
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| 450 | tx_enable <= '1'; |
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| 451 | spi_cs_int <= '1'; |
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| 452 | when TxDATA => |
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| 453 | tx_reg <= tx_data; |
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| 454 | tx_enable <= '1'; |
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| 455 | spi_cs_int <= '1'; |
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| 456 | is_tx_data <= '1'; |
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| 457 | when TxADD_H => |
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| 458 | tx_reg <= add_h; |
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| 459 | tx_enable <= '1'; |
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| 460 | spi_cs_int <= '1'; |
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| 461 | when TxADD_M => |
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| 462 | tx_reg <= add_m; |
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| 463 | tx_enable <= '1'; |
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| 464 | spi_cs_int <= '1'; |
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| 465 | when TxADD_L => |
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| 466 | tx_reg <= add_l; |
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| 467 | tx_enable <= '1'; |
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| 468 | spi_cs_int <= '1'; |
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| 469 | when TxDUMMY => |
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| 470 | tx_reg <= x"00"; |
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| 471 | tx_enable <= '1'; |
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| 472 | spi_cs_int <= '1'; |
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| 473 | when RxDATA => |
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| 474 | rx_bit_cnt_clr <= '0'; |
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| 475 | rx_enable <= '1'; |
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| 476 | spi_cs_int <= '1'; |
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| 477 | when WAIT1 | WAIT2 | WAIT3 | WAIT4 | WAIT8 => |
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| 478 | spi_cs_int <= '1'; |
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| 479 | when WAIT6 => |
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| 480 | is_wait6 <= '1'; |
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| 481 | spi_cs_int <= '1'; |
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| 482 | when WAIT5 | WAIT7 => |
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| 483 | rx_bit_cnt_clr <= '0'; |
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| 484 | spi_cs_int <= '1'; |
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| 485 | when CLR_CMD => |
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| 486 | cmd_clr <= '1'; |
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| 487 | when others => null; |
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| 488 | end case; |
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| 489 | end process; |
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| 490 | |
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| 491 | -- the tx_empty flip flop |
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| 492 | process (rst, wr_data, clk_in) |
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| 493 | begin |
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| 494 | if rst = '1' then |
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| 495 | tx_empty <= '1'; |
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| 496 | elsif wr_data = '1' then |
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| 497 | tx_empty <= '0'; |
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| 498 | elsif rising_edge (clk_in) then |
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| 499 | if tx_empty_set = '1' then |
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| 500 | tx_empty <= '1'; |
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| 501 | end if; |
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| 502 | end if; |
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| 503 | end process; |
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| 504 | |
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| 505 | -- delay the tx_enable signal |
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| 506 | process (rst, clk_in) |
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| 507 | begin |
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| 508 | if rst = '1' then |
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| 509 | tx_enable_d <= '0'; |
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| 510 | elsif rising_edge (clk_in) then |
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| 511 | tx_enable_d <= tx_enable; |
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| 512 | end if; |
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| 513 | end process; |
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| 514 | |
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| 515 | -- transmitter shift register and bit counter |
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| 516 | process (rst, tx_reg, tx_enable_d, clk_in) |
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| 517 | begin |
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| 518 | if rst = '1' then |
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| 519 | tx_sreg <= x"FF"; |
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| 520 | tx_bit_cnt <= x"0"; |
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| 521 | tx_empty_set <= '0'; |
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| 522 | elsif tx_enable_d = '0' then |
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| 523 | tx_sreg <= tx_reg; |
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| 524 | tx_bit_cnt <= x"0"; |
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| 525 | tx_empty_set <= '0'; |
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| 526 | elsif rising_edge (clk_in) then |
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| 527 | if clk_en = '1' then |
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| 528 | tx_bit_cnt <= tx_bit_cnt + 1; |
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| 529 | tx_sreg <= tx_sreg (6 downto 0) & '1'; |
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| 530 | if tx_bit_cnt = x"6" and is_tx_data = '1' then |
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| 531 | tx_empty_set <= '1'; |
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| 532 | else |
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| 533 | tx_empty_set <= '0'; |
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| 534 | end if; |
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| 535 | end if; |
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| 536 | end if; |
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| 537 | end process; |
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| 538 | |
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| 539 | -- synchronize rd_data |
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| 540 | process (rst, clk_in) |
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| 541 | begin |
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| 542 | if rst = '1' then |
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| 543 | rd_data1 <= '0'; |
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| 544 | elsif falling_edge (clk_in) then |
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| 545 | rd_data1 <= rd_data; |
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| 546 | end if; |
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| 547 | end process; |
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| 548 | |
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| 549 | process (rst, clk_in) |
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| 550 | begin |
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| 551 | if rst = '1' then |
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| 552 | rd_data2 <= '0'; |
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| 553 | elsif falling_edge (clk_in) then |
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| 554 | if rd_data = '0' then |
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| 555 | rd_data2 <= rd_data1; |
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| 556 | end if; |
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| 557 | end if; |
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| 558 | end process; |
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| 559 | |
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| 560 | -- the rx_empty flip flop |
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| 561 | process (rst, clk_in) |
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| 562 | begin |
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| 563 | if rst = '1' then |
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| 564 | rx_empty <= '1'; |
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| 565 | elsif rising_edge (clk_in) then |
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| 566 | if rx_empty_clr = '1' then |
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| 567 | rx_empty <= '0'; |
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| 568 | elsif rd_data2 = '1' then |
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| 569 | rx_empty <= '1'; |
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| 570 | end if; |
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| 571 | end if; |
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| 572 | end process; |
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| 573 | |
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| 574 | -- the rx_ready flip flop |
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| 575 | process (rst, clk_in) |
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| 576 | begin |
---|
| 577 | if rst = '1' then |
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| 578 | rx_ready <= '0'; |
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| 579 | elsif rising_edge (clk_in) then |
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| 580 | if rd_data = '1' then |
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| 581 | rx_ready <= '0'; |
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| 582 | elsif rx_ready_set = '1' then |
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| 583 | rx_ready <= '1'; |
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| 584 | end if; |
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| 585 | end if; |
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| 586 | end process; |
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| 587 | |
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| 588 | -- the rx_data register |
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| 589 | process (rst, clk_in) |
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| 590 | begin |
---|
| 591 | if rst = '1' then |
---|
| 592 | rx_data <= x"FF"; |
---|
| 593 | elsif rising_edge (clk_in) then |
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| 594 | if rx_ready_set = '1' then |
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| 595 | rx_data <= rx_sreg; |
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| 596 | end if; |
---|
| 597 | end if; |
---|
| 598 | end process; |
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| 599 | |
---|
| 600 | -- receiver shift register and bit counter |
---|
| 601 | process (rst, rx_bit_cnt_clr, clk_in) |
---|
| 602 | begin |
---|
| 603 | if rst = '1' or rx_bit_cnt_clr = '1' then |
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| 604 | rx_bit_cnt <= x"0"; |
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| 605 | rx_ready_set <= '0'; |
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| 606 | rx_empty_clr <= '0'; |
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| 607 | rx_sreg <= x"FF"; |
---|
| 608 | elsif rising_edge (clk_in) then |
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| 609 | if clk_en = '1' then |
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| 610 | rx_sreg <= rx_sreg (6 downto 0) & spi_din; |
---|
| 611 | case rx_bit_cnt is |
---|
| 612 | when x"0" => |
---|
| 613 | rx_bit_cnt <= rx_bit_cnt + 1; |
---|
| 614 | rx_ready_set <= '0'; |
---|
| 615 | rx_empty_clr <= '1'; |
---|
| 616 | when x"1" | x"2" | x"3" | x"4" | x"5" | x"6" => |
---|
| 617 | rx_bit_cnt <= rx_bit_cnt + 1; |
---|
| 618 | rx_ready_set <= '0'; |
---|
| 619 | rx_empty_clr <= '0'; |
---|
| 620 | when x"7" => |
---|
| 621 | rx_bit_cnt <= rx_bit_cnt + 1; |
---|
| 622 | rx_ready_set <= '1'; |
---|
| 623 | rx_empty_clr <= '0'; |
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| 624 | when others => |
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| 625 | null; |
---|
| 626 | end case; |
---|
| 627 | end if; |
---|
| 628 | end if; |
---|
| 629 | end process; |
---|
| 630 | end rtl; |
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