[143] | 1 | ---------------------------------------------------------------------------------- |
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| 2 | -- Company: |
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| 3 | -- Engineer: KIEGAING EMMANUEL GEL EN 5 |
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| 4 | -- |
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| 5 | -- Create Date: 19:56:34 05/06/2011 |
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| 6 | -- Design Name: |
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| 7 | -- Module Name: Sheduler - Behavioral |
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| 8 | -- Project Name: |
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| 9 | -- Target Devices: |
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| 10 | -- Tool versions: |
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| 11 | -- Description: Module de l'ordonnanceur du switch crossbar |
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| 12 | -- l'algorithme utilisé est le DPA (diagonal propagation arbiter) |
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| 13 | -- intencie un scheduler particulier en fonction du nombre de port |
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| 14 | -- Dependencies: |
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| 15 | -- |
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| 16 | -- Revision: 1.0 |
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| 17 | -- reconstruction du dpa |
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| 18 | -- Revision 0.01 - File Created |
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| 19 | -- Additional Comments: |
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| 20 | -- |
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| 21 | ---------------------------------------------------------------------------------- |
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| 22 | library IEEE; |
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| 23 | use IEEE.STD_LOGIC_1164.ALL; |
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| 24 | use IEEE.STD_LOGIC_ARITH.ALL; |
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| 25 | use IEEE.STD_LOGIC_UNSIGNED.ALL; |
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| 26 | --use Work.Sheduler_package.all; |
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| 27 | |
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| 28 | ---- Uncomment the following library declaration if instantiating |
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| 29 | ---- any Xilinx primitives in this code. |
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| 30 | --library UNISIM; |
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| 31 | --use UNISIM.VComponents.all; |
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| 32 | |
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| 33 | entity Scheduler is |
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| 34 | generic(number_of_ports : positive := 4); |
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| 35 | Port ( Request : in STD_LOGIC_VECTOR (number_of_ports*number_of_ports downto 1); |
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| 36 | Fifo_full : in STD_LOGIC_VECTOR (number_of_ports downto 1); |
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| 37 | clk : in STD_LOGIC; |
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| 38 | reset : in STD_LOGIC; |
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| 39 | priority_rotation : in STD_LOGIC_VECTOR (number_of_ports downto 1); |
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| 40 | port_grant : out STD_LOGIC_VECTOR (number_of_ports*number_of_ports downto 1)); |
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| 41 | end Scheduler; |
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| 42 | |
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| 43 | architecture Behavioral of Scheduler is |
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| 44 | -- signaux pour le pipeline; |
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| 45 | signal Request_latch :STD_LOGIC_VECTOR (number_of_ports*number_of_ports downto 1):=(others=>'0'); |
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| 46 | signal Fifo_full_latch : STD_LOGIC_VECTOR (number_of_ports downto 1):=(others=>'0'); |
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| 47 | signal priority_rotation_latch : STD_LOGIC_VECTOR (number_of_ports downto 1):=(others=>'1'); |
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| 48 | |
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| 49 | -- composants du scheduler |
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| 50 | COMPONENT Scheduler2_2 |
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| 51 | PORT( |
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| 52 | Request : IN std_logic_vector(4 downto 1); |
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| 53 | Fifo_full : IN std_logic_vector(2 downto 1); |
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| 54 | clk : IN std_logic; |
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| 55 | reset : IN std_logic; |
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| 56 | port_grant : OUT std_logic_vector(4 downto 1); |
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| 57 | priority_rotation : in STD_LOGIC_VECTOR (2 downto 1) |
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| 58 | ); |
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| 59 | END COMPONENT; |
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| 60 | |
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| 61 | COMPONENT Scheduler3_3 |
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| 62 | PORT( |
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| 63 | Request : IN std_logic_vector(9 downto 1); |
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| 64 | Fifo_full : IN std_logic_vector(3 downto 1); |
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| 65 | clk : IN std_logic; |
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| 66 | reset : IN std_logic; |
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| 67 | port_grant : OUT std_logic_vector(9 downto 1); |
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| 68 | priority_rotation : in STD_LOGIC_VECTOR (3 downto 1) |
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| 69 | ); |
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| 70 | END COMPONENT; |
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| 71 | |
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| 72 | COMPONENT Scheduler4_4 |
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| 73 | PORT( |
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| 74 | Request : IN std_logic_vector(16 downto 1); |
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| 75 | Fifo_full : IN std_logic_vector(4 downto 1); |
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| 76 | clk : IN std_logic; |
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| 77 | reset : IN std_logic; |
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| 78 | port_grant : OUT std_logic_vector(16 downto 1); |
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| 79 | priority_rotation : in STD_LOGIC_VECTOR (4 downto 1) |
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| 80 | ); |
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| 81 | END COMPONENT; |
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| 82 | |
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| 83 | COMPONENT Scheduler5_5 |
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| 84 | PORT( |
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| 85 | Request : IN std_logic_vector(25 downto 1); |
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| 86 | Fifo_full : IN std_logic_vector(5 downto 1); |
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| 87 | clk : IN std_logic; |
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| 88 | reset : IN std_logic; |
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| 89 | port_grant : OUT std_logic_vector(25 downto 1); |
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| 90 | priority_rotation : in STD_LOGIC_VECTOR (5 downto 1) |
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| 91 | ); |
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| 92 | END COMPONENT; |
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| 93 | |
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| 94 | COMPONENT Scheduler6_6 |
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| 95 | PORT( |
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| 96 | Request : IN std_logic_vector(36 downto 1); |
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| 97 | Fifo_full : IN std_logic_vector(6 downto 1); |
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| 98 | clk : IN std_logic; |
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| 99 | reset : IN std_logic; |
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| 100 | port_grant : OUT std_logic_vector(36 downto 1); |
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| 101 | priority_rotation : in STD_LOGIC_VECTOR (6 downto 1) |
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| 102 | ); |
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| 103 | END COMPONENT; |
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| 104 | |
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| 105 | COMPONENT Scheduler7_7 |
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| 106 | PORT( |
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| 107 | Request : IN std_logic_vector(49 downto 1); |
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| 108 | Fifo_full : IN std_logic_vector(7 downto 1); |
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| 109 | clk : IN std_logic; |
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| 110 | reset : IN std_logic; |
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| 111 | port_grant : OUT std_logic_vector(49 downto 1); |
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| 112 | priority_rotation : in STD_LOGIC_VECTOR (7 downto 1) |
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| 113 | ); |
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| 114 | END COMPONENT; |
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| 115 | |
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| 116 | COMPONENT Scheduler8_8 |
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| 117 | PORT( |
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| 118 | Req : IN std_logic_vector(64 downto 1); |
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| 119 | Fifo_full : IN std_logic_vector(8 downto 1); |
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| 120 | clk : IN std_logic; |
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| 121 | reset : IN std_logic; |
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| 122 | port_grant : OUT std_logic_vector(64 downto 1); |
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| 123 | priority_rotation : in STD_LOGIC_VECTOR (8 downto 1) |
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| 124 | ); |
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| 125 | END COMPONENT; |
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| 126 | |
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| 127 | COMPONENT Scheduler9_9 |
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| 128 | PORT( |
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| 129 | Request : IN std_logic_vector(81 downto 1); |
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| 130 | Fifo_full : IN std_logic_vector(9 downto 1); |
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| 131 | clk : IN std_logic; |
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| 132 | reset : IN std_logic; |
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| 133 | port_grant : OUT std_logic_vector(81 downto 1); |
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| 134 | priority_rotation : in STD_LOGIC_VECTOR (9 downto 1) |
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| 135 | ); |
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| 136 | END COMPONENT; |
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| 137 | |
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| 138 | COMPONENT Scheduler10_10 |
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| 139 | PORT( |
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| 140 | Request : IN std_logic_vector(100 downto 1); |
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| 141 | Fifo_full : IN std_logic_vector(10 downto 1); |
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| 142 | clk : IN std_logic; |
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| 143 | reset : IN std_logic; |
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| 144 | port_grant : OUT std_logic_vector(100 downto 1); |
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| 145 | priority_rotation : in STD_LOGIC_VECTOR (10 downto 1) |
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| 146 | ); |
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| 147 | END COMPONENT; |
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| 148 | |
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| 149 | COMPONENT Scheduler11_11 |
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| 150 | PORT( |
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| 151 | Request : IN std_logic_vector(121 downto 1); |
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| 152 | Fifo_full : IN std_logic_vector(11 downto 1); |
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| 153 | clk : IN std_logic; |
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| 154 | reset : IN std_logic; |
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| 155 | port_grant : OUT std_logic_vector(121 downto 1); |
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| 156 | priority_rotation : in STD_LOGIC_VECTOR (11 downto 1) |
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| 157 | ); |
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| 158 | END COMPONENT; |
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| 159 | |
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| 160 | COMPONENT Scheduler12_12 |
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| 161 | PORT( |
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| 162 | Request : IN std_logic_vector(144 downto 1); |
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| 163 | Fifo_full : IN std_logic_vector(12 downto 1); |
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| 164 | clk : IN std_logic; |
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| 165 | reset : IN std_logic; |
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| 166 | port_grant : OUT std_logic_vector(144 downto 1); |
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| 167 | priority_rotation : in STD_LOGIC_VECTOR (12 downto 1) |
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| 168 | ); |
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| 169 | END COMPONENT; |
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| 170 | |
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| 171 | COMPONENT Scheduler13_13 |
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| 172 | PORT( |
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| 173 | Request : IN std_logic_vector(169 downto 1); |
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| 174 | Fifo_full : IN std_logic_vector(13 downto 1); |
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| 175 | clk : IN std_logic; |
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| 176 | reset : IN std_logic; |
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| 177 | port_grant : OUT std_logic_vector(169 downto 1); |
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| 178 | priority_rotation : in STD_LOGIC_VECTOR (13 downto 1) |
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| 179 | ); |
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| 180 | END COMPONENT; |
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| 181 | |
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| 182 | COMPONENT Scheduler14_14 |
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| 183 | PORT( |
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| 184 | Request : IN std_logic_vector(196 downto 1); |
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| 185 | Fifo_full : IN std_logic_vector(14 downto 1); |
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| 186 | clk : IN std_logic; |
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| 187 | reset : IN std_logic; |
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| 188 | port_grant : OUT std_logic_vector(196 downto 1); |
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| 189 | priority_rotation : in STD_LOGIC_VECTOR (14 downto 1) |
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| 190 | ); |
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| 191 | END COMPONENT; |
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| 192 | |
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| 193 | COMPONENT Scheduler15_15 |
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| 194 | PORT( |
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| 195 | Request : IN std_logic_vector(225 downto 1); |
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| 196 | Fifo_full : IN std_logic_vector(15 downto 1); |
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| 197 | clk : IN std_logic; |
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| 198 | reset : IN std_logic; |
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| 199 | port_grant : OUT std_logic_vector(225 downto 1); |
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| 200 | priority_rotation : in STD_LOGIC_VECTOR (15 downto 1) |
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| 201 | ); |
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| 202 | END COMPONENT; |
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| 203 | |
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| 204 | COMPONENT Scheduler16_16 |
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| 205 | PORT( |
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| 206 | Request : IN std_logic_vector(256 downto 1); |
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| 207 | Fifo_full : IN std_logic_vector(16 downto 1); |
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| 208 | clk : IN std_logic; |
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| 209 | reset : IN std_logic; |
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| 210 | port_grant : OUT std_logic_vector(256 downto 1); |
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| 211 | priority_rotation : in STD_LOGIC_VECTOR (16 downto 1) |
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| 212 | ); |
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| 213 | END COMPONENT; |
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| 214 | |
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| 215 | |
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| 216 | -- instanciation des scheduler |
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| 217 | --======================scheduler 2 ports======================= |
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| 218 | |
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| 219 | begin |
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| 220 | |
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| 221 | -- instanciation des scheduler |
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| 222 | --======================scheduler 2 ports======================= |
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| 223 | |
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| 224 | scheduler2x2 : if number_of_ports = 2 generate |
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| 225 | |
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| 226 | Inst_Scheduler2_2 : Scheduler2_2 |
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| 227 | PORT MAP( |
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| 228 | Request => Request_latch, |
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| 229 | Fifo_full => Fifo_full_latch, |
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| 230 | clk => clk , |
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| 231 | reset =>reset, |
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| 232 | priority_rotation =>priority_rotation_latch, |
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| 233 | port_grant =>port_grant); |
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| 234 | end generate scheduler2x2; |
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| 235 | |
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| 236 | --======================scheduler 3 ports======================= |
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| 237 | |
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| 238 | scheduler3x3 : if number_of_ports = 3 generate |
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| 239 | |
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| 240 | Inst_Scheduler3_3 : Scheduler3_3 |
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| 241 | PORT MAP( |
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| 242 | Request => Request_latch, |
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| 243 | Fifo_full => Fifo_full_latch, |
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| 244 | clk => clk , |
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| 245 | reset =>reset, |
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| 246 | priority_rotation =>priority_rotation_latch, |
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| 247 | port_grant =>port_grant); |
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| 248 | end generate scheduler3x3; |
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| 249 | |
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| 250 | --======================scheduler 4 ports======================= |
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| 251 | |
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| 252 | scheduler4x4 : if number_of_ports = 4 generate |
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| 253 | |
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| 254 | Inst_Scheduler4_4 : Scheduler4_4 |
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| 255 | PORT MAP( |
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| 256 | Request => Request_latch, |
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| 257 | Fifo_full => Fifo_full_latch, |
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| 258 | clk => clk , |
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| 259 | reset =>reset, |
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| 260 | priority_rotation =>priority_rotation_latch, |
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| 261 | port_grant =>port_grant); |
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| 262 | end generate scheduler4x4; |
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| 263 | |
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| 264 | --======================scheduler 5 ports======================= |
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| 265 | |
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| 266 | scheduler5x5 : if number_of_ports = 5 generate |
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| 267 | |
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| 268 | Inst_Scheduler5_5 : Scheduler5_5 |
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| 269 | PORT MAP( |
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| 270 | Request => Request, |
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| 271 | Fifo_full => Fifo_full, |
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| 272 | clk => clk , |
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| 273 | reset =>reset, |
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| 274 | priority_rotation =>priority_rotation, |
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| 275 | port_grant =>port_grant); |
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| 276 | end generate scheduler5x5; |
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| 277 | |
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| 278 | --======================scheduler 6 ports======================= |
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| 279 | |
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| 280 | scheduler6x6 : if number_of_ports = 6 generate |
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| 281 | |
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| 282 | Inst_Scheduler6_6 : Scheduler6_6 |
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| 283 | PORT MAP( |
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| 284 | Request => Request_latch, |
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| 285 | Fifo_full => Fifo_full_latch, |
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| 286 | clk => clk , |
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| 287 | reset =>reset, |
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| 288 | priority_rotation =>priority_rotation_latch, |
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| 289 | port_grant =>port_grant); |
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| 290 | end generate scheduler6x6; |
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| 291 | |
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| 292 | --======================scheduler 7 ports======================= |
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| 293 | |
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| 294 | scheduler7x7 : if number_of_ports = 7 generate |
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| 295 | |
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| 296 | Inst_Scheduler7_7 : Scheduler7_7 |
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| 297 | PORT MAP( |
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| 298 | Request => Request_latch, |
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| 299 | Fifo_full => Fifo_full_latch, |
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| 300 | clk => clk , |
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| 301 | reset =>reset, |
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| 302 | priority_rotation =>priority_rotation_latch, |
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| 303 | port_grant =>port_grant); |
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| 304 | end generate scheduler7x7; |
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| 305 | |
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| 306 | --======================scheduler 8 ports======================= |
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| 307 | |
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| 308 | scheduler8x8 : if number_of_ports = 8 generate |
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| 309 | |
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| 310 | Inst_Scheduler8_8 : Scheduler8_8 |
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| 311 | PORT MAP( |
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| 312 | Req => Request_latch, |
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| 313 | Fifo_full => Fifo_full_latch, |
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| 314 | clk => clk , |
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| 315 | reset =>reset, |
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| 316 | priority_rotation =>priority_rotation_latch, |
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| 317 | port_grant =>port_grant); |
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| 318 | end generate scheduler8x8; |
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| 319 | |
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| 320 | --======================scheduler 9 ports======================= |
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| 321 | |
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| 322 | scheduler9x9 : if number_of_ports = 9 generate |
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| 323 | |
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| 324 | Inst_Scheduler9_9 : Scheduler9_9 |
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| 325 | PORT MAP( |
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| 326 | Request => Request_latch, |
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| 327 | Fifo_full => Fifo_full_latch, |
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| 328 | clk => clk , |
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| 329 | reset =>reset, |
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| 330 | priority_rotation =>priority_rotation_latch, |
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| 331 | port_grant =>port_grant); |
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| 332 | end generate scheduler9x9; |
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| 333 | |
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| 334 | --======================scheduler 10 ports======================= |
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| 335 | |
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| 336 | scheduler10x10 : if number_of_ports = 10 generate |
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| 337 | |
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| 338 | Inst_Scheduler10_10 : Scheduler10_10 |
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| 339 | PORT MAP( |
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| 340 | Request => Request, |
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| 341 | Fifo_full => Fifo_full, |
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| 342 | clk => clk , |
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| 343 | reset =>reset, |
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| 344 | priority_rotation =>priority_rotation, |
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| 345 | port_grant =>port_grant); |
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| 346 | end generate scheduler10x10; |
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| 347 | |
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| 348 | --======================scheduler 11 ports======================= |
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| 349 | |
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| 350 | scheduler11x11 : if number_of_ports = 11 generate |
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| 351 | |
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| 352 | Inst_Scheduler11_11 : Scheduler11_11 |
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| 353 | PORT MAP( |
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| 354 | Request => Request, |
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| 355 | Fifo_full => Fifo_full, |
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| 356 | clk => clk , |
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| 357 | reset =>reset, |
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| 358 | priority_rotation =>priority_rotation, |
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| 359 | port_grant =>port_grant); |
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| 360 | end generate scheduler11x11; |
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| 361 | |
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| 362 | --======================scheduler 12 ports======================= |
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| 363 | |
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| 364 | scheduler12x12 : if number_of_ports = 12 generate |
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| 365 | |
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| 366 | Inst_Scheduler12_12 : Scheduler12_12 |
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| 367 | PORT MAP( |
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| 368 | Request => Request_latch, |
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| 369 | Fifo_full => Fifo_full_latch, |
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| 370 | clk => clk , |
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| 371 | reset =>reset, |
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| 372 | priority_rotation =>priority_rotation_latch, |
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| 373 | port_grant =>port_grant); |
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| 374 | end generate scheduler12x12; |
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| 375 | |
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| 376 | --======================scheduler 13 ports======================= |
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| 377 | |
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| 378 | scheduler13x13 : if number_of_ports = 13 generate |
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| 379 | |
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| 380 | Inst_Scheduler13_13 : Scheduler13_13 |
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| 381 | PORT MAP( |
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| 382 | Request => Request_latch, |
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| 383 | Fifo_full => Fifo_full_latch, |
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| 384 | clk => clk , |
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| 385 | reset =>reset, |
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| 386 | priority_rotation =>priority_rotation_latch, |
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| 387 | port_grant =>port_grant); |
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| 388 | end generate scheduler13x13; |
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| 389 | |
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| 390 | --======================scheduler 14 ports======================= |
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| 391 | |
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| 392 | scheduler14x14 : if number_of_ports = 14 generate |
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| 393 | |
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| 394 | Inst_Scheduler14_14 : Scheduler14_14 |
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| 395 | PORT MAP( |
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| 396 | Request => Request_latch, |
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| 397 | Fifo_full => Fifo_full_latch, |
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| 398 | clk => clk , |
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| 399 | reset =>reset, |
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| 400 | priority_rotation =>priority_rotation_latch, |
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| 401 | port_grant =>port_grant); |
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| 402 | end generate scheduler14x14; |
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| 403 | |
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| 404 | --======================scheduler 15 ports======================= |
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| 405 | |
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| 406 | scheduler15x15 : if number_of_ports = 15 generate |
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| 407 | |
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| 408 | Inst_Scheduler15_15 : Scheduler15_15 |
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| 409 | PORT MAP( |
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| 410 | Request => Request_latch, |
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| 411 | Fifo_full => Fifo_full_latch, |
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| 412 | clk => clk , |
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| 413 | reset =>reset, |
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| 414 | priority_rotation =>priority_rotation_latch, |
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| 415 | port_grant =>port_grant); |
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| 416 | end generate scheduler15x15; |
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| 417 | |
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| 418 | --======================scheduler 16 ports======================= |
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| 419 | |
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| 420 | scheduler16x16 : if number_of_ports = 16 generate |
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| 421 | |
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| 422 | Inst_Scheduler16_16 : Scheduler16_16 |
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| 423 | PORT MAP( |
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| 424 | Request => Request_latch, |
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| 425 | Fifo_full => Fifo_full_latch, |
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| 426 | clk => clk , |
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| 427 | reset =>reset, |
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| 428 | priority_rotation =>priority_rotation_latch, |
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| 429 | port_grant =>port_grant); |
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| 430 | end generate scheduler16x16; |
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| 431 | Sched:process (clk,reset) |
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| 432 | begin |
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| 433 | if rising_edge(clk) then |
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| 434 | if reset='1' then |
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| 435 | request_latch<=(others=>'0'); |
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| 436 | --Fifo_full_latch<=(others=>'0'); |
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| 437 | priority_rotation_latch<=(others=>'1'); |
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| 438 | else |
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| 439 | request_latch<=request; |
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| 440 | -- Fifo_full_latch<=fifo_full; |
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| 441 | priority_rotation_latch<=priority_rotation; |
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| 442 | end if; |
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| 443 | end if; |
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| 444 | end process sched; |
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| 445 | Fifo_full_latch<=fifo_full; |
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| 446 | end Behavioral; |
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| 447 | |
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