[143] | 1 | -------------------------------------------------------------------------------- |
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| 2 | -- Company: |
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| 3 | -- Engineer: GAMOM NGOUNOU |
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| 4 | -- |
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| 5 | -- Create Date: 19:03:05 07/11/2011 |
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| 6 | -- Design Name: |
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| 7 | -- Module Name: C:/Xilinx/SWITCH_GENERIC_16_16/test_xbar_8x8.vhd |
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| 8 | -- Project Name: GENERIC_16_16 |
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| 9 | -- Target Device: |
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| 10 | -- Tool versions: |
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| 11 | -- Description: |
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| 12 | -- |
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| 13 | -- VHDL Test Bench Created by ISE for module: SWITCH_GENERIQUE |
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| 14 | -- |
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| 15 | -- Dependencies: |
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| 16 | -- |
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| 17 | -- Revision: |
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| 18 | -- Revision 0.01 - File Created |
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| 19 | -- Additional Comments: |
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| 20 | -- |
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| 21 | -- Notes: |
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| 22 | -- This testbench has been automatically generated using types std_logic and |
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| 23 | -- std_logic_vector for the ports of the unit under test. Xilinx recommends |
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| 24 | -- that these types always be used for the top-level I/O of a design in order |
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| 25 | -- to guarantee that the testbench will bind correctly to the post-implementation |
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| 26 | -- simulation model. |
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| 27 | -------------------------------------------------------------------------------- |
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| 28 | LIBRARY ieee; |
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| 29 | USE ieee.std_logic_1164.ALL; |
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| 30 | --use IEEE.std_logic_textio.ALL; |
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| 31 | -- Uncomment the following library declaration if using |
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| 32 | -- arithmetic functions with Signed or Unsigned values |
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| 33 | USE ieee.numeric_std.ALL; |
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| 34 | use work.Coretypes.all; |
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| 35 | |
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| 36 | |
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| 37 | ENTITY test_xbar_8x8 IS |
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| 38 | END test_xbar_8x8; |
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| 39 | |
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| 40 | ARCHITECTURE behavior OF test_xbar_8x8 IS |
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| 41 | CONSTANT MAXPORT :natural:=8; |
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| 42 | -- Component Declaration for the Unit Under Test (UUT) |
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| 43 | |
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| 44 | COMPONENT SWITCH_GEN |
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| 45 | GENERIC (number_of_ports : positive := MAXPORT); |
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| 46 | PORT( |
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| 47 | clk : IN std_logic; |
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| 48 | reset : IN std_logic; |
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| 49 | |
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| 50 | Port_in : in typ_portIO(1 to MAXPORT) ; |
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| 51 | Port_out : out typ_portIO(1 to MAXPORT); |
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| 52 | |
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| 53 | cmd_in_en : IN std_logic_vector(MAXPORT downto 1); |
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| 54 | data_in_en : IN std_logic_vector(MAXPORT downto 1); |
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| 55 | data_out_en : IN std_logic_vector(MAXPORT downto 1); |
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| 56 | fifo_in_full : OUT std_logic_vector(MAXPORT downto 1); |
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| 57 | fifo_in_empty : OUT std_logic_vector(MAXPORT downto 1); |
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| 58 | data_available : OUT std_logic_vector(MAXPORT downto 1) |
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| 59 | |
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| 60 | ); |
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| 61 | END COMPONENT; |
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| 62 | COMPONENT Stimport5 |
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| 63 | port ( |
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| 64 | clk : in std_logic; |
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| 65 | reset : in std_logic; |
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| 66 | clk_en : in std_logic; |
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| 67 | wr_en : out std_logic; |
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| 68 | data : out std_logic_vector (7 downto 0) |
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| 69 | ); |
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| 70 | |
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| 71 | END COMPONENT; |
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| 72 | type naturel is array (natural range <>) of natural range 0 to 511; |
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| 73 | type typ_send is (s_head,s_len,s_len2,s_data,s_end); |
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| 74 | type typ_receiv is (r_wait,r_head,r_dlen,r_glen,r_start,r_end); |
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| 75 | type typ_cmd is (cmdstart,cmdpost,cmdpostidle,cmdread,cmdlen,cmdglen,cmddata,cmdend,cmdtimeout); |
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| 76 | |
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| 77 | signal etsnd1,etsnd2,etsnd3 : typ_send; |
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| 78 | signal etrec:typ_receiv; --pour la machine à état de réception |
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| 79 | signal etcmd :typ_cmd; --pour la machine à état de commande |
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| 80 | --Inputs |
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| 81 | signal PortIn : Typ_portio (1 to MAXPORT); |
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| 82 | --Outputs |
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| 83 | signal portOut : Typ_portio(1 to maxport); |
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| 84 | |
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| 85 | signal data_in_en : std_logic_vector(MAXPORT downto 1) := (others => '0'); |
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| 86 | signal cmd_in_en : std_logic_vector(MAXPORT downto 1) := (others => '0'); |
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| 87 | signal data_out_en : std_logic_vector(MAXPORT downto 1) := (others => '0'); |
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| 88 | signal rdata_out_en : std_logic_vector(MAXPORT downto 1) := (others => '0'); |
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| 89 | signal rcount : naturel(1 to MAXPORT) ; |
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| 90 | |
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| 91 | signal cdata_out_en : std_logic_vector(MAXPORT downto 1) := (others => '0'); |
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| 92 | signal clk : std_logic := '0'; |
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| 93 | signal reset : std_logic := '0'; |
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| 94 | signal din1,din2,din3,din4: std_logic_vector(MAXPORT downto 1):= (others => '0'); |
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| 95 | --signaux utiliser pour la mise à jour des MAE |
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| 96 | signal sdestport,rdestport,rorigport:natural range 0 to 15; |
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| 97 | signal csend1,csend2,csend3,csend4:natural; |
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| 98 | signal sorigport :natural range 0 to 15:=1; |
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| 99 | |
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| 100 | |
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| 101 | signal fifo_in_full : std_logic_vector(MAXPORT downto 1); |
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| 102 | signal fifo_in_empty : std_logic_vector(MAXPORT downto 1); |
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| 103 | signal data_available : std_logic_vector(MAXPORT downto 1); |
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| 104 | |
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| 105 | -- Clock period definitions |
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| 106 | constant clk_period : time := 10 ns; |
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| 107 | -- autres signaux de simulation |
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| 108 | -- ici nous mettons les signaux permettant de gérer le processus de simulation |
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| 109 | signal time_out:std_logic_vector(8 downto 1); |
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| 110 | signal header : std_logic_vector(7 downto 0); |
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| 111 | signal tosend1,tosend2,tosend3,tosend4 : std_logic_vector(7 downto 0); |
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| 112 | |
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| 113 | BEGIN |
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| 114 | |
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| 115 | -- Instantiate the Unit Under Test (UUT) |
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| 116 | uut: SWITCH_GEN generic map (MAXPORT) PORT MAP ( |
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| 117 | Port_In => PortIn, |
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| 118 | Port_Out =>PortOut, |
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| 119 | |
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| 120 | --signaux de contrôle de la lecture des ports |
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| 121 | data_in_en => data_in_en, |
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| 122 | cmd_in_en =>cmd_in_en, |
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| 123 | data_out_en => data_out_en, |
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| 124 | fifo_in_full => fifo_in_full, |
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| 125 | fifo_in_empty => fifo_in_empty, |
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| 126 | data_available => data_available, |
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| 127 | clk => clk, |
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| 128 | reset => reset |
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| 129 | ); |
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| 130 | --Utilisation de la ROM pour envoyer des stimulis |
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| 131 | --stimport: stimport5 port map (clk,reset,not (fifo_in_full(5)),din3(5),port5_in); |
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| 132 | data_in_en<=din1 or din2 or din3 or din4; |
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| 133 | data_out_en<=rdata_out_en or cdata_out_en; |
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| 134 | -- Clock process definitions |
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| 135 | clk_process :process |
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| 136 | begin |
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| 137 | clk <= '0'; |
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| 138 | wait for clk_period/2; |
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| 139 | clk <= '1'; |
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| 140 | wait for clk_period/2; |
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| 141 | end process; |
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| 142 | |
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| 143 | init_process:process (reset) |
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| 144 | |
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| 145 | variable i: natural range 0 to 15; |
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| 146 | begin |
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| 147 | if reset='1' then |
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| 148 | for i in 1 to maxport |
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| 149 | loop |
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| 150 | --Portin(i)<=(others=>'0'); |
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| 151 | end loop ; |
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| 152 | end if ; |
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| 153 | end process init_process; |
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| 154 | psend1:process(clk,reset) |
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| 155 | --génération des paquets à partir du premier port |
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| 156 | variable pactype :natural range 0 to 15; |
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| 157 | variable origport,destport : natural range 0 to 15; |
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| 158 | variable datalen,i,i_pair : natural range 0 to 255; |
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| 159 | |
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| 160 | |
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| 161 | |
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| 162 | begin |
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| 163 | if reset='1' then |
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| 164 | etsnd1<=s_head; |
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| 165 | |
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| 166 | else --reset ='0' |
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| 167 | origport:=6; |
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| 168 | if rising_edge(clk) then -- le process s'exécute sur chaque front |
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| 169 | -- montant de l'horloge |
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| 170 | case etsnd1 is |
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| 171 | when s_head => -- construction et envoie de l'en-tête |
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| 172 | pactype:=5;-- fonction put |
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| 173 | destport:=6; -- le port de destination |
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| 174 | datalen :=4; |
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| 175 | header<=STD_LOGIC_VECTOR(to_unsigned(pactype,4)) & STD_LOGIC_VECTOR(to_unsigned(destport,4)); |
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| 176 | tosend1<=STD_LOGIC_VECTOR(to_unsigned(pactype,4)) & STD_LOGIC_VECTOR(to_unsigned(destport-1,4)); |
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| 177 | din1(origport)<='1'; -- en fait data_in_en(origport) |
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| 178 | i:=1;i_pair:=i /2; |
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| 179 | etsnd1<=s_len; -- passer à l'état suivant |
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| 180 | --port1_in<=tosend1; |
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| 181 | when s_len => |
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| 182 | --tosend1<=(STD_LOGIC_VECTOR(to_unsigned(datalen+2,8))); |
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| 183 | tosend1<=STD_LOGIC_VECTOR(to_unsigned(pactype,4)) & STD_LOGIC_VECTOR(to_unsigned(destport-1,4)); |
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| 184 | |
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| 185 | din1(origport)<='1'; |
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| 186 | |
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| 187 | --port1_in<=tosend1; --copie directe sur le port |
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| 188 | etsnd1<=s_len2; |
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| 189 | when s_len2 => |
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| 190 | tosend1<=(STD_LOGIC_VECTOR(to_unsigned(datalen+2,8))); |
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| 191 | din1(origport)<='1'; |
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| 192 | |
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| 193 | --port1_in<=tosend1; --copie directe sur le port |
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| 194 | etsnd1<=s_data; |
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| 195 | when s_data => |
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| 196 | |
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| 197 | if (fifo_in_full(origport)='0') then |
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| 198 | din1(origport)<='1'; |
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| 199 | i_pair:=i_pair *2; |
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| 200 | if i=i_pair then -- modulo |
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| 201 | tosend1<=(STD_LOGIC_VECTOR(to_unsigned(i,8))); |
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| 202 | --port1_in<="00001101"; --origport=1 |
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| 203 | else |
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| 204 | --tosend1<="00001111"; |
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| 205 | tosend1<=(STD_LOGIC_VECTOR(to_unsigned(i,8))); |
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| 206 | --port1_in<="00001111"; --origport=1 |
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| 207 | end if; |
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| 208 | i:=i+1;i_pair:=i / 2; |
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| 209 | if i>datalen then |
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| 210 | etsnd1<=s_end; |
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| 211 | din1(origport)<='0'; |
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| 212 | end if; |
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| 213 | else |
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| 214 | din1(origport)<='1'; |
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| 215 | end if; |
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| 216 | when s_end => |
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| 217 | tosend1<="--------"; |
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| 218 | din1(origport)<='0'; |
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| 219 | if fifo_in_empty(origport)='1' then |
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| 220 | etsnd1<=s_head; |
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| 221 | else |
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| 222 | etsnd1<=s_end; |
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| 223 | end if; |
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| 224 | end case; |
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| 225 | |
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| 226 | end if; |
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| 227 | |
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| 228 | |
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| 229 | |
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| 230 | end if; --reset='1' |
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| 231 | end process psend1; |
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| 232 | |
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| 233 | Portin(6)<=tosend1 when reset='0'; |
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| 234 | Portin(2)<=tosend2 when reset='0'; |
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| 235 | Portin(4)<=tosend3 when reset='0'; |
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| 236 | Portin(1)<=tosend4 when reset='0'; |
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| 237 | psend2:process(clk,reset) |
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| 238 | --génération des paquets à partir du premier port |
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| 239 | variable pactype :natural range 0 to 15; |
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| 240 | variable origport,destport : natural range 0 to 15; |
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| 241 | variable datalen,i,i_pair : natural range 0 to 255; |
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| 242 | |
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| 243 | |
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| 244 | |
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| 245 | begin |
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| 246 | if reset='1' then |
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| 247 | etsnd2<=s_head; |
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| 248 | |
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| 249 | else --reset ='0' |
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| 250 | origport:=2; |
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| 251 | if rising_edge(clk) then -- le process s'exécute sur chaque front |
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| 252 | -- montant de l'horloge |
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| 253 | case etsnd2 is |
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| 254 | when s_head => -- construction et envoie de l'en-tête |
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| 255 | pactype:=5;-- fonction put |
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| 256 | destport:=2; -- le port de destination |
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| 257 | datalen :=9; |
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| 258 | header<=STD_LOGIC_VECTOR(to_unsigned(pactype,4)) & STD_LOGIC_VECTOR(to_unsigned(destport,4)); |
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| 259 | tosend2<=STD_LOGIC_VECTOR(to_unsigned(pactype,4)) & STD_LOGIC_VECTOR(to_unsigned(destport-1,4)); |
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| 260 | din2(origport)<='1'; |
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| 261 | i:=1;i_pair:=i /2; |
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| 262 | etsnd2<=s_len; -- passer à l'état suivant |
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| 263 | |
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| 264 | when s_len => |
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| 265 | --tosend2<=(STD_LOGIC_VECTOR(to_unsigned(datalen+2,8))); |
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| 266 | tosend2<=STD_LOGIC_VECTOR(to_unsigned(pactype,4)) & STD_LOGIC_VECTOR(to_unsigned(destport-1,4)); |
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| 267 | |
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| 268 | din2(origport)<='1'; |
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| 269 | |
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| 270 | --port2_in<=tosend2; --copie directe sur le port |
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| 271 | etsnd2<=s_len2; |
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| 272 | when s_len2 => |
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| 273 | tosend2<=(STD_LOGIC_VECTOR(to_unsigned(datalen+2,8))); |
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| 274 | din2(origport)<='1'; |
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| 275 | |
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| 276 | --port1_in<=tosend1; --copie directe sur le port |
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| 277 | etsnd2<=s_data; |
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| 278 | when s_data => |
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| 279 | |
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| 280 | if (fifo_in_full(origport)='0') then |
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| 281 | din2(origport)<='1'; |
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| 282 | i_pair:=i_pair * 2; |
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| 283 | if i=i_pair then -- modulo |
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| 284 | --tosend2<="00000001"; |
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| 285 | tosend2<=(STD_LOGIC_VECTOR(to_unsigned(i,8))); |
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| 286 | --port2_in<="00000001"; --origport=1 |
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| 287 | else |
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| 288 | --tosend2<="00000010"; |
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| 289 | tosend2<=(STD_LOGIC_VECTOR(to_unsigned(i,8))); |
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| 290 | --port2_in<="00000001"; --origport=1 |
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| 291 | end if; |
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| 292 | i:=i+1;i_pair:=i / 2; |
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| 293 | if i>datalen then |
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| 294 | etsnd2<=s_end; |
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| 295 | din2(origport)<='0'; |
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| 296 | else |
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| 297 | din2(origport)<='1'; |
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| 298 | end if; |
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| 299 | else |
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| 300 | din2(origport)<='0'; |
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| 301 | end if; |
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| 302 | when s_end => |
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| 303 | tosend2<="--------"; |
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| 304 | din2(origport)<='0'; |
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| 305 | if fifo_in_empty(origport)='1' then |
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| 306 | etsnd2<=s_head; |
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| 307 | else |
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| 308 | etsnd2<=s_end; |
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| 309 | end if; |
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| 310 | end case; |
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| 311 | |
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| 312 | end if; |
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| 313 | |
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| 314 | |
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| 315 | |
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| 316 | end if; --reset='1' |
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| 317 | end process psend2; |
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| 318 | |
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| 319 | psend3:process(clk,reset) |
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| 320 | --génération des paquets à partir du premier port |
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| 321 | variable pactype :natural range 0 to 15; |
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| 322 | variable origport,destport : natural range 0 to 15; |
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| 323 | variable datalen,i,i_pair : natural range 0 to 255; |
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| 324 | |
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| 325 | |
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| 326 | |
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| 327 | begin |
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| 328 | if reset='1' then |
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| 329 | etsnd3<=s_head; |
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| 330 | |
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| 331 | else --reset ='0' |
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| 332 | origport:=4; --attention à régler tosend3 =Portin(....) !!!!!!! |
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| 333 | if rising_edge(clk) then -- le process s'exécute sur chaque front |
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| 334 | -- montant de l'horloge |
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| 335 | case etsnd3 is |
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| 336 | when s_head => -- construction et envoie de l'en-tête |
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| 337 | pactype:=5;-- fonction put |
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| 338 | destport:=MAXPORT; -- le port de destination |
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| 339 | datalen :=4; |
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| 340 | --header<=STD_LOGIC_VECTOR(to_unsigned(pactype,4)) & STD_LOGIC_VECTOR(to_unsigned(destport,4)); |
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| 341 | tosend3<=STD_LOGIC_VECTOR(to_unsigned(pactype,4)) & STD_LOGIC_VECTOR(to_unsigned(destport-1,4)); |
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| 342 | din3(origport)<='1'; -- en fait data_in_en(origport) |
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| 343 | i:=1;i_pair:=i /2; |
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| 344 | etsnd3<=s_len; -- passer à l'état suivant |
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| 345 | --port1_in<=tosend1; |
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| 346 | when s_len => |
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| 347 | --tosend3<=(STD_LOGIC_VECTOR(to_unsigned(datalen+2,8))); |
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| 348 | din3(origport)<='1'; |
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| 349 | tosend3<=STD_LOGIC_VECTOR(to_unsigned(pactype,4)) & STD_LOGIC_VECTOR(to_unsigned(destport-1,4)); |
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| 350 | |
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| 351 | --port1_in<=tosend1; --copie directe sur le port |
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| 352 | etsnd3<=s_len2; |
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| 353 | when s_len2 => |
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| 354 | tosend3<=(STD_LOGIC_VECTOR(to_unsigned(datalen+2,8))); |
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| 355 | din3(origport)<='1'; |
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| 356 | |
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| 357 | --port1_in<=tosend1; --copie directe sur le port |
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| 358 | etsnd3<=s_data; |
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| 359 | when s_data => |
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| 360 | |
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| 361 | if (fifo_in_full(origport)='0') then |
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| 362 | din3(origport)<='1'; |
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| 363 | i_pair:=i_pair * 2; |
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| 364 | if i=i_pair then -- modulo |
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| 365 | tosend3<=(STD_LOGIC_VECTOR(to_unsigned(i,8))); |
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| 366 | --tosend3<="00001100"; |
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| 367 | --port1_in<="00001101"; --origport=1 |
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| 368 | else |
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| 369 | tosend3<=(STD_LOGIC_VECTOR(to_unsigned(i,8))); |
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| 370 | --tosend3<="00000110"; |
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| 371 | --port1_in<="00001111"; --origport=1 |
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| 372 | end if; |
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| 373 | i:=i+1;i_pair:=i / 2; |
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| 374 | if i>datalen then |
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| 375 | din3(origport)<='0'; |
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| 376 | etsnd3<=s_end; |
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| 377 | else |
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| 378 | din3(origport)<='1'; |
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| 379 | end if; |
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| 380 | else |
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| 381 | din3(origport)<='0'; |
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| 382 | end if; |
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| 383 | when s_end => |
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| 384 | tosend3<="--------"; |
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| 385 | din3(origport)<='0'; |
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| 386 | if fifo_in_empty(origport)='1' then |
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| 387 | etsnd3<=s_head; |
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| 388 | else |
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| 389 | etsnd3<=s_end; |
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| 390 | end if; |
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| 391 | end case; |
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| 392 | |
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| 393 | end if; |
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| 394 | |
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| 395 | end if; --reset='1' |
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| 396 | end process psend3; |
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| 397 | |
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| 398 | preceiv:process(clk,reset) |
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| 399 | |
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| 400 | variable origport,ptype : natural range 0 to 15; |
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| 401 | variable datalen,dcount ,timeout:natural range 0 to 255; |
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| 402 | variable destport : natural range 0 to 15:=1; |
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| 403 | begin |
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| 404 | |
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| 405 | if reset='1' then |
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| 406 | etrec<=r_wait; |
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| 407 | destport:=1; |
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| 408 | timeout:=0; |
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| 409 | elsif rising_edge(clk) then |
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| 410 | case etrec is |
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| 411 | when r_wait => |
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| 412 | if destport=0 then |
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| 413 | destport:=1; |
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| 414 | end if; |
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| 415 | timeout:=0; |
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| 416 | time_out(destport)<='0'; |
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| 417 | if data_available(destport)='1' and cmd_in_en(destport)='0' then |
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| 418 | rdata_out_en(destport)<='1'; |
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| 419 | etrec<=r_head; |
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| 420 | else |
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| 421 | if destport>=MAXPORT then |
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| 422 | destport:=1; |
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| 423 | else |
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| 424 | destport:=destport+1; |
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| 425 | end if; |
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| 426 | etrec<=r_wait; |
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| 427 | end if; |
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| 428 | when r_head => |
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| 429 | |
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| 430 | ptype:=to_integer(unsigned(portout(destport)(7 downto 4))); |
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| 431 | origport:=to_integer(unsigned(portout(destport)(3 downto 0))); |
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| 432 | rdata_out_en(destport)<='1'; |
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| 433 | if ptype=5 then -- |
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| 434 | etrec<=r_Dlen;--identification de la signature d'en tête valide |
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| 435 | else |
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| 436 | etrec<=r_wait; |
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| 437 | end if; |
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| 438 | |
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| 439 | |
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| 440 | |
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| 441 | |
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| 442 | |
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| 443 | when r_Dlen => --positionnement du mot de longueur des données |
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| 444 | if data_available(destport)='1' then |
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| 445 | |
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| 446 | rdata_out_en(destport)<='1'; |
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| 447 | etrec<=r_glen; |
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| 448 | timeout:=0; |
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| 449 | else |
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| 450 | timeout:=timeout+1; |
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| 451 | if timeout>=30 then |
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| 452 | time_out(destport)<='1'; |
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| 453 | etrec<=r_end; -- données pas prêtes |
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| 454 | end if; |
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| 455 | |
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| 456 | |
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| 457 | end if; |
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| 458 | when r_glen => --lecture effective de la longueur des données |
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| 459 | if data_available(destport)='1' then |
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| 460 | datalen:=to_integer(unsigned(portout(destport)(7 downto 0)))-3; |
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| 461 | rdata_out_en(destport)<='1'; |
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| 462 | etrec<=r_start; |
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| 463 | dcount:=1; -- initialisation du compteur de reception |
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| 464 | else |
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| 465 | timeout:=timeout+1; |
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| 466 | if timeout>=30 then |
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| 467 | time_out(destport)<='1'; |
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| 468 | etrec<=r_end; -- données pas prêtes |
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| 469 | end if; |
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| 470 | |
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| 471 | end if; |
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| 472 | |
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| 473 | when r_start => |
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| 474 | if data_available(destport)='1' then |
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| 475 | |
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| 476 | dcount:=dcount+1; |
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| 477 | assert true report "Donnée lue :"; --& string(unsigned(port4_out(7 downto 0))) |
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| 478 | rdata_out_en(destport)<='1'; |
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| 479 | |
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| 480 | --severity note; |
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| 481 | if datalen<=dcount then |
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| 482 | etrec<=r_end; |
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| 483 | |
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| 484 | elsif dcount=255 then --dépassement de la capacité |
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| 485 | etrec<=r_end; |
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| 486 | end if; |
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| 487 | else |
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| 488 | timeout:=timeout+1; |
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| 489 | if timeout>=30 then |
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| 490 | time_out(destport)<='1'; |
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| 491 | etrec<=r_end; -- données pas prêtes |
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| 492 | end if; |
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| 493 | |
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| 494 | |
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| 495 | end if; |
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| 496 | when r_end => |
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| 497 | |
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| 498 | |
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| 499 | rdata_out_en(destport)<='0'; |
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| 500 | rcount(destport)<=rcount(destport)+1; |
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| 501 | etrec<=r_wait; |
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| 502 | if destport>=MAXPORT then -- provoquer le passage au prochain port de réception |
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| 503 | destport:=1; |
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| 504 | else |
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| 505 | destport:=destport+1; |
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| 506 | end if; |
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| 507 | end case; |
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| 508 | end if; --reset='1' |
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| 509 | end process preceiv; |
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| 510 | |
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| 511 | pcmd:process(clk,reset) |
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| 512 | |
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| 513 | variable origport,destport,pid,mport : natural range 0 to 15; |
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| 514 | variable datalen,dcount ,timeout:natural range 0 to 255; |
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| 515 | begin |
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| 516 | |
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| 517 | if reset='1' then |
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| 518 | etcmd<=cmdstart; |
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| 519 | destport:=0; |
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| 520 | timeout:=0; |
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| 521 | origport:=1; |
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| 522 | sorigport<=origport; |
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| 523 | elsif rising_edge(clk) then |
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| 524 | case etcmd is |
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| 525 | when cmdstart => |
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| 526 | if fifo_in_empty(origport)='1' then |
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| 527 | |
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| 528 | |
---|
| 529 | |
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| 530 | |
---|
| 531 | etcmd<=cmdpost; |
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| 532 | end if; |
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| 533 | when cmdpost => |
---|
| 534 | if fifo_in_empty(origport)='1' then |
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| 535 | ---assignations de l'état |
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| 536 | --din4(origport)<='1'; |
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| 537 | --tosend4<="00000001"; ---code pour getportid |
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| 538 | etcmd<=cmdpostidle; |
---|
| 539 | end if; |
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| 540 | when cmdpostidle => --permet juste la prise en compte de la commande |
---|
| 541 | if data_available(origport)='1' then |
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| 542 | etcmd<=cmdread; |
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| 543 | end if; |
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| 544 | when cmdread => |
---|
| 545 | |
---|
| 546 | |
---|
| 547 | timeout:=0; |
---|
| 548 | --time_out(destport)<='0'; |
---|
| 549 | if data_available(origport)='1' then |
---|
| 550 | mport:=to_integer(unsigned(portout(origport)(7 downto 4))); |
---|
| 551 | pid:=to_integer(unsigned(portout(origport)(3 downto 0)))+1; |
---|
| 552 | --cdata_out_en(origport)<='1'; |
---|
| 553 | if pid=origport then --le port a été bien identifié |
---|
| 554 | etcmd<=cmdglen; -- |
---|
| 555 | else |
---|
| 556 | etcmd<=cmdtimeout; |
---|
| 557 | end if; |
---|
| 558 | else |
---|
| 559 | -- if destport>=MAXPORT then |
---|
| 560 | -- destport:=1; |
---|
| 561 | -- else |
---|
| 562 | -- destport:=destport+1; |
---|
| 563 | -- end if; |
---|
| 564 | etcmd<=cmdread; |
---|
| 565 | end if; |
---|
| 566 | |
---|
| 567 | |
---|
| 568 | when cmdlen => --positionnement du mot de longueur des données |
---|
| 569 | if data_available(origport)='1' then |
---|
| 570 | |
---|
| 571 | --cdata_out_en(origport)<='1'; |
---|
| 572 | etcmd<=cmdglen; |
---|
| 573 | timeout:=0; |
---|
| 574 | else |
---|
| 575 | timeout:=timeout+1; |
---|
| 576 | if timeout>=30 then |
---|
| 577 | --time_out(destport)<='1'; |
---|
| 578 | etcmd<=cmdtimeout; -- données pas prêtes |
---|
| 579 | end if; |
---|
| 580 | |
---|
| 581 | |
---|
| 582 | end if; |
---|
| 583 | when cmdglen => --lecture effective de la longueur des données |
---|
| 584 | if data_available(origport)='1' then |
---|
| 585 | datalen:=to_integer(unsigned(portout(origport)(7 downto 0)))-3; |
---|
| 586 | |
---|
| 587 | etcmd<=cmddata; |
---|
| 588 | dcount:=0; -- initialisation du compteur de reception |
---|
| 589 | else |
---|
| 590 | timeout:=timeout+1; |
---|
| 591 | if timeout>=30 then |
---|
| 592 | --time_out(destport)<='1'; |
---|
| 593 | etcmd<=cmdtimeout; -- données pas prêtes |
---|
| 594 | end if; |
---|
| 595 | |
---|
| 596 | end if; |
---|
| 597 | |
---|
| 598 | when cmddata => |
---|
| 599 | if data_available(origport)='1' and timeout<30 then |
---|
| 600 | |
---|
| 601 | --cdata_out_en(origport)<='1'; |
---|
| 602 | mport:=to_integer(unsigned(portout(origport)(7 downto 4))); |
---|
| 603 | --attention les ports sont numérotés à partir de 0 |
---|
| 604 | pid:=to_integer(unsigned(portout(origport)(3 downto 0)))+1; |
---|
| 605 | |
---|
| 606 | --severity note; |
---|
| 607 | if Pid=origport then |
---|
| 608 | etcmd<=cmdend; |
---|
| 609 | |
---|
| 610 | else --dépassement de la capacité |
---|
| 611 | |
---|
| 612 | timeout:=timeout+1; |
---|
| 613 | if timeout>=30 then |
---|
| 614 | etcmd<=cmdtimeout; |
---|
| 615 | end if; |
---|
| 616 | |
---|
| 617 | end if; |
---|
| 618 | else |
---|
| 619 | |
---|
| 620 | if timeout>=30 then |
---|
| 621 | time_out(origport)<='1'; |
---|
| 622 | etcmd<=cmdtimeout; -- données pas prêtes |
---|
| 623 | end if; |
---|
| 624 | timeout:=timeout+1; |
---|
| 625 | |
---|
| 626 | end if; |
---|
| 627 | when cmdend => |
---|
| 628 | |
---|
| 629 | |
---|
| 630 | --cdata_out_en(origport)<='0'; |
---|
| 631 | |
---|
| 632 | -- if origport>=mport then -- provoquer le passage au prochain port de réception |
---|
| 633 | -- origport:=1; |
---|
| 634 | -- else |
---|
| 635 | -- origport:=origport+1; |
---|
| 636 | -- end if; |
---|
| 637 | etcmd<=cmdstart; |
---|
| 638 | --cmd_in_en(origport)<='0'; |
---|
| 639 | when cmdtimeout => |
---|
| 640 | etcmd<=cmdtimeout; |
---|
| 641 | --cmd_in_en(origport)<='0'; |
---|
| 642 | etcmd<=cmdstart; |
---|
| 643 | end case; |
---|
| 644 | sorigport<=origport; |
---|
| 645 | end if; --reset='1' |
---|
| 646 | |
---|
| 647 | end process pcmd; |
---|
| 648 | |
---|
| 649 | majetcmd:process (etcmd) |
---|
| 650 | variable origport : natural:=1;-- =sorigport ; |
---|
| 651 | begin |
---|
| 652 | case etcmd is |
---|
| 653 | when cmdstart => |
---|
| 654 | |
---|
| 655 | cmd_in_en(origport)<='1'; |
---|
| 656 | |
---|
| 657 | when cmdpost => |
---|
| 658 | din4(origport)<='1'; |
---|
| 659 | tosend4<="00000001"; ---code pour getportid |
---|
| 660 | cmd_in_en(origport)<='1'; |
---|
| 661 | cdata_out_en(origport)<='0'; |
---|
| 662 | when cmdpostidle => |
---|
| 663 | din4(origport)<='0'; |
---|
| 664 | cdata_out_en(origport)<=data_available(origport); |
---|
| 665 | cmd_in_en(origport)<='1'; |
---|
| 666 | |
---|
| 667 | when cmdread => |
---|
| 668 | din4(origport)<='0'; |
---|
| 669 | cdata_out_en(origport)<=data_available(origport); |
---|
| 670 | cmd_in_en(origport)<='1'; |
---|
| 671 | |
---|
| 672 | when cmdlen |cmdglen => --positionnement du mot de longueur des données |
---|
| 673 | |
---|
| 674 | din4(origport)<='0'; |
---|
| 675 | cdata_out_en(origport)<=data_available(origport); |
---|
| 676 | cmd_in_en(origport)<='1'; |
---|
| 677 | |
---|
| 678 | when cmddata => |
---|
| 679 | |
---|
| 680 | din4(origport)<='0'; |
---|
| 681 | cdata_out_en(origport)<=data_available(origport); |
---|
| 682 | cmd_in_en(origport)<='1'; |
---|
| 683 | |
---|
| 684 | |
---|
| 685 | when cmdend => |
---|
| 686 | |
---|
| 687 | din4(origport)<='0'; |
---|
| 688 | cdata_out_en(origport)<='0'; |
---|
| 689 | cmd_in_en(origport)<='0'; |
---|
| 690 | |
---|
| 691 | when cmdtimeout => |
---|
| 692 | din4(origport)<='0'; |
---|
| 693 | cdata_out_en(origport)<='0'; |
---|
| 694 | cmd_in_en(origport)<='0'; |
---|
| 695 | |
---|
| 696 | end case; |
---|
| 697 | |
---|
| 698 | end process majetcmd ; |
---|
| 699 | -- Stimulus process |
---|
| 700 | stim_proc: process |
---|
| 701 | begin |
---|
| 702 | -- hold reset state for 100 ns. |
---|
| 703 | reset<='1'; |
---|
| 704 | wait for 1 ns; |
---|
| 705 | reset<='1'; |
---|
| 706 | wait for clk_period*10; |
---|
| 707 | reset<='0'; |
---|
| 708 | wait; |
---|
| 709 | -- insert stimulus here |
---|
| 710 | |
---|
| 711 | |
---|
| 712 | |
---|
| 713 | |
---|
| 714 | end process; |
---|
| 715 | |
---|
| 716 | END; |
---|