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HT_dyn.vhd @ 153

Last change on this file since 153 was 153, checked in by rolagamo, 10 years ago

File size: 18.7 KB

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1	----------------------------------------------------------------------------------
2	-- Company:
3	-- Engineer:
4	--
5	-- Create Date: 12:04:21 04/22/2013
6	-- Design Name:
7	-- Module Name: HT_process - Behavioral
8	-- Project Name:
9	-- Target Devices:
10	-- Tool versions:
11	-- Description:
12	--
13	-- Dependencies:
14	--
15	-- Revision:
16	-- Revision 0.01 - File Created
17	-- Additional Comments:
18	--
19	----------------------------------------------------------------------------------
20	library IEEE;
21	use IEEE.STD_LOGIC_1164.ALL;
22	USE ieee.numeric_std.ALL;
23	library NocLib ;
24
25	use std.textio.all;
26	use NocLib.CoreTypes.all;
27	Library MPI_HCL;
28	use MPI_HCL.Packet_type.all;
29	use MPI_HCL.MPI_RMA.all;
30	-- Uncomment the following library declaration if using
31	-- arithmetic functions with Signed or Unsigned values
32	--use IEEE.NUMERIC_STD.ALL;
33
34	-- Uncomment the following library declaration if instantiating
35	-- any Xilinx primitives in this code.
36	--library UNISIM;
37	--use UNISIM.VComponents.all;
38
39	entity HT_dyn is
40	generic (Task_id : natural:=0);
41	Port ( clk : in STD_LOGIC;
42	reset : in STD_LOGIC;
43	en : in std_logic; -- active la tâche
44	Interf_i : in core_i; --signaux pour l'interface IO
45	Interf_o : out core_o; --signaux pour l'interface IO
46	mem_o : out typ_dpram_o; -- signaux pour l'accès à la mémoire
47	mem_i : in typ_dpram_i; -- signaux pour l'accès à la mémoire
48	ct_out : out unsigned(7 downto 0);
49	ht_state : out typ_mae;
50	PE_in : in STD_LOGIC_VECTOR (Word-1 downto 0); --port GPIO pour le PE
51	PE_out : out STD_LOGIC_VECTOR (Word-1 downto 0) --port GPIO pour le PE
52	);
53	end HT_dyn;
54
55	architecture Behavioral of HT_dyn is
56	constant simres : time :=1 ps; --simulation resolution
57	constant realres : real :=1.0e-3; --ramener le temps en ns
58
59	--type typ_mae is (start,Fillmem,NextFill,InitApp,GetRank,WInCreate,WinPost,WinStart,
60	--putdata,getdata,getcmd,WinWait,WinCompleted,MpiSpawn,finalize,st_timeout);
61	signal sram : typ_dpram;
62	signal MyGroup:mpi_group;
63	signal MyWin : mpi_win;
64	signal MyRank :std_logic_vector(3 downto 0);
65	signal intercomm,array_of_errcodes : natural;
66	signal ct_state:natural:=0;
67	signal compteur:natural:=4321;
68	signal Libr : Core_io; --regroupe tous les signaux IO de la bibliothèque
69	signal RunState : typ_mae;
70	signal load : std_logic;
71	signal start1 : std_logic;
72	signal loadval : std_logic_vector(31 downto 0);
73	signal outval : std_logic_vector(31 downto 0);
74	signal zero : std_logic;
75	COMPONENT IP_Timer
76	PORT(
77	clk : IN std_logic;
78	reset : IN std_logic;
79	upDn : IN std_logic;
80	load : IN std_logic;
81	start : IN std_logic;
82	loadval : IN std_logic_vector(31 downto 0);
83	outval : OUT std_logic_vector(31 downto 0);
84	zero : OUT std_logic
85	);
86	END COMPONENT;
87	begin
88	Inst_IP_Timer: IP_Timer PORT MAP(
89	clk =>clk ,
90	reset => reset,
91	upDn => '0',
92	load => load,
93	start => start1,
94	loadval => loadval,
95	outval => outval,
96	zero => zero
97	);
98
99	--MAE du PE
100	--=======================================================================
101	-- Interf<=Libr;
102
103
104	pPutGet:process(clk,reset,en)
105
106	constant DATAPTR : natural :=256;
107	variable nb_rma:natural range 0 to 15:=0;
108	variable bfill,destrank,pid,mport : natural range 0 to 15;
109	variable fsrc,ret : natural range 0 to 15:=0;
110	variable timeout,ct,dlen,dcount : natural range 0 to 511;
111	variable adrToset,SrcAdr,DestAdr : std_logic_vector(ADRLEN-1 downto 0);
112	variable mywin : Mpi_win;
113	variable command , argv , maxprocs , info , root : natural:=0; --variable pour le spawn
114	variable comm : natural :=0;
115	variable iack,spawn : std_logic:='0';
116	variable adresse,adresse_rd :natural range 0 to 65536;
117	variable status_reg,config_reg,param :std_logic_vector(Word-1 downto 0):=(others=>'0');
118
119	--=======================================================
120	--variables pour la création du fichier de résultats
121	-- synthesis translate_off
122	type char_file is file of character;
123	file f: text;
124	variable status :file_open_status ;
125	variable char_count: integer range 0 to 65536 := 0;
126	variable str: string (1 to 79) ;
127	variable L: line;
128	variable fopened: std_logic:='0';
129
130	-- constant simres : time :=1 ps; --simulation resolution
131	-- constant realres : real :=1.0e-3; --ramener le temps en ns
132	-- returns real value of time parameter using pure VHDL
133	function rt(t : time) return real is
134	begin
135	--if (simres=0) then
136	return real(t/1 ns) * realres;
137	-- else
138	-- return 0.0;
139	-- end if;
140	end;
141	-- synthesis translate_on
142	--======================================================
143	begin
144	--=== Partie combinatoire du process ===================================
145
146	--=== Fin de la partie combinatoire du process ==========================
147
148
149
150	--end loop;
151
152	if (clk'event and clk='1') and en='1' then
153
154
155	if reset='1' then
156	RunState<=start;
157	bfill:=0;
158	ct:=0;
159	ct_state<=0;
160	dcount:=0;
161	sram<=init_dpram;
162	Libr<=init_Core_io;
163	spawn:='0';nb_rma:=0;
164	else
165	--==========================================================
166	--affectation des entrées sorties mémoires
167	sram.i.data_out<=mem_I.data_out;
168	mem_o.addr_wr<=sram.O.addr_wr;
169	mem_o.addr_rd<=sram.O.addr_rd ;
170	mem_o.we<=sram.O.we;
171	mem_o.ena<=sram.O.ena;
172	mem_o.enb<=sram.O.enb;
173	mem_o.data_in<=sram.O.data_in;
174	--affectation des entrées sorties MPI_HCL
175	Interf_o.Instr_EN<=Libr.O.instr_en;
176	Interf_o.Membusy<=Libr.O.MemBusy;
177	Interf_o.Instruction<=Libr.O.Instruction;
178	Libr.i.Instr_ack<=Interf_i.Instr_ack;
179	Libr.i.InitOk<=Interf_i.InitOk;
180	Libr.i.Hold_Req<=Interf_i.Hold_req;
181	Libr.I.Spawned<=Interf_i.Spawned;
182	--Libr.i.Hold_Ack<=Interf_i.Hold_Ack;
183	Libr.i.RamSel<=Interf_i.RamSel;
184	--ct_state<=ct; --pour débogage
185	--============================================================
186
187	case RunState is
188	when start =>
189	--Dcount<=0;
190	if bfill=0 then -- si le nombre de bloc de mémoire remplis est vide
191	--RunState<=InitApp;
192	runstate<=fillmem;
193	end if;
194	--Ram_busy<='0';
195	Libr.O.MemBusy<='0';
196	Libr.O.Instr_En<='0';
197	iack:='0';
198	adresse:=10;--DATAPTR;
199
200	adresse_rd:=0;
201	timeout:=0;
202	--dcount<=0;
203	sram.O.we<='0';
204	sram.O.ena<='0';
205	sram.O.enb<='0';
206	-- synthesis translate_off
207	if fopened='0' then
208	file_open(status,f, integer'image(Task_Id) & "test_file0.txt", APPEND_MODE);
209	--while not endfile(c_file_handle) loop
210	--end if;
211
212	--write (l,string'("Ce fichier contient des resultats de la simulation ; ;" & " started at time ; " & time'image(now)));
213	--report l.all;
214	-- writeline (f, l) ;
215	fopened:='1';
216	end if;
217	-- synthesis translate_on
218	when Fillmem =>
219	-- sram.O.we<='1';
220	-- sram.O.ena<='1';
221	-- sram.O.enb<='1';
222	-- if Libr.I.Ramsel='0' then
223	-- sram.O.addr_rd<=std_logic_vector(to_unsigned(adresse,ADRLEN));
224	-- sram.O.addr_wr<=std_logic_vector(to_unsigned(adresse,ADRLEN));
225	-- sram.O.data_in<=std_logic_vector(to_unsigned(dcount,8)); -- x"0f";
226	Libr.O.Instr_En<='0';
227	Writemem(ct,Libr,SRam,std_logic_vector(to_unsigned(adresse,ADRLEN)),std_logic_vector(to_unsigned(Task_id+1,8)));
228	if ct=0 then
229	dcount:=dcount+1;
230	timeout:=0;
231	if dcount=250 then
232	bfill:=bfill+1;
233
234	if bfill=4 then
235	--RunState<=WinCreate;
236	Runstate<=InitApp;
237	else
238	RunState<=nextfill;
239	end if;
240	else
241	adresse:=adresse+1;
242	--sram.O.addr_wr<=std_logic_vector(to_unsigned(adresse,ADRLEN));
243	RunState<=Fillmem;
244	end if;
245	end if;
246	--else -- attente de la libéraion de la mémoire
247	-- timeout:=timeout+1;
248	-- if timeout=500 then
249	-- RunState<=st_timeout;
250	-- end if;
251
252	-- end if;
253	when nextfill => --prépare le prochain bloc mémoire qui sera rempli
254	adresse:=250*bfill+10;
255
256	dcount:=0;
257	ct:=0;
258	RunState<=Fillmem;
259	Libr.O.Instr_En<='0';
260	sram.O.we<='1';
261	sram.O.ena<='1';
262	sram.O.enb<='0';
263	when InitApp =>
264	--code pour Init
265	dlen:=100;
266	if ct=0 then
267	-- synthesis translate_off
268	write (l,string'("Dlen; ;INIT1 " & integer'image(Dlen)& "; " & image(MyRank) & "; started at ; " & real'image(rt(now))));
269
270	report l.all;
271	writeline (f, l) ;
272	-- synthesis translate_on
273	end if;
274	pMPI_Init(ct,Libr,Clk,SRam);
275
276	adresse:=to_integer(unsigned(sram.O.addr_wr));
277	adresse_rd:=to_integer(unsigned(sram.O.addr_rd));
278
279	--if Libr.InitOk='1' then
280	if ct=0 then
281	RunState<=GetRank;
282	-- synthesis translate_off
283	write (l,string'("Dlen;" & integer'image(Dlen) & ";INIT2 " & integer'image(Dlen) & ";" & image(MyRank) & "; ended at ; " & real'image(rt(now))));
284	report l.all;
285	writeline (f, l) ;
286	-- synthesis translate_on
287	end if;
288
289
290
291	when GetRank =>
292	if ct=0 then
293	-- synthesis translate_off
294	write (l,string'("Dlen;" & integer'image(Dlen)& ";Rank1 " & integer'image(Dlen) & "; ; started ; " & real'image(rt(now))));
295	report l.all;
296	writeline (f, l) ;
297	-- synthesis translate_on
298	end if;
299	pMPI_Comm_rank(ct,Libr,sram,MPI_COMM_WORLD,MyRank);
300	adresse_rd:=to_integer(unsigned(sram.O.addr_rd));
301
302
303	if ct=0 then
304	RunState<=Fillmem;
305	RunState<=Wincreate;
306	-- synthesis translate_off
307	write (l,string'("Dlen;"& integer'image(dlen) & ";Rank2 " & integer'image(Dlen) & ";" & image(MyRank) & "; ended at ; " & real'image(rt(now))));
308	report l.all;
309	writeline (f, l) ;
310	-- synthesis translate_on
311	end if;
312
313
314	when Wincreate => --par défaut la fenêtre 0 est utilisée !
315	case MyRank is
316	when x"0"=>
317	Mygroup.grp<=x"0002";-- rank 1
318	MyGroup.nb<=2;
319	destRank:=1;
320	DestAdr:=X"043F";
321	nb_rma:=1;
322	when x"1" =>
323	Mygroup.grp<=x"0001";-- rank 0
324	destRank:=0;
325	DestAdr:=X"0440";
326	when x"2" =>
327	Mygroup.grp<=x"0000";-- aucun rank
328	destRank:=0;
329	DestAdr:=X"0473";
330	when x"3" =>
331	Mygroup.grp<=x"0000";-- aucun rank
332	destRank:=0;
333	DestAdr:=X"04A5";
334	when others => --cas des processus spawn
335	Mygroup.grp<=x"0000";-- rank 0
336	DestAdr:=X"022F";
337	destRank:=0;
338	end case;
339	RunState<=WinPost;
340	when WinPost =>
341	if ct=0 then
342	-- synthesis translate_off
343	write (l,string'("Dlen;"& integer'image(dlen) & ";WPost1 " & integer'image(Dlen) & "; ; started ; " & real'image(rt(now))));
344	report l.all;
345	writeline (f, l) ;
346	-- synthesis translate_on
347	end if;
348
349	pMPI_Win_Post(ct,Libr,sram,MyGroup,0,MyWin);
350
351	if ct=0 then
352	RunState<=WinStart;
353	-- synthesis translate_off
354	write (l,string'("Dlen;"& integer'image(dlen) & ";WPost2 " & integer'image(Dlen) & ";" & image(MyRank) & "; ended at ; " & real'image(rt(now))));
355	report l.all;
356	writeline (f, l) ;
357	-- synthesis translate_on
358	end if;
359
360	when WinStart =>
361	if ct=0 then
362	-- synthesis translate_off
363	write (l,string'("Dlen;" & integer'image(dlen) & ";WStart1 " & integer'image(Dlen) & "; ; started ; " & real'image(rt(now))));
364	report l.all;
365	writeline (f, l) ;
366	-- synthesis translate_on
367	end if;
368	pMPI_Win_start(ct,Libr,sram,MyGroup,0,MyWin);
369	adresse:=to_integer(unsigned(sram.O.addr_wr));
370	adresse_rd:=to_integer(unsigned(sram.O.addr_rd));
371
372	dcount:=ct;
373
374	if ct=0 then
375	if spawn='0' then
376	RunState<=PutData;
377	else
378	RunState<=WinCompleted;
379	end if;
380	-- synthesis translate_off
381	write (l,string'("Dlen;" & integer'image(dlen) & ";WStart2 " & integer'image(Dlen) & ";" & image(MyRank) & "; ended at ; " & real'image(rt(now))));
382	report l.all;
383	writeline (f, l) ;
384	-- synthesis translate_on
385	end if;
386
387
388	when putdata => --construire le packet pour le Put
389
390	--dlen:=251; ---
391	if ct=0 then
392	-- synthesis translate_off
393	write (l,string'("Dlen;" & integer'image(dlen) & ";PUT1 " & integer'image(dlen) & ";" & image(MyRank) & "; started at ; " & real'image(rt(now))));
394	report l.all;
395	writeline (f, l) ;
396	-- synthesis translate_on
397	end if;
398
399	SrcAdr:=X"0105";--std_logic_vector(to_unsigned(DATAPTR,ADRLEN));
400	--DestAdr:=X"033F";
401	pMPI_put(ct,Libr,Clk,Sram,SrcAdr,Dlen,MPI_int,destrank,DestAdr,Dlen,Mpi_int,Default_win);
402
403	adresse:=to_integer(unsigned(sram.O.addr_wr));
404	adresse_rd:=to_integer(unsigned(sram.O.addr_rd));
405
406	dcount:=ct;
407
408	if ct=0 then
409	RunState<=GetData;
410	-- synthesis translate_off
411	report "Put of Process n°; " & image(MyRank) & "; ended at ; " & real'image(rt(now));
412	write (l,string'("Dlen;" & integer'image(dlen) & ";PUT2 " & integer'image(dlen) & ";" & image(MyRank) & "; ended at time ; " & real'image(rt(now))));
413	report l.all;
414	writeline (f, l) ;
415	-- synthesis translate_on
416	end if;
417
418
419	when getdata => --positionnement du mot de longueur des données
420	--dlen:=251; ---
421	if ct=0 then
422	-- synthesis translate_off
423	write (l,string'("Dlen;" & integer'image(dlen) & ";GET1; " & image(MyRank) & "; started at ; " & real'image(rt(now))));
424	report l.all;
425	writeline (f, l) ;
426	-- synthesis translate_on
427	end if;
428
429	SrcAdr:=X"0104";
430	DestAdr:=X"1400";
431	if unsigned(MyRank) = 0 then
432	--pMPI_GET(ct,Libr,Clk,Sram,SrcAdr,Dlen,MPI_int,destrank,DestAdr,Dlen,Mpi_int,Default_win);
433	else
434
435	--pMPI_GET(ct,Libr,Clk,Sram,SrcAdr,Dlen,MPI_int,destrank,DestAdr,Dlen,Mpi_int,Default_win);
436	end if;
437	adresse:=to_integer(unsigned(sram.O.addr_wr));
438	adresse_rd:=to_integer(unsigned(sram.O.addr_rd));
439
440	dcount:=ct;
441
442	if ct=0 then
443	if unsigned(MyRank)/=0 then
444	RunState<=wincompleted;
445	else
446	nb_rma:=nb_rma+1;
447	if nb_rma=2 then
448	RunState<=wincompleted;
449	nb_rma:=0;
450	end if;
451	end if;
452	-- synthesis translate_off
453	assert ct/=0 report "GET_END " & integer'image(destrank)
454	severity Warning ;
455	write (l,string'("Dlen ;" & integer'image(dlen) & ";GET2 " & integer'image(dlen) & ";" & image(MyRank) & "; ended at ; " & real'image(rt(now))));
456	report l.all;
457
458	writeline (f, l) ;
459	-- synthesis translate_on
460	end if;
461
462	when WinCompleted =>
463	if ct=0 then
464	-- synthesis translate_off
465	write (l,string'("Dlen ;" & integer'image(dlen) & ";Compl1 " & integer'image(dlen) & ";" & image(MyRank) & "; started at ; " & real'image(rt(now))));
466	report l.all;
467	writeline (f, l) ;
468	-- synthesis translate_on
469	end if;
470	pMPI_Win_Complete(ct,Libr,sram,MyWin );
471	adresse:=to_integer(unsigned(sram.O.addr_wr));
472	adresse_rd:=to_integer(unsigned(sram.O.addr_rd));
473
474	if ct=0 then
475	RunState<=WinWait;
476	-- synthesis translate_off
477	write (l,string'("Dlen ;" & integer'image(dlen) & ";Compl2 " & integer'image(dlen) & ";" & image(MyRank) & "; ended at ; " & real'image(rt(now))));
478	report l.all;
479	writeline (f, l) ;
480	-- synthesis translate_on
481
482	end if;
483	when WinWait =>
484	if ct=0 then
485	-- synthesis translate_off
486	write (l,string'("Dlen ;" & integer'image(dlen) & ";WAIT1 " & integer'image(dlen) & ";" & image(MyRank) & "; started at ; " & real'image(rt(now))));
487	report l.all;
488	writeline (f, l) ;
489	-- synthesis translate_on
490	end if;
491	pMPI_Win_wait(ct,Libr,sram,MyWin );
492	adresse:=to_integer(unsigned(sram.O.addr_wr));
493	adresse_rd:=to_integer(unsigned(sram.O.addr_rd));
494
495	if ct=0 then
496	if unsigned(Myrank)>1 or spawn='1' then
497	RunState<=Finalize;
498	else
499	RunState<=MpiSpawn;
500	end if;
501	-- synthesis translate_off
502	write (l,string'("Dlen ;" & integer'image(dlen) & ";WAIT2 " & integer'image(dlen) & ";" & image(MyRank) & "; ended at ; " & real'image(rt(now))));
503	report l.all;
504	writeline (f, l) ;
505	-- synthesis translate_on
506
507	end if;
508	when GetCmd=>
509	adresse:=4; --adresse des paramètres
510	readmem(ct,Libr,SRam,std_logic_vector(to_unsigned(adresse,ADRLEN)),param);
511	if ct=0 then
512	if unsigned(MyRank)=0 then
513	if unsigned(param)=5 then
514	Runstate<=MPISpawn;
515	end if;
516	else
517	Runstate<=MPISpawn;
518	end if;
519
520	end if;
521	when MpiSpawn =>
522	if ct=0 then
523	-- synthesis translate_off
524	write (l,string'("Dlen ;" & integer'image(dlen) & ";Spawn1 " & integer'image(dlen) & ";" & image(MyRank) & "; started at ; " & real'image(rt(now))));
525	report l.all;
526	writeline (f, l) ;
527	-- synthesis translate_on
528	end if;
529	--(NextCtx : inout natural;signal Interf:inout Core_io;signal SysRam :inout typ_dpram;
530
531	maxprocs:=2;
532	pMPI_Comm_Spawn(ct,Libr,sram,command,argv,maxprocs,info,root,comm,intercomm,array_of_errcodes);
533	adresse:=to_integer(unsigned(sram.O.addr_wr));
534	adresse_rd:=to_integer(unsigned(sram.O.addr_rd));
535
536	if ct=0 then
537	if unsigned(Myrank)=0 and spawn='0' then
538	MyGroup.Grp<=x"000C";
539	spawn:='1';
540	Runstate<=WinPost;
541	else
542	RunState<=Finalize;
543	end if;
544	-- synthesis translate_off
545	write (l,string'("Dlen ;" & integer'image(dlen) & ";Spawn2 " & integer'image(dlen) & ";" & image(MyRank) & "; ended at ; " & real'image(rt(now))));
546	report l.all;
547	writeline (f, l) ;
548	-- synthesis translate_on
549
550	end if;
551	when finalize =>
552	if ct=0 then
553	-- synthesis translate_off
554	write (l,string'("Dlen ;" & integer'image(dlen) & ";FINALIZE1 " & integer'image(dlen) & ";" & image(MyRank) & "; started at ; " & real'image(rt(now))));
555	report l.all;
556	writeline (f, l) ;
557	-- synthesis translate_on
558	end if;
559	sram.O.we<='0';
560	sram.O.ena<='0';
561	sram.O.enb<='0';
562	if ct=0 then
563	RunState<=start;
564	-- synthesis translate_off
565	write (l,string'("Dlen ;" & integer'image(dlen) & ";FINALIZE2 " & integer'image(dlen) & ";" & image(MyRank) & "; ended at ; " & real'image(rt(now))));
566	report l.all;
567	writeline (f, l) ;
568	file_close(f);
569	fopened:='0';
570	-- synthesis translate_on
571	end if;
572
573	when st_timeout =>
574
575	sram.O.we<='0';
576	sram.O.ena<='0';
577	sram.O.enb<='0';
578
579	RunState<=start;
580	end case;
581	ct_state<=ct; --pour débogage
582	--ct_out<=ct;
583	end if;
584	end if;
585	--ct_out<=ct_state;
586	ht_state<=runstate;
587	end process pPutGet;
588	out_proc:process(clk)
589
590	begin
591
592	if rising_edge(clk) then
593	if Pe_in(0)='1' then
594	ct_out<=x"00";
595	compteur<=0;
596	elsif compteur>=5000000 then
597	compteur<=0;
598	ct_out<=to_unsigned(ct_state,8);
599	elsif compteur<=2500000 then
600	ct_out<=to_unsigned(ct_state+128,8);
601	compteur<=compteur+1;
602	else
603	ct_out<=to_unsigned(ct_state,8);
604	compteur<=0;
605	end if;
606	end if;
607	end process;
608	end Behavioral;
609

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source: PROJECT_CORE_MPI/MPI_HCL/BRANCHES/v2.1/Timer_Par/HT_dyn.vhd @ 153

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