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HT_stat.vhd @ 154

Last change on this file since 154 was 154, checked in by rolagamo, 10 years ago

File size: 19.2 KB

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1	----------------------------------------------------------------------------------
2	-- Company:
3	-- Engineer:
4	--
5	-- Create Date: 12:04:21 04/22/2013
6	-- Design Name:
7	-- Module Name: HT_process - Behavioral
8	-- Project Name:
9	-- Target Devices:
10	-- Tool versions:
11	-- Description:
12	--
13	-- Dependencies:
14	--
15	-- Revision:
16	-- Revision 0.01 - File Created
17	-- Additional Comments:
18	--
19	----------------------------------------------------------------------------------
20	library IEEE;
21	use IEEE.STD_LOGIC_1164.ALL;
22	USE ieee.numeric_std.ALL;
23	library NocLib ;
24
25	use std.textio.all;
26	use NocLib.CoreTypes.all;
27	Library MPI_HCL;
28	use MPI_HCL.Packet_type.all;
29	use MPI_HCL.MPI_RMA.all;
30	-- Uncomment the following library declaration if using
31	-- arithmetic functions with Signed or Unsigned values
32	--use IEEE.NUMERIC_STD.ALL;
33
34	-- Uncomment the following library declaration if instantiating
35	-- any Xilinx primitives in this code.
36	--library UNISIM;
37	--use UNISIM.VComponents.all;
38
39	entity HT_stat is
40	generic (Task_id : natural:=0);
41	Port ( clk : in STD_LOGIC;
42	reset : in STD_LOGIC;
43	en : in std_logic; -- active la tâche
44	Interf_i : in core_i; --signaux pour l'interface IO
45	Interf_o : out core_o; --signaux pour l'interface IO
46	mem_o : out typ_dpram_o; -- signaux pour l'accès à la mémoire
47	mem_i : in typ_dpram_i; -- signaux pour l'accès à la mémoire
48	ct_out :out unsigned(7 downto 0);
49	ht_state : out typ_mae;
50	PE_in : in STD_LOGIC_VECTOR (Word-1 downto 0); --port GPIO pour le PE
51	PE_out : out STD_LOGIC_VECTOR (Word-1 downto 0) --port GPIO pour le PE
52
53	);
54	end HT_stat;
55
56	architecture Behavioral of HT_stat is
57	constant simres : time :=1 ps; --simulation resolution
58	constant realres : real :=1.0e-3; --ramener le temps en ns
59
60	-- type typ_mae is (start,Fillmem,NextFill,InitApp,GetRank,WInCreate,WinPost,WinStart,
61	-- putdata,getdata,WinWait,WinCompleted,GetCmd,MpiSpawn,finalize,st_timeout);
62	signal sram : typ_dpram;
63	signal MyGroup:mpi_group;
64	signal MyWin : mpi_win;
65	signal MyRank :std_logic_vector(3 downto 0);
66	signal intercomm,array_of_errcodes : natural;
67	signal ct_state:natural :=0;
68	signal Libr : Core_io; --regroupe tous les signaux IO de la bibliothèque
69	signal RunState : typ_mae;
70	signal load : std_logic;
71	signal start1 : std_logic;
72	signal loadval : std_logic_vector(31 downto 0);
73	signal outval : std_logic_vector(31 downto 0);
74	signal zero : std_logic;
75	COMPONENT IP_Timer
76	PORT(
77	clk : IN std_logic;
78	reset : IN std_logic;
79	upDn : IN std_logic;
80	load : IN std_logic;
81	start : IN std_logic;
82	loadval : IN std_logic_vector(31 downto 0);
83	outval : OUT std_logic_vector(31 downto 0);
84	zero : OUT std_logic
85	);
86	END COMPONENT;
87
88	attribute keep : string;
89	attribute keep of sram : signal is "true";
90	attribute keep of libr : signal is "true";
91	attribute keep of RunState : signal is "true";
92	begin
93	Inst_IP_Timer: IP_Timer PORT MAP(
94	clk =>clk ,
95	reset => reset,
96	upDn => '0',
97	load => load,
98	start => start1,
99	loadval => loadval,
100	outval => outval,
101	zero => zero
102	);
103
104	--MAE du PE
105	--=======================================================================
106	-- Interf<=Libr;
107
108
109	pPutGet:process(clk,reset,en)
110
111	constant DATAPTR : natural :=256;
112	variable nb_rma:natural range 0 to 15:=0;
113	variable bfill,destrank,pid,mport : natural range 0 to 15;
114	variable fsrc,ret : natural range 0 to 15:=0;
115	variable ct : natural range 0 to 31;
116	variable timeout,dlen,dcount : natural range 0 to 511;
117	variable adrToset,SrcAdr,DestAdr : std_logic_vector(ADRLEN-1 downto 0);
118	variable mywin : Mpi_win;
119	variable command , argv , maxprocs , info , root : natural:=0; --variable pour le spawn
120	variable comm : natural :=0;
121	variable iack,spawn : std_logic:='0';
122	variable adresse,adresse_rd :natural range 0 to 65536;
123	variable status_reg,config_reg,param :std_logic_vector(Word-1 downto 0):=(others=>'0');
124
125	--=======================================================
126	--variables pour la création du fichier de résultats
127	-- synthesis translate_off
128	type char_file is file of character;
129	file f: text;
130	variable status :file_open_status ;
131	variable char_count: integer range 0 to 65536 := 0;
132	variable str: string (1 to 79) ;
133	variable L: line;
134	variable fopened: std_logic:='0'; --indique si le fichier est ouvert ou non
135
136	-- constant simres : time :=1 ps; --simulation resolution
137	-- constant realres : real :=1.0e-3; --ramener le temps en ns
138	-- returns real value of time parameter using pure VHDL
139	function rt(t : time) return real is
140	begin
141	--if (simres=0) then
142	return real(t/1 ns) * realres;
143	-- else
144	-- return 0.0;
145	-- end if;
146	end;
147	-- synthesis translate_on
148	--======================================================
149	begin
150	--=== Partie combinatoire du process ===================================
151
152	--=== Fin de la partie combinatoire du process ==========================
153
154
155
156	--end loop;
157
158	if (clk'event and clk='1') and en='1' then
159
160
161	if reset='1' then
162	RunState<=start;
163	bfill:=0;
164	ct:=0;
165	dcount:=0;
166	sram<=init_dpram;
167	Libr<=init_Core_io;
168	spawn:='0';nb_rma:=0;
169	MyRank<="0000";
170	Interf_o.Instr_EN<='0';
171	Interf_o.Membusy<='0';
172	Interf_o.Instruction<=x"00";
173	Libr.i.Instr_ack<='0';
174	Libr.i.InitOk<='0';
175	Libr.i.Hold_Req<='0';
176	Libr.I.Spawned<='0';
177	Libr.i.RamSel<='0';
178
179	else
180	--==========================================================
181	--affectation des entrées sorties mémoires
182	sram.i.data_out<=mem_I.data_out;
183	mem_o.addr_wr<=sram.O.addr_wr;
184	mem_o.addr_rd<=sram.O.addr_rd ;
185	mem_o.we<=sram.O.we;
186	mem_o.ena<=sram.O.ena;
187	mem_o.enb<=sram.O.enb;
188	mem_o.data_in<=sram.O.data_in;
189	--affectation des entrées sorties MPI_HCL
190	Interf_o.Instr_EN<=Libr.O.instr_en;
191	Interf_o.Membusy<=Libr.O.MemBusy;
192	Interf_o.Instruction<=Libr.O.Instruction;
193	Libr.i.Instr_ack<=Interf_i.Instr_ack;
194	Libr.i.InitOk<=Interf_i.InitOk;
195	Libr.i.Hold_Req<=Interf_i.Hold_req;
196	Libr.I.Spawned<=Interf_i.Spawned;
197	--Libr.i.Hold_Ack<=Interf_i.Hold_Ack;
198	Libr.i.RamSel<=Interf_i.RamSel;
199	--ct_state<=ct; --pour débogage
200	--============================================================
201
202	case RunState is
203	when start =>
204	--Dcount<=0;
205	if bfill=0 then -- si le nombre de bloc de mémoire remplis est vide
206	--RunState<=InitApp;
207	runstate<=fillmem;
208	end if;
209	--Ram_busy<='0';
210	Libr.O.MemBusy<='0';
211	Libr.O.Instr_En<='0';
212	iack:='0';
213	adresse:=10;--DATAPTR;
214
215	adresse_rd:=0;
216	timeout:=0;
217	--dcount<=0;
218	sram.O.we<='0';
219	sram.O.ena<='0';
220	sram.O.enb<='0';
221	-- synthesis translate_off
222	if fopened='0' then
223	file_open(status,f, integer'image(Task_Id) & "test_file0.txt", APPEND_MODE);
224	--while not endfile(c_file_handle) loop
225	--end if;
226
227	--write (l,string'("Ce fichier contient des resultats de la simulation ; ;" & " started at time ; " & time'image(now)));
228	--report l.all;
229	-- writeline (f, l) ;
230	fopened:='1';
231	end if;
232	-- synthesis translate_on
233	when Fillmem =>
234	-- sram.O.we<='1';
235	-- sram.O.ena<='1';
236	-- sram.O.enb<='1';
237	-- if Libr.I.Ramsel='0' then
238	-- sram.O.addr_rd<=std_logic_vector(to_unsigned(adresse,ADRLEN));
239	-- sram.O.addr_wr<=std_logic_vector(to_unsigned(adresse,ADRLEN));
240	-- sram.O.data_in<=std_logic_vector(to_unsigned(dcount,8)); -- x"0f";
241	Libr.O.Instr_En<='0';
242	Writemem(ct,Libr,SRam,std_logic_vector(to_unsigned(adresse,ADRLEN)),std_logic_vector(to_unsigned(dcount,8)));
243	if ct=0 then
244	dcount:=dcount+1;
245	timeout:=0;
246	if dcount=250 then
247	bfill:=bfill+1;
248
249	if bfill=4 then
250	--RunState<=WinCreate;
251	Runstate<=InitApp;
252	else
253	RunState<=nextfill;
254	end if;
255	else
256	adresse:=adresse+1;
257	--sram.O.addr_wr<=std_logic_vector(to_unsigned(adresse,ADRLEN));
258	RunState<=Fillmem;
259	end if;
260	end if;
261	--else -- attente de la libéraion de la mémoire
262	-- timeout:=timeout+1;
263	-- if timeout=500 then
264	-- RunState<=st_timeout;
265	-- end if;
266
267	-- end if;
268	when nextfill => --prépare le prochain bloc mémoire qui sera rempli
269	adresse:=250*bfill+10;
270
271	dcount:=0;
272	ct:=0;
273	RunState<=Fillmem;
274	Libr.O.Instr_En<='0';
275	sram.O.we<='1';
276	sram.O.ena<='1';
277	sram.O.enb<='0';
278	when InitApp =>
279	--code pour Init
280	dlen:=50;
281	if ct=0 then
282	-- synthesis translate_off
283	write (l,string'("Dlen; ;INIT1 " & integer'image(Dlen)& "; " & image(MyRank) & "; started at ; " & real'image(rt(now))));
284
285	report l.all;
286	writeline (f, l) ;
287	-- synthesis translate_on
288	end if;
289	pMPI_Init(ct,Libr,Clk,SRam);
290
291	adresse:=to_integer(unsigned(sram.O.addr_wr));
292	adresse_rd:=to_integer(unsigned(sram.O.addr_rd));
293
294	--if Libr.InitOk='1' then
295	if ct=0 then
296	RunState<=GetRank;
297	-- synthesis translate_off
298	write (l,string'("Dlen;" & integer'image(Dlen) & ";INIT2 " & integer'image(Dlen) & ";" & image(MyRank) & "; ended at ; " & real'image(rt(now))));
299	report l.all;
300	writeline (f, l) ;
301	-- synthesis translate_on
302	end if;
303
304
305
306	when GetRank =>
307	if ct=0 then
308	-- synthesis translate_off
309	write (l,string'("Dlen;" & integer'image(Dlen)& ";Rank1 " & integer'image(Dlen) & "; ; started ; " & real'image(rt(now))));
310	report l.all;
311	writeline (f, l) ;
312	-- synthesis translate_on
313	end if;
314	pMPI_Comm_rank(ct,Libr,sram,MPI_COMM_WORLD,MyRank);
315	adresse_rd:=to_integer(unsigned(sram.O.addr_rd));
316
317
318	if ct=0 then
319	RunState<=Fillmem;
320	RunState<=Wincreate;
321	-- synthesis translate_off
322	write (l,string'("Dlen;"& integer'image(dlen) & ";Rank2 " & integer'image(Dlen) & ";" & image(MyRank) & "; ended at ; " & real'image(rt(now))));
323	report l.all;
324	writeline (f, l) ;
325	-- synthesis translate_on
326	end if;
327
328
329	when Wincreate => --par défaut la fenêtre 0 est utilisée !
330	case MyRank is
331	when x"0"=>
332	Mygroup.grp<=x"0002";-- rank 1
333	MyGroup.nb<=2;
334	destRank:=1;
335	DestAdr:=X"043F";
336	nb_rma:=1;
337	when x"1" =>
338	Mygroup.grp<=x"0001";-- rank 0
339	destRank:=0;
340	DestAdr:=X"0440";
341	when x"2" =>
342	Mygroup.grp<=x"0001";-- rank 0
343	destRank:=0;
344	DestAdr:=X"0473";
345	when x"3" =>
346	Mygroup.grp<=x"0001";-- rank 0
347	destRank:=0;
348	DestAdr:=X"04A5";
349	when others => --cas des processus spawn
350	Mygroup.grp<=x"0000";-- rank 0
351	DestAdr:=X"022F";
352	destRank:=0;
353	end case;
354	RunState<=WinPost;
355	when WinPost =>
356	if ct=0 then
357	-- synthesis translate_off
358	write (l,string'("Dlen;"& integer'image(dlen) & ";WPost1 " & integer'image(Dlen) & "; ; started ; " & real'image(rt(now))));
359	report l.all;
360	writeline (f, l) ;
361	-- synthesis translate_on
362	end if;
363
364	pMPI_Win_Post(ct,Libr,sram,MyGroup,0,MyWin);
365
366	if ct=0 then
367	RunState<=WinStart;
368	-- synthesis translate_off
369	write (l,string'("Dlen;"& integer'image(dlen) & ";WPost2 " & integer'image(Dlen) & ";" & image(MyRank) & "; ended at ; " & real'image(rt(now))));
370	report l.all;
371	writeline (f, l) ;
372	-- synthesis translate_on
373	end if;
374
375	when WinStart =>
376	if ct=0 then
377	-- synthesis translate_off
378	write (l,string'("Dlen;" & integer'image(dlen) & ";WStart1 " & integer'image(Dlen) & "; ; started ; " & real'image(rt(now))));
379	report l.all;
380	writeline (f, l) ;
381	-- synthesis translate_on
382	end if;
383	pMPI_Win_start(ct,Libr,sram,MyGroup,0,MyWin);
384	adresse:=to_integer(unsigned(sram.O.addr_wr));
385	adresse_rd:=to_integer(unsigned(sram.O.addr_rd));
386
387	dcount:=ct;
388
389	if ct=0 then
390	if spawn='0' then
391	RunState<=PutData;
392	else
393	RunState<=WinCompleted;
394	end if;
395	-- synthesis translate_off
396	write (l,string'("Dlen;" & integer'image(dlen) & ";WStart2 " & integer'image(Dlen) & ";" & image(MyRank) & "; ended at ; " & real'image(rt(now))));
397	report l.all;
398	writeline (f, l) ;
399	-- synthesis translate_on
400	end if;
401
402
403	when putdata => --construire le packet pour le Put
404
405	--dlen:=251; ---
406	if ct=0 then
407	-- synthesis translate_off
408	write (l,string'("Dlen;" & integer'image(dlen) & ";PUT1 " & integer'image(dlen) & ";" & image(MyRank) & "; started at ; " & real'image(rt(now))));
409	report l.all;
410	writeline (f, l) ;
411	-- synthesis translate_on
412	end if;
413
414	SrcAdr:=X"0105";--std_logic_vector(to_unsigned(DATAPTR,ADRLEN));
415	--DestAdr:=X"033F";
416	pMPI_put(ct,Libr,Clk,Sram,SrcAdr,Dlen,MPI_int,destrank,DestAdr,Dlen,Mpi_int,Default_win);
417
418	adresse:=to_integer(unsigned(sram.O.addr_wr));
419	adresse_rd:=to_integer(unsigned(sram.O.addr_rd));
420
421	dcount:=ct;
422
423	if ct=0 then
424	RunState<=GetData;
425	-- synthesis translate_off
426	report "Put of Process n°; " & image(MyRank) & "; ended at ; " & real'image(rt(now));
427	write (l,string'("Dlen;" & integer'image(dlen) & ";PUT2 " & integer'image(dlen) & ";" & image(MyRank) & "; ended at time ; " & real'image(rt(now))));
428	report l.all;
429	writeline (f, l) ;
430	-- synthesis translate_on
431	end if;
432
433
434	when getdata => --positionnement du mot de longueur des données
435	--dlen:=251; ---
436	if ct=0 then
437	-- synthesis translate_off
438	write (l,string'("Dlen;" & integer'image(dlen) & ";GET1; " & image(MyRank) & "; started at ; " & real'image(rt(now))));
439	report l.all;
440	writeline (f, l) ;
441	-- synthesis translate_on
442	end if;
443
444	SrcAdr:=X"0104";
445	DestAdr:=X"1400";
446	if unsigned(MyRank) = 0 then
447	--pMPI_GET(ct,Libr,Clk,Sram,SrcAdr,Dlen,MPI_int,destrank,DestAdr,Dlen,Mpi_int,Default_win);
448	else
449
450	--pMPI_GET(ct,Libr,Clk,Sram,SrcAdr,Dlen,MPI_int,destrank,DestAdr,Dlen,Mpi_int,Default_win);
451	end if;
452	adresse:=to_integer(unsigned(sram.O.addr_wr));
453	adresse_rd:=to_integer(unsigned(sram.O.addr_rd));
454
455	dcount:=ct;
456
457	if ct=0 then
458	if unsigned(MyRank)/=0 then
459	RunState<=wincompleted;
460	else
461	nb_rma:=nb_rma+1;
462	if nb_rma=2 then
463	RunState<=wincompleted;
464	nb_rma:=0;
465	end if;
466	end if;
467	-- synthesis translate_off
468	assert ct/=0 report "GET_END " & integer'image(destrank)
469	severity Warning ;
470	write (l,string'("Dlen ;" & integer'image(dlen) & ";GET2 " & integer'image(dlen) & ";" & image(MyRank) & "; ended at ; " & real'image(rt(now))));
471	report l.all;
472
473	writeline (f, l) ;
474	-- synthesis translate_on
475	end if;
476
477	when WinCompleted =>
478	if ct=0 then
479	-- synthesis translate_off
480	write (l,string'("Dlen ;" & integer'image(dlen) & ";Compl1 " & integer'image(dlen) & ";" & image(MyRank) & "; started at ; " & real'image(rt(now))));
481	report l.all;
482	writeline (f, l) ;
483	-- synthesis translate_on
484	end if;
485	pMPI_Win_Complete(ct,Libr,sram,MyWin );
486	adresse:=to_integer(unsigned(sram.O.addr_wr));
487	adresse_rd:=to_integer(unsigned(sram.O.addr_rd));
488
489	if ct=0 then
490	RunState<=WinWait;
491	-- synthesis translate_off
492	write (l,string'("Dlen ;" & integer'image(dlen) & ";Compl2 " & integer'image(dlen) & ";" & image(MyRank) & "; ended at ; " & real'image(rt(now))));
493	report l.all;
494	writeline (f, l) ;
495	-- synthesis translate_on
496
497	end if;
498	when WinWait =>
499	if ct=0 then
500	-- synthesis translate_off
501	write (l,string'("Dlen ;" & integer'image(dlen) & ";WAIT1 " & integer'image(dlen) & ";" & image(MyRank) & "; started at ; " & real'image(rt(now))));
502	report l.all;
503	writeline (f, l) ;
504	-- synthesis translate_on
505	end if;
506	pMPI_Win_wait(ct,Libr,sram,MyWin );
507	adresse:=to_integer(unsigned(sram.O.addr_wr));
508	adresse_rd:=to_integer(unsigned(sram.O.addr_rd));
509
510	if ct=0 then
511	if unsigned(Myrank)>1 or spawn='1' then
512	RunState<=Finalize;
513	else
514	RunState<=GetCmd;
515	end if;
516	-- synthesis translate_off
517	write (l,string'("Dlen ;" & integer'image(dlen) & ";WAIT2 " & integer'image(dlen) & ";" & image(MyRank) & "; ended at ; " & real'image(rt(now))));
518	report l.all;
519	writeline (f, l) ;
520	-- synthesis translate_on
521
522	end if;
523	when GetCmd=>
524	adresse:=4; --adresse des paramètres
525	readmem(ct,Libr,SRam,std_logic_vector(to_unsigned(adresse,ADRLEN)),param);
526	if ct=0 then
527	if unsigned(MyRank)=0 then
528	if unsigned(param)=5 then
529	Runstate<=MPISpawn;
530	else
531	Runstate<=MPISpawn;
532	end if;
533	else
534	Runstate<=MPISpawn;
535	end if;
536
537	end if;
538	when MpiSpawn =>
539	if ct=0 then
540	-- synthesis translate_off
541	write (l,string'("Dlen ;" & integer'image(dlen) & ";Spawn1 " & integer'image(dlen) & ";" & image(MyRank) & "; started at ; " & real'image(rt(now))));
542	report l.all;
543	writeline (f, l) ;
544	-- synthesis translate_on
545	end if;
546	--(NextCtx : inout natural;signal Interf:inout Core_io;signal SysRam :inout typ_dpram;
547
548	maxprocs:=2;
549	pMPI_Comm_Spawn(ct,Libr,sram,command,argv,maxprocs,info,root,comm,intercomm,array_of_errcodes);
550	adresse:=to_integer(unsigned(sram.O.addr_wr));
551	adresse_rd:=to_integer(unsigned(sram.O.addr_rd));
552
553	if ct=0 then
554	if unsigned(Myrank)=0 and spawn='0' then
555	MyGroup.Grp<=x"000C";
556	spawn:='1';
557	Runstate<=WinPost;
558	else
559	RunState<=Finalize;
560	end if;
561	-- synthesis translate_off
562	write (l,string'("Dlen ;" & integer'image(dlen) & ";Spawn2 " & integer'image(dlen) & ";" & image(MyRank) & "; ended at ; " & real'image(rt(now))));
563	report l.all;
564	writeline (f, l) ;
565	-- synthesis translate_on
566
567	end if;
568	when finalize =>
569	if ct=0 then
570	-- synthesis translate_off
571	write (l,string'("Dlen ;" & integer'image(dlen) & ";FINALIZE1 " & integer'image(dlen) & ";" & image(MyRank) & "; started at ; " & real'image(rt(now))));
572	report l.all;
573	writeline (f, l) ;
574	-- synthesis translate_on
575	end if;
576	sram.O.we<='0';
577	sram.O.ena<='0';
578	sram.O.enb<='0';
579	if ct=0 then
580	RunState<=start;
581	-- synthesis translate_off
582	write (l,string'("Dlen ;" & integer'image(dlen) & ";FINALIZE2 " & integer'image(dlen) & ";" & image(MyRank) & "; ended at ; " & real'image(rt(now))));
583	report l.all;
584	writeline (f, l) ;
585	file_close(f);
586	fopened:='0';
587	-- synthesis translate_on
588	end if;
589
590	when st_timeout =>
591
592	sram.O.we<='0';
593	sram.O.ena<='0';
594	sram.O.enb<='0';
595
596	RunState<=start;
597	end case;
598	ct_state<=ct; --pour débogage
599	--ct_out<=ct;
600	end if;
601	end if;
602
603	end process pPutGet;
604	--ct_out<=ct_state;
605	ht_state<=runstate;
606	out_proc:process(clk)
607	variable compteur:natural;
608	begin
609	if rising_edge(clk) then
610	if reset='1' then
611	ct_out<=x"00";
612	compteur:=0;
613	elsif compteur>=5000000 then
614	compteur:=0;
615	ct_out<=to_unsigned(ct_state,8);
616	elsif compteur<=2500000 then
617	ct_out<=to_unsigned(ct_state+128,8);
618	compteur:=compteur+1;
619	else
620	ct_out<=to_unsigned(ct_state,8);
621	compteur:=compteur+1;
622	end if;
623	end if;
624	end process;
625	end Behavioral;
626

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source: PROJECT_CORE_MPI/MPI_HCL/BRANCHES/v2.1/Timer_Par/HT_stat.vhd @ 154

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