1 | -------------------------------------------------------------------------------- |
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2 | -- Company: |
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3 | -- Engineer: GAMOM Roland Christian |
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4 | -- |
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5 | -- Create Date: 16:44:13 08/01/2012 |
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6 | -- Design Name: |
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7 | -- Module Name: C:/Core MPI/CORE_MPI/MultiMPITest.vhd |
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8 | -- Project Name: MPI_CORE_COMPONENTS |
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9 | -- Target Device: |
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10 | -- Tool versions: |
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11 | -- Description: |
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12 | -- |
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13 | -- Template d'untilisation de MPI - HCL |
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14 | -- |
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15 | -- Dependencies: |
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16 | -- |
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17 | -- Revision: |
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18 | -- Revision 0.01 - File Created |
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19 | -- Additional Comments: |
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20 | -- |
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21 | -- |
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22 | -- |
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23 | -------------------------------------------------------------------------------- |
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24 | LIBRARY ieee; |
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25 | USE ieee.std_logic_1164.ALL; |
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26 | |
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27 | library NocLib ; |
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28 | |
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29 | use NocLib.CoreTypes.all; |
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30 | LIbrary MPI_HCL; |
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31 | use MPI_HCL.Packet_type.all; |
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32 | use work.Hcl_Arch_conf.all; |
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33 | USE ieee.numeric_std.ALL; |
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34 | Library UNISIM; |
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35 | use UNISIM.vcomponents.all; |
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36 | ENTITY Mpi_template IS |
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37 | --rem simulation translate_off |
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38 | port (clk100MHz : in std_logic; |
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39 | rstn : in std_logic; |
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40 | sw : in std_logic_vector(15 downto 0); --bouton bascule |
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41 | Led : out std_logic_vector(15 downto 0); |
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42 | --rem simulation translate_on |
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43 | RsRX : in STD_LOGIC; |
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44 | RsTX : out STD_LOGIC); |
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45 | END MPi_template; |
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46 | |
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47 | ARCHITECTURE behavior OF MPI_Template IS |
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48 | |
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49 | -- Composant pour le diviseur d'horloge |
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50 | component CLKDIV |
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51 | port |
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52 | (-- Clock in ports |
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53 | SysCLK100 : in std_logic; |
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54 | -- Clock out ports |
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55 | CLK100 : out std_logic; |
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56 | CLK50 : out std_logic; |
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57 | CLK25 : out std_logic; |
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58 | -- Status and control signals |
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59 | RST : in std_logic; |
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60 | LOCKED : out std_logic |
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61 | ); |
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62 | end component; |
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63 | --------------------------------------------------------------------- |
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64 | -- |
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65 | -- ICON component declaration |
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66 | -- |
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67 | --------------------------------------------------------------------- |
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68 | |
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69 | component chipscope_icon |
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70 | port ( |
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71 | CONTROL0 : inout std_logic_vector(35 downto 0) |
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72 | |
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73 | ); |
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74 | end component; |
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75 | |
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76 | --------------------------------------------------------------------- |
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77 | -- |
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78 | -- VIO component declaration |
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79 | -- |
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80 | --------------------------------------------------------------------- |
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81 | |
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82 | component chipscope_vio |
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83 | port ( |
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84 | CONTROL : inout std_logic_vector(35 downto 0); |
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85 | CLK : in std_logic; |
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86 | SYNC_IN : in std_logic_vector(7 downto 0) |
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87 | ); |
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88 | end component; |
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89 | |
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90 | --------------------------------------------------------------------- |
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91 | -- |
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92 | -- ILA component declaration |
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93 | -- |
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94 | --------------------------------------------------------------------- |
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95 | |
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96 | component chipscope_ila |
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97 | port ( |
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98 | CONTROL : inout std_logic_vector(35 downto 0); |
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99 | CLK : in std_logic; |
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100 | TRIG0 : in std_logic_vector(7 downto 0); |
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101 | TRIG1 : in std_logic_vector(7 downto 0); |
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102 | TRIG2 : in std_logic_vector(7 downto 0); |
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103 | TRIG3 : in std_logic_vector(7 downto 0); |
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104 | TRIG4 : in std_logic_vector(7 downto 0); |
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105 | TRIG5 : in std_logic_vector(7 downto 0); |
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106 | TRIG6 : in std_logic_vector(7 downto 0); |
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107 | TRIG7 : in std_logic_vector(7 downto 0); |
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108 | TRIG_OUT : out std_logic |
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109 | ); |
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110 | end component; |
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111 | COMPONENT MPI_NOC |
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112 | generic (NPROC: natural:=2); |
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113 | PORT( |
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114 | MPI_Node_in : IN Ar_MPIPort_in(1 to NPROC); |
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115 | MPI_Node_Out : OUT Ar_MPIPort_out(1 to NPROC) |
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116 | ); |
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117 | END COMPONENT; |
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118 | component proto_send is |
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119 | generic (sizemem : natural := 64); |
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120 | port ( |
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121 | clk,reset : in std_logic; |
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122 | fifo_in_empty,fifo_in_full : in std_logic; --signaux pour le fifo d'entrée |
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123 | fifo_out_empty,fifo_out_full : in std_logic; --signaux pour le fifo de sortie |
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124 | fifo_out_wr_en : out std_logic:='0'; --écriture autorisée dans la fifo de sortie |
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125 | fifo_in_rd_en : out std_logic:='0'; --lecture autorisée dans la fifo d'entrée |
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126 | fifo_in_data_out : in std_logic_vector(Word-1 downto 0); |
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127 | fifo_out_data_in : out std_logic_vector(Word-1 downto 0); |
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128 | packet_len : in std_logic_vector(Word-1 downto 0); --la longueur du paquet |
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129 | copy_mode : in std_logic; --Fifo_to_mem ou Fifo_to_fifo |
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130 | snd_start : in std_logic; --début de la réception |
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131 | snd_ack :in std_logic; -- acquittement de la réception |
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132 | snd_comp : out std_logic; -- fin de la réception |
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133 | mem :in memory(0 to sizemem-1)); --données à copier vers le fifo |
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134 | end component proto_send; |
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135 | Component Fifo2mem is |
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136 | Port ( clk : in STD_LOGIC; |
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137 | reset : in STD_LOGIC; |
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138 | wr_start : in STD_LOGIC; |
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139 | fifo_data_out : in STD_LOGIC_VECTOR (Word-1 downto 0); |
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140 | fifo_data_available : in STD_LOGIC; |
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141 | datalen : STD_LOGIC_VECTOR (Word-1 downto 0); |
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142 | fifo_data_out_en : out STD_LOGIC; |
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143 | fifo_empty : in STD_LOGIC; |
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144 | ram_busy : in STD_LOGIC; |
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145 | ram_addr_start : in STD_LOGIC_VECTOR (ADRLEN-1 downto 0); |
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146 | ram_addr : out STD_LOGIC_VECTOR (ADRLEN-1 downto 0); |
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147 | ram_data_in : out STD_LOGIC_VECTOR (Word-1 downto 0); |
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148 | ram_wr : out STD_LOGIC; |
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149 | ram_en : out STD_LOGIC; |
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150 | wr_comp :out STD_LOGIC); |
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151 | end component fifo2mem; |
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152 | |
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153 | COMPONENT mem2fifo_a is --copy from memory to fifo |
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154 | port ( |
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155 | clk,reset : in std_logic; |
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156 | copy_mode : in std_logic; --Fifo_to_mem ou Fifo_to_fifo |
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157 | snd_start : in std_logic; --début de la réception |
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158 | snd_ack :in std_logic; -- acquittement de la réception |
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159 | datalen : in std_logic_vector(Word-1 downto 0); --la longueur du paquet |
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160 | ram_busy : in STD_LOGIC; |
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161 | ram_addr_start :in std_logic_vector(ADRLEN-1 downto 0); --addresse de début du bloc de donnée à copier |
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162 | fifo_out_empty,fifo_out_full : in std_logic; --signaux pour le fifo de sortie |
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163 | fifo_out_wr_en : out std_logic:='0'; --écriture autorisée dans la fifo de sortie |
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164 | ram_in_rd_en : out std_logic:='0'; --lecture autorisée dans la fifo d'entrée |
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165 | ram_in_data_out : in std_logic_vector(Word-1 downto 0); |
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166 | ram_in_addr_rd :out std_logic_vector(ADRLEN-1 downto 0); --addresse de la donnée à copier |
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167 | fifo_out_data_in : out std_logic_vector(Word-1 downto 0); |
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168 | snd_comp : out std_logic); -- fin de la réception |
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169 | |
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170 | END COMPONENT mem2fifo_a; |
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171 | |
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172 | COMPONENT UART_TX_CTRL generic (ComRate : natural:=217); |
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173 | PORT( |
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174 | SEND : IN std_logic; |
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175 | DATA : IN std_logic_vector(7 downto 0); |
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176 | CLK : IN std_logic; |
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177 | READY : OUT std_logic; |
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178 | UART_TX : OUT std_logic |
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179 | ); |
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180 | END COMPONENT; |
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181 | component com_icap is |
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182 | generic ( hexmode : boolean := true; -- false is for faster binary mode, but will not work on all machines/boards |
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183 | ComRate : integer := 217); -- ComRate = f_CLK / Boud_rate (e.g., 25 MHz/115200 Boud = 217) |
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184 | port (CLK : in std_logic; |
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185 | Rx : in std_logic; |
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186 | Tx : out std_logic; |
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187 | RxErr: out std_logic; |
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188 | debug0: out std_logic_vector(19 downto 0); |
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189 | debug1: out std_logic_vector(19 downto 0); |
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190 | debug2: out std_logic_vector(19 downto 0); |
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191 | bs_load_start : in std_logic; --début de réception bitstream |
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192 | bs_load_comp :out std_logic; --fin de réception |
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193 | bs_load_ack :in std_logic; --acquitement bistream |
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194 | bs_load_data : out std_logic_vector(31 downto 0); |
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195 | rxWord : out std_logic_vector(7 downto 0); -- mot reçu |
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196 | RxRdy : out std_logic; --données reçues |
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197 | ComActive : out std_logic; |
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198 | WriteStrobe : out std_logic; |
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199 | ReceiveLED : out std_logic); |
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200 | end component com_icap; |
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201 | Component PE |
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202 | generic(destid : natural; |
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203 | use_dyn:natural); |
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204 | Port ( Instruction : out STD_LOGIC_VECTOR (Word-1 downto 0); |
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205 | Instruction_en : out STD_LOGIC; |
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206 | Core_PushOut : in STD_LOGIC_VECTOR (Word-1 downto 0); |
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207 | clk : in STD_LOGIC; |
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208 | reset : in STD_LOGIC; |
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209 | CE : in STD_LOGIC; |
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210 | ct_out : out unsigned(7 downto 0); |
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211 | PE_in : in STD_LOGIC_VECTOR (Word-1 downto 0); |
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212 | PE_out : out STD_LOGIC_VECTOR (Word-1 downto 0); |
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213 | Core_RAM_Data_Out : out STD_LOGIC_VECTOR (Word-1 downto 0); |
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214 | Core_RAM_Data_Out2: out STD_LOGIC_VECTOR (Word-1 downto 0); |
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215 | Core_RAM_Data_In : in STD_LOGIC_VECTOR (Word-1 downto 0); |
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216 | Core_RAM_WE : in STD_LOGIC; |
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217 | Core_RAM_EN : in STD_LOGIC; |
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218 | --Core_RAM_ENB : in STD_LOGIC; |
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219 | Core_RAM_ADDRESS_WR : in STD_LOGIC_VECTOR (ADRLEN-1 downto 0); |
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220 | Core_RAM_ADDRESS_RD : in STD_LOGIC_VECTOR (ADRLEN-1 downto 0); |
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221 | Core_Hold_req : in STD_LOGIC; |
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222 | Core_Hold_Ack : out STD_LOGIC); |
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223 | end Component; |
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224 | component FIFO_256_FWFT |
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225 | port ( |
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226 | clk: IN std_logic; |
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227 | din: IN std_logic_VECTOR(Word-1 downto 0); |
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228 | rd_en: IN std_logic; |
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229 | srst: IN std_logic; |
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230 | wr_en: IN std_logic; |
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231 | dout: OUT std_logic_VECTOR(Word-1 downto 0); |
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232 | empty: OUT std_logic; |
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233 | full: OUT std_logic); |
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234 | end component; |
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235 | constant clk_period : time := 15 ns; |
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236 | constant PROC : positive :=NOC_SIZE; --4 |
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237 | |
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238 | --===================signaux pour l'horloge ============================== |
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239 | signal CLK100,CLK50,CLK25,reset,locked : std_logic := '0'; |
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240 | signal CLK200,Clkm,RST : std_logic := '0'; |
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241 | --======================================================================== |
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242 | |
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243 | --signaux pour la gestion de la MAE |
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244 | type typ_rs_send is (snd_wait,snd_read,snd_sendBit,snd_lf,snd_cr); |
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245 | type typ_mem is array (natural range <>) of std_logic_vector(Word-1 downto 0); |
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246 | type typ_tab is array (natural range <>) of unsigned(7 downto 0); |
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247 | --groupe de signaux utilisé pour communiquer avec l'extérieur de la plateforme |
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248 | type arDpRam is array (natural range <>) of typ_dpRam; |
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249 | type typ_Pconsole is(idle,get_bus,get_ht_mem,rd_ht_mem,wr_ht_mem, |
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250 | Write_cmd,Cmd_To_fifo,et_end); |
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251 | signal et_send :typ_rs_send; |
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252 | signal et_Pconsole,Next_et_Pconsole : typ_pconsole; |
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253 | signal Pcons_ram :typ_dpram; --signaux pour accès à la ram par la console |
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254 | signal pcons_hold_req,pcons_hold_ack: std_logic;--pour accès à la Ram du HT |
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255 | signal pcons_cmd : natural range 0 to 15; -- la commande qui est sollicitée depuis le clavier |
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256 | signal pcons_wr_comp,pcons_wr_start : std_logic;--pour contrôler l'écriture dans la Ram du HT |
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257 | signal pcons_fifo_wr:std_logic;--contrôle l'écriture des données dans le FIFO de sortie |
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258 | signal pcons_rd_comp,pcons_rd_start,pcons_rd_ack :std_logic; |
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259 | signal pcons_ram_busy : std_logic:='0'; |
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260 | signal pcons_data:std_logic_vector(Word-1 downto 0); --une données fournie par la console aux HTs |
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261 | signal pcons_ht : natural range 0 to 15:=0;--le numéro du HT qui est sollicité |
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262 | signal mux_hold_req,dmux_hold_ack: std_logic_vector(1 to PROC); --multiplexer les signaux d'accès RAM HT entre Core_MPI et console |
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263 | signal dmux_instruction : typ_mem(1 to PROC); |
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264 | signal dmux_instruction_en : std_logic_vector(1 to PROC); |
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265 | signal mux_ram,mux_ram_s,mux_ram_d : Ar_DpRam(1 to PROC); --signaux pour récupérer les données de la RAM |
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266 | signal pcons_sel,pcons_sel_i:std_logic_vector(1 to PROC):=(others=>'0');--état de la sélection du MUX entre Console et Core MPI |
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267 | signal pcons_fin_rd_en:std_logic; |
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268 | signal wr_ok,rd_ok:std_logic:='0'; |
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269 | signal presence : std_logic_vector(1 to 4); --signale les modules actifs |
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270 | signal ct_tab : typ_tab(1 to 4); --etat des sorties des MAE |
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271 | --signal PE_out : std_logic_vector(Word-1 downto 0); |
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272 | signal Sys_in : typ_mem(1 to PROC); |
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273 | signal Sys_Out : typ_mem(1 to PROC); |
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274 | -- |
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275 | --signaux pour le module de communication RS232C |
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276 | signal rs_cmd,rs_rw,rs_comp:std_logic; |
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277 | signal rs_addr_start:std_logic_vector(adrlen-1 downto 0); |
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278 | signal rs_plen :std_logic_vector(word-1 downto 0); |
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279 | signal rs_fifo_in_data_out_en:std_logic; |
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280 | signal rs_fifo_in_data_available : std_logic; |
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281 | signal rs_fifo_in_data_out :std_logic_vector(word-1 downto 0); |
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282 | signal rs_fifo_out_data_out_en:std_logic; |
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283 | signal rsin_fifo_data_available : std_logic; |
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284 | signal rs_fifo_out_data_out :std_logic_vector(word-1 downto 0); |
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285 | signal rs_fifo_out_empty:std_logic; |
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286 | -- |
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287 | signal dcount : natural range 0 to 255:=0; --permet de compter le packet de données envoyées |
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288 | signal count,count_i : natural range 0 to 15:=0; |
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289 | |
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290 | signal MPI_Node_in : Ar_MPIPort_in(1 to PROC) ; |
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291 | signal MPI_Node_Out : Ar_MPIPort_out(1 to PROC); |
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292 | --========================================================= |
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293 | --signaux pour la communication série |
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294 | constant period : time := 68 ns ; |
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295 | constant BITperiod : time := 8680 ns ; -- 115.200 ; -- 115.200 |
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296 | signal COM_RX : std_logic := '0'; |
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297 | signal COM_TX : std_logic := '0'; |
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298 | signal RSData :std_logic_vector (7 downto 0):=x"00"; |
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299 | signal Data_to_send :memory(0 to 8000); |
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300 | signal n : natural:=0; |
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301 | -- |
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302 | type UART_STATE_TYPE is (RST_REG, LD_INIT_STR, SEND_CHAR, RDY_LOW, WAIT_RDY, WAIT_BTN, LD_BTN_STR); |
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303 | type CHAR_ARRAY is array (integer range<>) of std_logic_vector(7 downto 0); |
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304 | constant MAX_STR_LEN : integer := 27; |
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305 | |
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306 | signal counter : std_logic_vector(25 downto 0) := (others => '0'); |
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307 | signal rxWord : std_logic_vector(7 downto 0); |
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308 | signal ComCommand : std_logic_vector(7 downto 0); |
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309 | signal comWriteStrobe :std_logic; |
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310 | signal ComActive, NotComActive : std_logic; |
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311 | signal RxRdy : std_logic; |
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312 | signal Local_COM_RX : std_logic; |
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313 | signal Local_COM_TX : std_logic; |
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314 | signal uartState : UART_STATE_TYPE := RST_REG; |
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315 | --UART_TX_CTRL control signals |
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316 | signal uartRdy : std_logic; |
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317 | signal uartSend : std_logic := '0'; |
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318 | signal uartData : std_logic_vector (7 downto 0):= "00000000"; |
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319 | signal uartTX : std_logic; |
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320 | --signale une erreur en cas de mauvaise réception |
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321 | signal Recv_Err_led : std_logic:='0'; |
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322 | --===============================================================+ |
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323 | --signaux pour les fifo d'entrée et de sortie |
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324 | |
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325 | signal rsin_fifo_rd_en:std_logic;--(ADRLEN-1 downto 0); |
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326 | signal rsin_fifo_wr_en : std_logic; |
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327 | signal rsin_fifo_empty : std_logic; |
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328 | signal rsin_fifo_full : std_logic; |
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329 | signal rsin_fifo_dout : std_logic_vector(WORD-1 downto 0); |
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330 | signal rsin_fifo_din : std_logic_vector(WORD-1 downto 0); |
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331 | signal rsout_fifo_rd_en:std_logic;--(ADRLEN-1 downto 0); |
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332 | signal rsout_fifo_wr_en : std_logic; |
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333 | signal rsout_fifo_empty : std_logic; |
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334 | signal rsout_fifo_full : std_logic; |
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335 | signal rsout_fifo_dout : std_logic_vector(WORD-1 downto 0); |
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336 | signal rsout_fifo_din : std_logic_vector(WORD-1 downto 0); |
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337 | --=============================================================== |
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338 | signal trigout : std_logic; |
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339 | signal syncin : std_logic_vector(7 downto 0); |
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340 | signal control_0 : std_logic_vector (35 downto 0); |
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341 | signal control_1 : std_logic_vector(35 downto 0); |
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342 | ----------------------------------------------------------------------- |
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343 | -- Constant Declaration |
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344 | ----------------------------------------------------------------------- |
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345 | constant C_NUM_OF_TRIGPORTS : integer := 8; |
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346 | constant C_TRIG0_SIZE : integer := 8; |
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347 | constant C_TRIG1_SIZE : integer := 8; |
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348 | constant C_TRIG2_SIZE : integer := 8; |
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349 | constant C_TRIG3_SIZE : integer := 8; |
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350 | constant C_TRIG4_SIZE : integer := 8; |
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351 | constant C_TRIG5_SIZE : integer := 8; |
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352 | constant C_TRIG6_SIZE : integer := 8; |
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353 | constant C_TRIG7_SIZE : integer := 8; |
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354 | --=============================================================== |
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355 | signal trig_0 : std_logic_vector(C_TRIG0_SIZE-1 downto 0); |
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356 | signal trig_1 : std_logic_vector(C_TRIG1_SIZE-1 downto 0); |
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357 | signal trig_2 : std_logic_vector(C_TRIG2_SIZE-1 downto 0); |
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358 | signal trig_3 : std_logic_vector(C_TRIG3_SIZE-1 downto 0); |
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359 | signal trig_4 : std_logic_vector(C_TRIG4_SIZE-1 downto 0); |
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360 | signal trig_5 : std_logic_vector(C_TRIG5_SIZE-1 downto 0); |
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361 | signal trig_6 : std_logic_vector(C_TRIG6_SIZE-1 downto 0); |
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362 | signal trig_7 : std_logic_vector(C_TRIG7_SIZE-1 downto 0); |
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363 | |
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364 | ---=============================================================== |
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365 | --signaux pour le port ICAP |
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366 | signal swap_reg : std_logic_vector(31 downto 0) := (others=>'0'); |
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367 | type RegStateType is (getHigh, getNib1,getNib2,getLow); |
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368 | signal RegState : RegStateType; |
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369 | signal IcapCLK_trigger, IcapCLK_trigger_reg, IcapCLK : std_logic; |
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370 | signal Icapi, IcapO : std_logic_vector(31 downto 0); |
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371 | signal IcapBUSY : std_logic; |
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372 | signal IcapCE : std_logic; |
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373 | Signal RdWrB : std_logic:='0'; --contrôle la lecture ou l'écriture du port ICAP |
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374 | signal icap_COM_RX,icap_COM_TX:std_logic; --conversion serie/ICAP |
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375 | -- Signaux pour le port Série qui reçoit le fichier *.Bit |
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376 | signal debug0: std_logic_vector(19 downto 0); |
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377 | signal debug1: std_logic_vector(19 downto 0); |
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378 | signal debug2: std_logic_vector(19 downto 0); |
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379 | signal receiveLed :std_logic; --led qui clignote au rithme des réceptions. |
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380 | signal bs_load_start : std_logic; --début de réception bitstream |
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381 | signal bs_load_comp : std_logic; --fin de réception |
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382 | signal bs_load_ack : std_logic; --acquitement bistream |
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383 | signal bs_load_data: std_logic_vector(31 downto 0); |
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384 | --signal rxWord : std_logic_vector(7 downto 0); -- mot reçu |
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385 | --signal RxRdy : std_logic; |
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386 | --================================================================= |
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387 | |
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388 | BEGIN |
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389 | SysMPI: MPI_NOC GENERIC MAP (NPROC=>NOC_SIZE) |
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390 | PORT MAP ( |
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391 | MPI_Node_in => MPI_Node_in, |
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392 | MPI_Node_Out => MPI_Node_Out |
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393 | ); |
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394 | -- |
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395 | ---port ICAP série ==================================================================== |
---|
396 | instcomicap:com_icap -- instantiate the UART receiving the configuration data |
---|
397 | generic map( |
---|
398 | hexmode => false, -- false is for faster binary mode, but will not work on all PCs |
---|
399 | ComRate => 108) -- ComRate = f_CLK / Boud_rate (e.g., 25 MHz/115200 Boud = 217) |
---|
400 | -- 1302 @ 19200 Boud 108 @ 230400/25 MHz |
---|
401 | port map ( |
---|
402 | clk => CLK25, |
---|
403 | rx => icap_COM_RX, |
---|
404 | tx => icap_COM_TX, |
---|
405 | rxerr => Recv_Err_led, |
---|
406 | rxRdy => RxRdy, |
---|
407 | --rxWord => RxWord, |
---|
408 | debug0 => debug0, |
---|
409 | debug1 => debug1, |
---|
410 | debug2 => debug2, |
---|
411 | RxWord => rxWord, |
---|
412 | bs_load_data => bs_load_data, |
---|
413 | comactive => ComActive, |
---|
414 | writestrobe => ComWritestrobe, |
---|
415 | bs_load_start => bs_load_start, |
---|
416 | bs_load_comp =>bs_load_comp, |
---|
417 | bs_load_ack =>bs_load_ack, |
---|
418 | receiveled => receiveled ); |
---|
419 | |
---|
420 | --======================================================== |
---|
421 | |
---|
422 | res_Led_sw:process (MPi_Node_out,sw,bs_load_start,CLK25,uartTX,rsRX, |
---|
423 | pcons_sel,receiveLed,presence) |
---|
424 | variable p:natural range 0 to 255:=1; |
---|
425 | begin |
---|
426 | p:=to_integer(unsigned(sw)); --récupérer les switchs pour définir les entrées |
---|
427 | if p>0 then |
---|
428 | Led(7 downto 0)<=MPi_Node_out(1).PushOut; |
---|
429 | else |
---|
430 | Led(7 downto 0)<=MPi_Node_out(2).PushOut; |
---|
431 | end if; |
---|
432 | led(8)<=sw(4); |
---|
433 | led(9)<=CLK25; |
---|
434 | led(10)<=uartTx; |
---|
435 | led(11)<=rsRX; |
---|
436 | led(12)<=ReceiveLed; |
---|
437 | led(13)<=pcons_sel(1); |
---|
438 | led(14)<=bs_load_start; |
---|
439 | led(8)<=presence(1); |
---|
440 | led(9)<=presence(2); |
---|
441 | led(15)<=presence(3); |
---|
442 | end process; |
---|
443 | --=========================================================== |
---|
444 | --diviseur d'horloge |
---|
445 | process(CLK100Mhz) |
---|
446 | begin |
---|
447 | if CLK100Mhz'event AND CLK100Mhz='1' then |
---|
448 | counter <= std_logic_vector(unsigned(counter) + 1); |
---|
449 | end if; |
---|
450 | end process; |
---|
451 | inst_CLKDIV : CLKDIV |
---|
452 | port map |
---|
453 | (-- Clock in ports |
---|
454 | SysCLK100 => CLK100Mhz, |
---|
455 | -- Clock out ports |
---|
456 | CLK100 => CLK100, |
---|
457 | CLK50 => CLK50, |
---|
458 | CLK25 => CLK25, |
---|
459 | -- Status and control signals |
---|
460 | RST => Rst, |
---|
461 | LOCKED => LOCKED); |
---|
462 | --CLKm<=counter(0);--horloge à 50 MHz |
---|
463 | CLKm<=CLK50;--counter(0);--horloge à 50 MHz |
---|
464 | --CLK25<=counter(1); --CLK10 est une horloge à 100 MHZ sur NEXSYS 4! |
---|
465 | reset<= not locked; --inversion de l'état de reset pour les composant du montage |
---|
466 | RST<= not rstn; |
---|
467 | --=========================================================== |
---|
468 | |
---|
469 | --=========================================================== |
---|
470 | S_Grp:for i in 1 to STATIC_HT generate |
---|
471 | S: PE Generic map (DestId=>i-1, |
---|
472 | use_dyn=>0) |
---|
473 | Port Map ( |
---|
474 | Instruction => dmux_instruction(i), |
---|
475 | Instruction_en =>dmux_instruction_en(i), |
---|
476 | Core_PushOut => MPi_Node_out(i).PushOut, |
---|
477 | clk =>clkm, |
---|
478 | reset =>reset, |
---|
479 | CE => '1', |
---|
480 | ct_out=>ct_tab(i), |
---|
481 | PE_Out=>Sys_out(i), |
---|
482 | PE_In=>sys_In(i), |
---|
483 | Core_RAM_Data_Out =>mux_ram_d(i).i.Data_out, |
---|
484 | Core_RAM_Data_Out2=>mux_ram_s(i).i.Data_out, |
---|
485 | Core_RAM_Data_IN => mux_ram(i).o.data_in, |
---|
486 | Core_RAM_WE => mux_ram(i).o.we, |
---|
487 | Core_RAM_EN => mux_ram(i).o.enb, |
---|
488 | Core_RAM_Address_Wr => mux_ram(i).o.addr_wr, |
---|
489 | Core_RAM_Address_Rd => mux_ram(i).o.addr_rd, |
---|
490 | Core_Hold_req => mux_hold_req(i), |
---|
491 | Core_Hold_Ack => dmux_hold_ack(i) |
---|
492 | |
---|
493 | ); |
---|
494 | |
---|
495 | end generate S_Grp; |
---|
496 | dyn_mod: if dyn_allowed='1' generate |
---|
497 | D_Grp:for i in STATIC_HT+1 to NOC_SIZE generate |
---|
498 | D: PE Generic map (DestId=>i-1, |
---|
499 | use_dyn=>1) |
---|
500 | Port Map ( |
---|
501 | Instruction => dmux_instruction(i),--MPi_Node_in(i).Instruction, |
---|
502 | Instruction_en =>dmux_instruction_en(i),-- MPi_Node_in(i).Instruction_en, |
---|
503 | Core_PushOut => MPi_Node_out(i).PushOut, |
---|
504 | clk =>clkm, |
---|
505 | reset =>reset, |
---|
506 | CE => '0', |
---|
507 | ct_out=>ct_tab(i), |
---|
508 | PE_Out=>Sys_out(i), |
---|
509 | PE_In=>sys_In(i), |
---|
510 | Core_RAM_Data_Out2 =>mux_ram_s(i).i.Data_out, |
---|
511 | Core_RAM_Data_Out =>mux_ram_d(i).i.Data_out, |
---|
512 | Core_RAM_Data_IN => mux_ram(i).o.data_in, |
---|
513 | Core_RAM_WE => mux_ram(i).o.we, |
---|
514 | Core_RAM_EN => mux_ram(i).o.enb, |
---|
515 | Core_RAM_Address_Wr => mux_ram(i).o.addr_wr, |
---|
516 | Core_RAM_Address_Rd => mux_ram(i).o.addr_rd, |
---|
517 | Core_Hold_req => mux_hold_req(i), |
---|
518 | Core_Hold_Ack => dmux_hold_ack(i) |
---|
519 | ); |
---|
520 | |
---|
521 | end generate D_Grp; |
---|
522 | end generate dyn_mod; |
---|
523 | |
---|
524 | trig_0(3 downto 0)<= x"0"; |
---|
525 | trig_0(7)<=MPi_Node_out(1).PushOut(0); |
---|
526 | trig_0(6)<=MPi_Node_out(2).PushOut(0); |
---|
527 | trig_0(5)<=MPi_Node_out(3).PushOut(0); |
---|
528 | trig_0(4)<=MPi_Node_out(4).PushOut(0); |
---|
529 | trig_1<=dmux_instruction(1); |
---|
530 | trig_2<=dmux_instruction(2); |
---|
531 | trig_3<=dmux_instruction(3); |
---|
532 | trig_4<=dmux_instruction(4); |
---|
533 | trig_5<=std_logic_vector(ct_tab(1)); |
---|
534 | trig_6<=std_logic_vector(ct_tab(2)); |
---|
535 | trig_7<=std_logic_vector(ct_tab(3)); |
---|
536 | |
---|
537 | --(7 => '0', 6 downto 5 => '1',others => '0') |
---|
538 | --affect_process |
---|
539 | affec_pres:process(ct_tab) |
---|
540 | begin |
---|
541 | for i in 1 to 4 loop |
---|
542 | presence(i)<=ct_tab(i)(7); |
---|
543 | end loop; |
---|
544 | end process; |
---|
545 | affec_PE:process(sw) |
---|
546 | begin |
---|
547 | for i in 1 to 4 loop |
---|
548 | sys_in(i)<=(0=>sw(i+7),others=>'1'); |
---|
549 | end loop; |
---|
550 | end process; |
---|
551 | --instantiation du FIFO_256 pour le port série |
---|
552 | RS_INPUT_FIFO : FIFO_256_FWFT |
---|
553 | port map ( |
---|
554 | clk => clkm, |
---|
555 | din => rsin_fifo_din, |
---|
556 | rd_en => rsin_fifo_rd_en, |
---|
557 | srst => reset, |
---|
558 | wr_en => rsin_fifo_wr_en, |
---|
559 | dout => rsin_fifo_dout, |
---|
560 | empty => rsin_fifo_empty, |
---|
561 | full => rsin_fifo_full); |
---|
562 | RS_OutPut_FIFO : FIFO_256_FWFT |
---|
563 | port map ( |
---|
564 | clk => clkm, |
---|
565 | din => rsout_fifo_din, |
---|
566 | rd_en => rsout_fifo_rd_en, |
---|
567 | srst => reset, |
---|
568 | wr_en => rsout_fifo_wr_en, |
---|
569 | dout => rsout_fifo_dout, |
---|
570 | empty => rsout_fifo_empty, |
---|
571 | full => rsout_fifo_full); |
---|
572 | |
---|
573 | ------------------------------------------------------------------- |
---|
574 | -- |
---|
575 | -- ICON Pro core instance |
---|
576 | -- |
---|
577 | ------------------------------------------------------------------- |
---|
578 | -- Icon core with two control ports is instantiated to connect to ILA and VIO cores. |
---|
579 | ICON_inst : chipscope_icon |
---|
580 | port map( |
---|
581 | CONTROL0 => control_0 -- INOUT BUS [35:0] |
---|
582 | |
---|
583 | ); |
---|
584 | |
---|
585 | --VIO_inst : chipscope_vio |
---|
586 | -- port map ( |
---|
587 | -- CONTROL => control_1, -- INOUT BUS (35:0) |
---|
588 | -- CLK => clk50, -- IN |
---|
589 | -- SYNC_IN =>MPi_Node_out(1).PushOut -- IN (7:0) |
---|
590 | -- ); |
---|
591 | |
---|
592 | ILA_inst : chipscope_ila |
---|
593 | port map ( |
---|
594 | CONTROL => control_0, -- INOUT BUS (35:0) |
---|
595 | CLK => clk50, -- IN |
---|
596 | TRIG0 => trig_0, -- IN BUS (7:0) |
---|
597 | TRIG1 => trig_1, -- IN BUS (7:0) |
---|
598 | TRIG2 => trig_2, -- IN BUS (7:0) |
---|
599 | TRIG3 => trig_3, -- IN BUS (7:0) |
---|
600 | TRIG4 => trig_4, -- IN BUS (7:0) |
---|
601 | TRIG5 => trig_5, -- IN BUS (7:0) |
---|
602 | TRIG6 => trig_6, -- IN BUS (7:0) |
---|
603 | TRIG7 => trig_7, -- IN BUS (7:0) |
---|
604 | TRIG_OUT => trigout -- OUT |
---|
605 | ); |
---|
606 | |
---|
607 | |
---|
608 | rsin_fifo_data_available<= not rsin_fifo_empty; |
---|
609 | -- Merge two bytes or four bytes if ICAPE2 from the UART to one 16/32 bit word for the Spartan-6 ICAP/ARTIX-7 ICAPE2 |
---|
610 | -- Note that we have to permute the bits within each byte... |
---|
611 | inversion_byte:process(bs_load_data) |
---|
612 | begin |
---|
613 | for i in 0 to 7 loop --inversion des bits octet par octet |
---|
614 | for j in 0 to 3 loop |
---|
615 | swap_reg(j*8+i)<= bs_load_data(j*8+7-i); |
---|
616 | end loop; |
---|
617 | end loop; |
---|
618 | end process; |
---|
619 | |
---|
620 | --- controle de la reconfiguration du FPGA |
---|
621 | process(CLKM) |
---|
622 | begin |
---|
623 | if rising_edge(clkm) then |
---|
624 | if ComWritestrobe='1' then |
---|
625 | IcapCLK_trigger <= '1'; |
---|
626 | else |
---|
627 | IcapCLK_trigger <= '0'; |
---|
628 | end if; |
---|
629 | IcapCLK_trigger_reg <= IcapCLK_trigger; |
---|
630 | end if; |
---|
631 | end process; |
---|
632 | --Component used to send a byte of data over a UART line. |
---|
633 | Inst_UART_TX_CTRL: UART_TX_CTRL generic map(ComRate => 217) |
---|
634 | port map( |
---|
635 | SEND => uartSend, |
---|
636 | DATA => uartData, |
---|
637 | CLK => CLKm, |
---|
638 | READY => uartRdy, |
---|
639 | UART_TX => uartTX |
---|
640 | ); |
---|
641 | rsTX<=UartTX; |
---|
642 | -- connect ICAP signals |
---|
643 | --icap_signal:process (Et_Icap,bs_load_data,writestrobe, |
---|
644 | --bs_load_start,bs_load_comp) |
---|
645 | --begin |
---|
646 | -- |
---|
647 | -- case et_icap is |
---|
648 | -- when icap_idle => |
---|
649 | -- IcapCE <= '1'; |
---|
650 | -- RDWRB<='1'; |
---|
651 | -- IcapI <= bs_load_data; |
---|
652 | -- when icap_writting => |
---|
653 | -- IcapCE <= '1'; |
---|
654 | -- RDWRB<='1'; |
---|
655 | -- IcapI <= bs_load_data; |
---|
656 | -- when icap_idle => |
---|
657 | IcapCLK<=clkm;--IcapCLK_trigger_reg |
---|
658 | IcapCE <= not comWritestrobe;--Not(bs_load_start); |
---|
659 | RDWRB<='0'; |
---|
660 | IcapI <= swap_reg; |
---|
661 | -- end case; |
---|
662 | -- ICAPE2: Internal Configuration Access Port |
---|
663 | -- Artix-7 ID=X3631093 Voir UG470 pour les autres devices |
---|
664 | -- Xilinx HDL Language Template, version 14.7 |
---|
665 | |
---|
666 | ICAPE2_inst : ICAPE2 |
---|
667 | generic map ( |
---|
668 | DEVICE_ID => X"03631093", -- Specifies the pre-programmed Device ID value to be used for simulation |
---|
669 | -- purposes. |
---|
670 | ICAP_WIDTH => "X32", -- Specifies the input and output data width. |
---|
671 | SIM_CFG_FILE_NAME => "None" -- Specifies the Raw Bitstream (RBT) file to be parsed by the simulation |
---|
672 | -- model. |
---|
673 | ) |
---|
674 | port map ( |
---|
675 | O => IcapO, -- 32-bit output: Configuration data output bus |
---|
676 | CLK => IcapCLK, -- 1-bit input: Clock Input |
---|
677 | CSIB => IcapCE, -- 1-bit input: Active-Low ICAP Enable |
---|
678 | I => IcapI, -- 32-bit input: Configuration data input bus |
---|
679 | RDWRB => RDWRB -- 1-bit input: Read/Write Select input |
---|
680 | ); |
---|
681 | |
---|
682 | -- End of ICAPE2_inst instantiation |
---|
683 | |
---|
684 | |
---|
685 | --****************************************** |
---|
686 | --** Gestion des switchs et de la réception des données |
---|
687 | --******************************************** |
---|
688 | process(clkm,sw,rsRX,bs_load_comp) |
---|
689 | begin |
---|
690 | if rising_edge(clkm) then |
---|
691 | if sw(0)='1' then |
---|
692 | rs_cmd<='1'; |
---|
693 | else |
---|
694 | rs_cmd<='0'; |
---|
695 | end if; |
---|
696 | |
---|
697 | if sw(1)='1' then |
---|
698 | rs_rw<='1'; |
---|
699 | else |
---|
700 | rs_rw<='0'; |
---|
701 | |
---|
702 | end if; |
---|
703 | |
---|
704 | --if sw(2)='1' or sw(3)='1' then |
---|
705 | --pcons_ht<=to_integer(unsigned(sw(3 downto 2))+1); --choix du HT à contrôler |
---|
706 | --else |
---|
707 | pcons_ht<=1; --choix du HT à contrôler |
---|
708 | --end if; |
---|
709 | if sw(3)='1' then |
---|
710 | icap_COM_RX<=rsRX; |
---|
711 | bs_load_start<='1'; |
---|
712 | bs_load_ack<=bs_load_comp; |
---|
713 | else |
---|
714 | icap_COM_RX<='1'; |
---|
715 | bs_load_start<='0'; |
---|
716 | bs_load_ack<='0'; |
---|
717 | end if; |
---|
718 | pcons_cmd<=to_integer(unsigned(sw(7 downto 4))); |
---|
719 | end if; |
---|
720 | end process; |
---|
721 | --************************************************************ |
---|
722 | --MAE de lecture de la mémoire de communication de chaque tâche et envoie des données |
---|
723 | -- sur le port série |
---|
724 | Pcons_sync:process(clkm) |
---|
725 | begin |
---|
726 | if rising_edge(clkm) then |
---|
727 | if reset='1' then |
---|
728 | Et_Pconsole<=idle; |
---|
729 | pcons_sel<=(others=>'0'); |
---|
730 | else |
---|
731 | et_Pconsole<=next_et_Pconsole; |
---|
732 | pcons_sel<=pcons_sel_i; |
---|
733 | end if; |
---|
734 | end if; |
---|
735 | end process; |
---|
736 | --********************************************************* |
---|
737 | Pcons_next : process(et_Pconsole,pcons_rd_comp,pcons_wr_comp,dmux_hold_ack,rs_cmd, |
---|
738 | rs_rw,rsin_fifo_empty,pcons_ht,MPI_Node_out,pcons_cmd,pcons_sel) |
---|
739 | |
---|
740 | variable bus_free:std_logic:='0'; |
---|
741 | begin |
---|
742 | next_et_pconsole<=et_Pconsole; --valeur par défaut |
---|
743 | pcons_sel_i<=pcons_sel; |
---|
744 | wr_ok<='0'; |
---|
745 | rd_ok<='0'; |
---|
746 | case et_pconsole is |
---|
747 | when idle => if rs_cmd='1' then |
---|
748 | next_et_pconsole<=get_bus; |
---|
749 | end if; |
---|
750 | pcons_sel_i<=(others=>'0'); |
---|
751 | when get_bus => |
---|
752 | bus_free:='0'; |
---|
753 | for i in 1 to PROC loop |
---|
754 | if pcons_ht=i then |
---|
755 | if MPI_Node_out(i).Hold_req='0' then |
---|
756 | Pcons_sel_i(i)<='1'; |
---|
757 | bus_free:='1'; |
---|
758 | else |
---|
759 | Pcons_sel_i(i)<='0'; |
---|
760 | end if; |
---|
761 | else |
---|
762 | Pcons_sel_i(i)<='0'; |
---|
763 | end if; |
---|
764 | end loop; |
---|
765 | if bus_free='1' then |
---|
766 | next_et_pconsole<=get_ht_mem; |
---|
767 | end if; |
---|
768 | when get_ht_mem => if dmux_hold_ack(pcons_ht)='1' then |
---|
769 | if pcons_cmd>0 then |
---|
770 | next_et_pconsole<=Cmd_to_fifo; |
---|
771 | else |
---|
772 | if rs_rw='1' then |
---|
773 | next_et_pconsole<=rd_ht_mem; |
---|
774 | else --if rs_rw='1' then |
---|
775 | next_et_pconsole<=wr_ht_mem; |
---|
776 | end if; |
---|
777 | end if; |
---|
778 | end if; |
---|
779 | when cmd_to_fifo=> if rsin_fifo_empty='1' then |
---|
780 | wr_ok<='1'; |
---|
781 | next_et_pconsole<=Write_cmd; |
---|
782 | else |
---|
783 | rd_ok<='1'; --vider le fifo |
---|
784 | end if; |
---|
785 | when Write_cmd => --écrire la commande dans la mémoire du HT |
---|
786 | if pcons_wr_comp='1' then |
---|
787 | if rs_rw='1' then |
---|
788 | next_et_pconsole<=rd_ht_mem; |
---|
789 | else --if rs_rw='1' then |
---|
790 | next_et_pconsole<=wr_ht_mem; |
---|
791 | end if; |
---|
792 | end if; |
---|
793 | when rd_ht_mem => if pcons_rd_comp='1' then |
---|
794 | |
---|
795 | next_et_pconsole<=et_end; |
---|
796 | end if; |
---|
797 | when wr_ht_mem=> if pcons_wr_comp='1' then |
---|
798 | next_et_pconsole<=et_end; |
---|
799 | |
---|
800 | end if; |
---|
801 | when et_end => |
---|
802 | for i in 1 to PROC loop |
---|
803 | Pcons_sel_i(i)<='0'; |
---|
804 | end loop; |
---|
805 | if rs_cmd='0' then --atendre la fin de la cmd |
---|
806 | next_et_pconsole<=idle; |
---|
807 | end if; |
---|
808 | end case; |
---|
809 | end process; |
---|
810 | --************************************************* |
---|
811 | Pcons_val : process(et_Pconsole,pcons_cmd,pcons_rd_comp,wr_ok,rd_ok, |
---|
812 | rxRdy,rxWord,pcons_fin_rd_en) |
---|
813 | begin |
---|
814 | pcons_rd_start<='0'; |
---|
815 | pcons_rd_ack<='0'; |
---|
816 | pcons_wr_start<='0'; |
---|
817 | Pcons_Hold_req<='0'; |
---|
818 | rs_comp<='0'; |
---|
819 | rs_addr_start<=x"0100"; |
---|
820 | rs_plen<=x"FA"; --taille des données à copier (250) |
---|
821 | rsin_fifo_wr_en<=RxRdy; |
---|
822 | rsin_fifo_din<=RxWord; |
---|
823 | rsin_fifo_rd_en<=pcons_fin_rd_en; |
---|
824 | case et_pconsole is |
---|
825 | when idle => |
---|
826 | when get_bus => |
---|
827 | when get_ht_mem => Pcons_Hold_req<='1'; |
---|
828 | WHEN Write_cmd=>rs_addr_start<=x"0004"; --adresse dans la mémoire pour les commandes |
---|
829 | rs_plen<=x"01"; --un seul octet |
---|
830 | pcons_wr_start<='1'; |
---|
831 | Pcons_Hold_req<='1'; |
---|
832 | when Cmd_to_fifo => |
---|
833 | rsin_fifo_wr_en<=wr_ok; |
---|
834 | rsin_fifo_rd_en<=rd_ok; |
---|
835 | rsin_fifo_din<=std_logic_vector(to_unsigned(pcons_cmd,WoRD)); |
---|
836 | Pcons_Hold_req<='1'; |
---|
837 | when rd_ht_mem => pcons_rd_start<='1'; |
---|
838 | Pcons_Hold_req<='1'; |
---|
839 | if pcons_cmd=1 then |
---|
840 | rs_addr_start<=x"1000"; |
---|
841 | elsif pcons_cmd=2 then |
---|
842 | rs_addr_start<=x"1200"; |
---|
843 | elsif pcons_cmd=3 then |
---|
844 | rs_addr_start<=x"0104"; |
---|
845 | elsif pcons_cmd=4 then |
---|
846 | rs_addr_start<=x"0004"; |
---|
847 | elsif pcons_cmd=5 then |
---|
848 | rs_addr_start<=x"0440"; |
---|
849 | end if; |
---|
850 | pcons_rd_ack<=pcons_rd_comp; |
---|
851 | when wr_ht_mem=> pcons_wr_start<='1'; |
---|
852 | Pcons_Hold_req<='1'; |
---|
853 | rs_addr_start<=x"0100"; |
---|
854 | when et_end=>rs_comp<='1'; |
---|
855 | pcons_wr_start<='0'; |
---|
856 | Pcons_Hold_req<='0'; |
---|
857 | end case; |
---|
858 | end process; |
---|
859 | --Multiplexeur de la console pour l'accès à la RAM de chaque HT. |
---|
860 | Ram_mux: process (MPI_Node_out,pcons_sel,pcons_ram.o, |
---|
861 | pcons_rd_start,pcons_wr_start,pcons_hold_req ) |
---|
862 | begin |
---|
863 | for i in 1 to PROC loop |
---|
864 | case Pcons_sel(i) is |
---|
865 | |
---|
866 | |
---|
867 | when '1' => |
---|
868 | mux_ram(i).o.addr_wr<=pcons_ram.o.addr_wr; |
---|
869 | mux_ram(i).o.addr_rd<=pcons_ram.o.addr_rd ; |
---|
870 | mux_ram(i).o.we<=pcons_ram.o.we; |
---|
871 | if pcons_rd_start='1' then |
---|
872 | mux_ram(i).o.enb<=pcons_ram.o.enb; |
---|
873 | elsif pcons_wr_start='1' then |
---|
874 | mux_ram(i).o.enb<=pcons_ram.o.ena; |
---|
875 | else |
---|
876 | mux_ram(i).o.enb<='0'; |
---|
877 | end if; |
---|
878 | mux_ram(i).o.data_in<=pcons_ram.o.data_in; |
---|
879 | mux_hold_req(i)<=Pcons_Hold_req; |
---|
880 | when others => |
---|
881 | mux_ram(i).o.addr_wr<=MPI_Node_out(i).Ram_address_wr; |
---|
882 | mux_ram(i).o.addr_rd<=MPI_Node_out(i).Ram_address_rd ; |
---|
883 | mux_ram(i).o.we<=MPI_Node_out(i).Ram_we; |
---|
884 | mux_ram(i).o.enb<=MPI_Node_out(i).Ram_en; |
---|
885 | mux_ram(i).o.data_in<=MPI_Node_out(i).Ram_data_in; |
---|
886 | mux_hold_req(i)<=MPI_Node_out(i).Hold_req; |
---|
887 | end case ; |
---|
888 | end loop; |
---|
889 | end process ; |
---|
890 | --écriture dans la mémoire d'une tâche matérielle |
---|
891 | Inst_Fifo2Mem: Fifo2Mem PORT MAP( |
---|
892 | clk =>clkm , |
---|
893 | reset =>reset , |
---|
894 | wr_start =>pcons_wr_start , |
---|
895 | fifo_data_out => rsin_fifo_dout, |
---|
896 | fifo_data_available =>rsin_fifo_data_available, |
---|
897 | datalen =>rs_plen , |
---|
898 | fifo_data_out_en =>pcons_fin_rd_en,--rsin_fifo_rd_en , |
---|
899 | fifo_empty =>'0' , |
---|
900 | ram_busy => pcons_ram_busy, --not pcons_sel(pcons_ht) , |
---|
901 | ram_addr_start =>rs_addr_start , |
---|
902 | ram_addr =>pcons_ram.o.addr_wr, |
---|
903 | ram_data_in =>pcons_ram.o.data_in , |
---|
904 | ram_wr =>pcons_ram.o.we , |
---|
905 | ram_en =>pcons_ram.o.ena, |
---|
906 | wr_comp =>pcons_wr_comp |
---|
907 | ); |
---|
908 | -- Lecture des données dans la RAM d'une tâche |
---|
909 | --ce process lit les données de la RAM et les charge dans le FIFO |
---|
910 | --copy from memory to fifo |
---|
911 | Inst_Mem2fifo: entity mpi_hcl.Mem2fifo_a PORT MAP( |
---|
912 | clk =>clkm , |
---|
913 | reset =>reset , |
---|
914 | copy_mode =>'0', |
---|
915 | snd_start=>pcons_rd_start, --début de la lecture |
---|
916 | snd_ack =>pcons_rd_ack, -- acquittement de la lecture |
---|
917 | datalen => rs_plen, --la longueur du paquet |
---|
918 | ram_busy => pcons_ram_busy, |
---|
919 | ram_addr_start => rs_addr_start, --addresse de début du bloc de donnée à copier |
---|
920 | fifo_out_empty=> rsout_fifo_empty, |
---|
921 | fifo_out_full => rsout_fifo_full, --signaux pour le fifo de sortie |
---|
922 | fifo_out_wr_en => rsout_fifo_wr_en, --écriture autorisée dans la fifo de sortie |
---|
923 | ram_in_rd_en => pcons_ram.o.enb, --lecture autorisée dans la fifo d'entrée |
---|
924 | ram_in_data_out=> pcons_ram.i.data_out, |
---|
925 | ram_in_addr_rd => pcons_ram.O.addr_rd, --addresse de la donnée à copier |
---|
926 | fifo_out_data_in => rsout_fifo_din, |
---|
927 | snd_comp => pcons_rd_comp -- fin de la lecture |
---|
928 | ); |
---|
929 | |
---|
930 | |
---|
931 | --démultiplexeurs de la console pour accès à la RAM de chaque Tâche matérielle. |
---|
932 | Ram_dmux : process(mux_ram_d,dmux_hold_ack,PCons_sel,pcons_ht,clkm,reset, |
---|
933 | dmux_instruction,dmux_instruction_en) |
---|
934 | variable Tram_out:std_logic_vector(Word-1 downto 0):=(others=>'0'); |
---|
935 | begin |
---|
936 | for i in 1 to PROC loop |
---|
937 | case PCons_sel(i) is |
---|
938 | |
---|
939 | when '1' => if pcons_ht=i then |
---|
940 | Pcons_hold_ack<=dmux_hold_ack(i); |
---|
941 | end if; |
---|
942 | --Pcons_ram.I.data_out<=mux_ram(i).i.data_out; |
---|
943 | if pcons_ht=i then |
---|
944 | Pcons_ram.I.data_out<=mux_ram_d(i).i.data_out; |
---|
945 | else |
---|
946 | TRam_out:=Tram_out or mux_ram_d(i).i.data_out; |
---|
947 | Pcons_ram.I.data_out<=Pcons_ram.I.data_out; |
---|
948 | end if; |
---|
949 | MPI_Node_in(i).hold_ack<='0'; |
---|
950 | MPI_Node_in(i).Ram_data_out<=(others=>'-'); |
---|
951 | when others => Pcons_hold_ack<='0'; |
---|
952 | --Pcons_ram.I.data_out<=(others=>'-'); |
---|
953 | TRam_out:=(others=>'-'); |
---|
954 | MPI_Node_in(i).hold_ack<=dmux_hold_ack(i); |
---|
955 | MPI_Node_in(i).Ram_data_out<=mux_ram_d(i).i.data_out; |
---|
956 | end case; |
---|
957 | MPI_Node_in(i).reset<=reset; |
---|
958 | MPI_Node_in(i).clk<=clkm; |
---|
959 | MPI_Node_in(i).instruction<=dmux_instruction(i); |
---|
960 | MPI_Node_in(i).instruction_en<=dmux_instruction_en(i); |
---|
961 | end loop; |
---|
962 | |
---|
963 | end process; |
---|
964 | |
---|
965 | sendrs232c_proc: process(clkm,reset,rsout_fifo_empty,rsout_fifo_dout, |
---|
966 | uartrdy) |
---|
967 | variable nib:natural range 0 to 1:=0; |
---|
968 | variable rs_crlf : natural range 0 to 3:=0; --compte les derniers mots |
---|
969 | begin |
---|
970 | |
---|
971 | if rising_edge(clkm) then |
---|
972 | rsout_fifo_rd_en<='0'; |
---|
973 | uartSend<='0'; |
---|
974 | --UartData<=rsout_fifo_dout or x"AA"; |
---|
975 | if reset='1' then |
---|
976 | et_send<=snd_wait; |
---|
977 | --rs_crlf:=0; |
---|
978 | else |
---|
979 | case et_send is |
---|
980 | |
---|
981 | when snd_wait => --attente |
---|
982 | --rs_crlf:=0; |
---|
983 | if rsout_fifo_empty='0' then |
---|
984 | et_send<=snd_read; |
---|
985 | --rs_crlf:=2; --deux caractères à envoyer |
---|
986 | end if; |
---|
987 | |
---|
988 | -- when snd_read => --lecture du mot |
---|
989 | -- if unsigned(rsout_fifo_dout)>31 then |
---|
990 | -- UartData<=rsout_fifo_dout ; |
---|
991 | -- else --rendre les codes observables en ASCII |
---|
992 | -- UartData<=rsout_fifo_dout or x"20"; |
---|
993 | -- end if; |
---|
994 | -- |
---|
995 | -- |
---|
996 | -- rsout_fifo_rd_en<='1'; |
---|
997 | -- et_send<=snd_sendBit; |
---|
998 | |
---|
999 | when snd_sendbit=> --envoie du mot |
---|
1000 | |
---|
1001 | UartSend<='1'; |
---|
1002 | if Uartrdy='1' and rsout_fifo_empty='0' then |
---|
1003 | et_send<=snd_read; |
---|
1004 | elsif UartRdy='1' then |
---|
1005 | et_send<=snd_Cr; --fin de l'envoi |
---|
1006 | end if; |
---|
1007 | when snd_read => |
---|
1008 | if Nib=0 then --envoi du code ascii en mode hexa décimal texte (Intel Hex) |
---|
1009 | UartData<=Hex_to_ascii(rsout_fifo_dout(7 downto 4)); |
---|
1010 | nib:=1; |
---|
1011 | rsout_fifo_rd_en<='0'; |
---|
1012 | et_send<=snd_sendBit; |
---|
1013 | else |
---|
1014 | UartData<=Hex_to_ascii(rsout_fifo_dout(3 downto 0)); |
---|
1015 | nib:=0; |
---|
1016 | rsout_fifo_rd_en<='1'; |
---|
1017 | et_send<=snd_sendBit; |
---|
1018 | end if; |
---|
1019 | et_send<=snd_sendbit; |
---|
1020 | When snd_Cr =>UartSend<='1'; |
---|
1021 | if UartRdy='1' then |
---|
1022 | et_send<=snd_lf; |
---|
1023 | end if; |
---|
1024 | UartData<=x"0D"; |
---|
1025 | When snd_Lf =>UartSend<='1'; |
---|
1026 | if UartRdy='1' then |
---|
1027 | et_send<=snd_wait; |
---|
1028 | end if; |
---|
1029 | UartData<=x"0A"; |
---|
1030 | when others => |
---|
1031 | |
---|
1032 | end case; |
---|
1033 | end if; |
---|
1034 | end if; |
---|
1035 | end process; |
---|
1036 | ------------------------------------------------------------------- |
---|
1037 | -- |
---|
1038 | -- If Trigout port is selected |
---|
1039 | -- |
---|
1040 | ------------------------------------------------------------------- |
---|
1041 | -- Trigger output logic triggers external test equipment and other logic. |
---|
1042 | -- In this example, TRIG_OUT is used to view shift operation on VIO core. |
---|
1043 | process (clk50) |
---|
1044 | begin |
---|
1045 | if (clk50'event and clk50='1') then |
---|
1046 | if(trigout = '1') then |
---|
1047 | syncin <= trig_0; |
---|
1048 | end if; |
---|
1049 | end if; |
---|
1050 | end process; |
---|
1051 | |
---|
1052 | END; |
---|