1 | ---------------------------------------------------------------------------------- |
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2 | -- Company: |
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3 | -- Engineer: GAMOM Roland Christian |
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4 | -- |
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5 | -- Create Date: 21:20:54 07/16/2012 |
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6 | -- Design Name: |
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7 | -- Module Name: PE - Behavioral |
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8 | -- Project Name: |
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9 | -- Target Devices: |
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10 | -- Tool versions: |
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11 | -- Description: Ce module permet d'encapsuler une tâche matérielle |
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12 | -- et lui donne la possiblité de communiquer à l'aide des fonctions MPI-2 RMA |
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13 | -- Dependencies: |
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14 | -- |
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15 | -- Revision: |
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16 | -- Revision 0.01 - File Created |
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17 | -- Additional Comments: |
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18 | -- |
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19 | ---------------------------------------------------------------------------------- |
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20 | library IEEE; |
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21 | use IEEE.STD_LOGIC_1164.ALL; |
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22 | library NocLib ; |
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23 | library Std; |
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24 | --use IEEE.STD_LOGIC_ARITH.ALL; |
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25 | --use IEEE.STD_LOGIC_UNSIGNED.ALL; |
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26 | Library MPI_HCL; |
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27 | use NocLib.CoreTypes.all; |
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28 | use MPI_HCL.Packet_type.all; |
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29 | use MPI_HCL.MPI_RMA.all; |
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30 | |
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31 | -- synthesis translate_off |
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32 | use std.textio.all; |
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33 | -- synthesis translate_on |
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34 | use IEEE.NUMERIC_STD.ALL; |
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35 | |
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36 | |
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37 | entity PE is |
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38 | Generic (DestId : natural:=0; --utiliser pour identifier la tâche |
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39 | Use_dyn : natural:=0); --détermine si le module est statique =0 ou reconfigurable =1 |
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40 | Port ( Instruction : out STD_LOGIC_VECTOR (Word-1 downto 0); |
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41 | Instruction_en : out STD_LOGIC; |
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42 | Core_PushOut : in STD_LOGIC_VECTOR (Word-1 downto 0); |
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43 | clk : in STD_LOGIC; |
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44 | reset : in STD_LOGIC; |
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45 | CE : in STD_LOGIC; -- Active le PE après sa synthèse |
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46 | PE_in : in STD_LOGIC_VECTOR (Word-1 downto 0); --port GPIO pour le PE |
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47 | PE_out : out STD_LOGIC_VECTOR (Word-1 downto 0); --port GPIO pour le PE |
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48 | Core_RAM_Data_Out : out STD_LOGIC_VECTOR (Word-1 downto 0); |
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49 | Core_RAM_Data_Out2: out STD_LOGIC_VECTOR (Word-1 downto 0); |
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50 | Core_RAM_Data_In : in STD_LOGIC_VECTOR (Word-1 downto 0); |
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51 | Core_RAM_WE : in STD_LOGIC; |
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52 | Core_RAM_EN : in STD_LOGIC; |
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53 | --Core_RAM_ENB : in STD_LOGIC; |
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54 | Core_RAM_ADDRESS_WR : in STD_LOGIC_VECTOR (ADRLEN-1 downto 0); |
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55 | Core_RAM_ADDRESS_RD : in STD_LOGIC_VECTOR (ADRLEN-1 downto 0); |
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56 | Core_Hold_req : in STD_LOGIC; |
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57 | ct_out : out unsigned(7 downto 0); |
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58 | ht_state : out typ_mae; |
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59 | Core_Hold_Ack : out STD_LOGIC); |
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60 | end PE; |
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61 | |
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62 | architecture Behavioral of PE is |
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63 | COMPONENT RAM_v |
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64 | generic (width : positive;size :positive); |
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65 | Port ( clka, clkb : in std_logic; |
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66 | wea : in std_logic; |
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67 | ena, enb : in std_logic; |
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68 | addra, addrb : in std_logic_vector(size-1 downto 0); --cinq lignes d'adresse |
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69 | dia : in std_logic_vector(width-1 downto 0); |
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70 | dob : out std_logic_vector(width-1 downto 0)); |
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71 | END COMPONENT; |
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72 | COMPONENT memo8k8 |
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73 | PORT ( |
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74 | clka : IN STD_LOGIC; |
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75 | ena : IN STD_LOGIC; |
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76 | wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0); |
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77 | addra : IN STD_LOGIC_VECTOR(12 DOWNTO 0); |
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78 | dina : IN STD_LOGIC_VECTOR(7 DOWNTO 0); |
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79 | clkb : IN STD_LOGIC; |
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80 | enb : IN STD_LOGIC; |
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81 | addrb : IN STD_LOGIC_VECTOR(12 DOWNTO 0); |
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82 | doutb : OUT STD_LOGIC_VECTOR(7 DOWNTO 0) |
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83 | ); |
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84 | END COMPONENT; |
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85 | COMPONENT HT_dyn is |
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86 | generic (Task_Id : natural); |
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87 | Port ( clk : in STD_LOGIC; |
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88 | reset : in STD_LOGIC; |
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89 | en : in std_logic; -- active la tâche |
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90 | Interf_i : in core_i; --signaux pour l'interface I |
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91 | Interf_o : out core_o; --signaux pour l'interface IO |
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92 | mem_i : in typ_dpram_i; -- signaux pour l'accès à la mémoire |
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93 | mem_o : out typ_dpram_o; -- signaux pour l'accès à la mémoire |
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94 | ct_out : out unsigned(7 downto 0); |
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95 | ht_state : out typ_mae; |
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96 | PE_in : in STD_LOGIC_VECTOR (Word-1 downto 0); --port GPIO pour le PE |
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97 | PE_out : out STD_LOGIC_VECTOR (Word-1 downto 0) --port GPIO pour le PE |
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98 | ); |
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99 | end COMPONENT HT_dyn; |
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100 | COMPONENT HT_stat is |
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101 | generic (Task_Id : natural); |
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102 | Port ( clk : in STD_LOGIC; |
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103 | reset : in STD_LOGIC; |
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104 | en : in std_logic; -- active la tâche |
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105 | Interf_i : in core_i; --signaux pour l'interface I |
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106 | Interf_o : out core_o; --signaux pour l'interface IO |
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107 | mem_i : in typ_dpram_i; -- signaux pour l'accès à la mémoire |
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108 | mem_o : out typ_dpram_o; -- signaux pour l'accès à la mémoire |
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109 | ct_out :out unsigned(7 downto 0); |
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110 | ht_state : out typ_mae; |
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111 | PE_in : in STD_LOGIC_VECTOR (Word-1 downto 0); --port GPIO pour le PE |
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112 | PE_out : out STD_LOGIC_VECTOR (Word-1 downto 0) --port GPIO pour le PE |
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113 | |
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114 | ); |
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115 | end COMPONENT HT_stat; |
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116 | |
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117 | COMPONENT Hold_FSM is |
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118 | |
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119 | Port ( Hold_Req : in STD_LOGIC; |
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120 | Ram_busy : in STD_LOGIC; |
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121 | Clk : in STD_LOGIC; |
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122 | Reset : in STD_LOGIC; |
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123 | Ramsel : out STD_LOGIC; |
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124 | Hold_Ack : out STD_LOGIC); |
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125 | end COMPONENT Hold_FSM; |
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126 | --données du programme PE |
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127 | --signaux pour l'interconnexionsignal datain :std_logic_vector(word-1 downto 0):= (others => '0'); |
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128 | signal ram_we ,ram_ena,ram_enb,ramsel_i: std_logic:='0'; |
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129 | signal pe_ram_we ,pe_ram_ena,pe_ram_enb: std_logic; |
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130 | signal pe_instr_en,pe_hold_ack: std_logic:='0'; |
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131 | signal ram_do,ram_din:std_logic_vector(word-1 downto 0):= (others => '0'); |
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132 | signal pe_ram_do,pe_ram_din:std_logic_vector(word-1 downto 0):= (others => '0'); |
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133 | signal ram_addra,ram_addrb :std_logic_vector(ADRLEN-1 downto 0); |
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134 | signal pe_ram_addra,pe_ram_addrb :std_logic_vector(ADRLEN-1 downto 0); |
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135 | signal CRAM_DO : STD_LOGIC_VECTOR (Word-1 downto 0); |
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136 | signal sram : typ_dpram; |
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137 | signal clk_ht : std_logic; |
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138 | signal MyGroup:mpi_group; |
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139 | signal MyWin : mpi_win; |
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140 | signal SrcAdr0,SrcAdr1,destAdr0,destAdr1,Datalen:std_logic_vector(word-1 downto 0); |
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141 | --signal PE_out_i:std_logic_vector(Word-1 downto 0); |
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142 | signal dpid,dpid_i : natural range 0 to 15:=DestId; |
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143 | signal MyRank :std_logic_vector(3 downto 0); |
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144 | signal Libr : Core_io; --regroupe tous les signaux IO de la bibliothèque |
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145 | signal Lib_Ready:std_logic; --indique que l'exécution de la fonction est terminée |
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146 | signal Lib_instr_ack : std_logic; -- l'instruction est copiée dans le tampon FIFO |
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147 | signal Lib_Init : std_logic; -- l'initialisation est terminée |
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148 | signal Lib_Enable : std_logic:='0'; |
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149 | signal Ex1_run,Ex4_run : std_logic:='0'; --indique que ces modules sont en fin d'exécution |
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150 | signal Hold_Ack : std_logic; |
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151 | signal en_task : std_logic; |
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152 | signal ht_reset :std_logic; |
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153 | signal raz_en:std_logic;--signal pour l'activation de la RAZ RAM |
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154 | signal m_count : natural:= 0; |
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155 | --signaux pour la gestion de la MAE |
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156 | type typ_Ht_ena is (ht_lock,ht_raz,ht_stop,ht_on); |
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157 | type typ_mae is (start,Fillmem,NextFill,InitApp,GetRank,WInCreate,WinStart, putdata,getdata,WinCompleted,finalize,st_timeout); |
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158 | type typ_Hld is (Ht_Lock,Core_Lock,Ht_free); |
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159 | signal dcount : natural range 0 to 255:=0; |
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160 | signal wea : std_logic_vector (0 downto 0); |
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161 | signal count,count_i : natural range 0 to 15:=0; |
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162 | signal et_ht_ena : typ_ht_ena; |
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163 | |
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164 | signal RunState : typ_mae; |
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165 | signal Hld_state :typ_hld; |
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166 | signal Ram_busy :std_logic:='0'; |
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167 | begin |
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168 | Ram8_k8: RAM_v generic map(width=>word,size=>ADRLEN) |
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169 | PORT MAP( |
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170 | clka =>clk , |
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171 | clkb => clk , |
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172 | wea => ram_we, |
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173 | ena => ram_ena, |
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174 | enb => ram_enb, |
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175 | addra => ram_addra, |
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176 | addrb =>ram_addrb, |
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177 | dia => ram_din, |
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178 | dob => ram_do |
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179 | ); |
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180 | --wea(0)<=ram_we; |
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181 | -- Ram8_k8 : memo8k8 |
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182 | -- PORT MAP ( |
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183 | -- clka => clk, |
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184 | -- ena => ram_ena, |
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185 | -- wea => wea, |
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186 | -- addra => ram_addra(12 downto 0), |
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187 | -- dina => ram_din, |
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188 | -- clkb => clk, |
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189 | -- enb => ram_enb, |
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190 | -- addrb => ram_addrb(12 downto 0), |
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191 | -- doutb => ram_do |
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192 | -- ); |
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193 | ts: if use_dyn=0 generate |
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194 | HT_task:HT_stat generic map(Task_id =>DestId) |
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195 | port map ( |
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196 | clk=>clk, |
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197 | reset=>ht_reset, |
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198 | en=>en_task, |
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199 | Interf_i =>Libr.i, |
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200 | Interf_o=>Libr.o, |
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201 | mem_i =>sram.i, |
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202 | |
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203 | mem_o =>sram.o, |
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204 | ct_out=>ct_out, |
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205 | pe_in=>pe_in, |
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206 | pe_out=>pe_out, |
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207 | ht_state=>ht_state); |
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208 | |
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209 | end generate; |
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210 | td: if use_dyn=1 generate |
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211 | HT_task:HT_dyn generic map(Task_id =>DestId) |
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212 | port map ( |
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213 | clk=>clk, |
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214 | reset=>ht_reset, |
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215 | en=>en_task, |
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216 | Interf_i =>Libr.i, |
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217 | Interf_o=>Libr.o, |
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218 | mem_i =>sram.i, |
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219 | mem_o =>sram.o, |
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220 | ct_out=>ct_out, |
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221 | pe_in=>pe_in, |
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222 | pe_out=>pe_out, |
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223 | ht_state=>ht_state); |
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224 | |
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225 | end generate; |
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226 | --================================================================ |
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227 | --MUX de la RAM |
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228 | |
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229 | Ram_mux: process (ramsel_i,pe_ram_addra,pe_ram_addrb,Core_ram_address_rd,Core_ram_address_wr, |
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230 | Core_ram_en,Core_ram_we,Core_ram_data_in,pe_ram_ena,pe_ram_enb,Ram_do, |
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231 | Pe_ram_din,Pe_ram_we ) |
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232 | begin |
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233 | case ramsel_i is |
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234 | |
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235 | when '1' => |
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236 | ram_addra <= Core_ram_address_wr ; |
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237 | ram_addrb <= Core_ram_address_rd ; |
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238 | ram_ena <= Core_ram_en; |
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239 | ram_enb <= Core_ram_en; |
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240 | ram_we<= Core_ram_we; |
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241 | ram_din <= Core_ram_data_in; |
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242 | pe_ram_do<=(others=>'U'); |
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243 | CRAM_DO<=ram_do; |
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244 | |
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245 | when others => |
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246 | ram_addra <= pe_ram_addra; |
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247 | ram_addrb <= pe_ram_addrb; |
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248 | ram_ena <= pe_ram_ena; |
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249 | ram_enb <= pe_ram_enb; |
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250 | ram_we<= pe_ram_we; |
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251 | ram_din <=pe_ram_din; |
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252 | CRAM_DO<=(others=>'0'); |
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253 | pe_ram_do<=ram_do; |
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254 | end case ; |
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255 | |
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256 | end process ; |
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257 | |
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258 | process(CRAM_DO) |
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259 | begin |
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260 | CORE_RAM_DATA_OUT<=CRAM_DO; |
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261 | end process; |
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262 | CORE_RAM_DATA_OUT2<=CRAM_DO; |
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263 | --Instruction_En<=PE_instr_EN; -- Libr.Instr_en; --********A changer ********** |
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264 | --=== !!!!! attention la suppression de la ligne ci-dessous empêche ce |
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265 | -- composant de bien fonctionner !!! !!!!!!!!!!!!!!!!!!!!!!! |
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266 | --instruction<=std_logic_vector(to_unsigned(Core_upper_adr,8)); |
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267 | |
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268 | dpid<=dpid_i; |
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269 | Lib_Instr_ack<=Core_Pushout(0); --l'instruction a été copié |
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270 | Lib_init<=Core_Pushout(4); -- Initialized |
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271 | Lib_Enable<=Core_Pushout(6);-- HT activée par la Librairie. |
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272 | Ex1_Run<=Core_Pushout(5); -- fin de l'exécution de Ex1 |
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273 | Ex4_Run<=Core_pushout(7); -- fin de l'exécution de Ex4 pour Spawn |
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274 | horloge_ht:process (reset,en_task,clk) |
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275 | begin |
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276 | if reset='1' then |
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277 | clk_ht<='0'; |
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278 | count<=0; |
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279 | Ht_reset<='1'; |
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280 | else |
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281 | if en_task='1' then |
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282 | clk_ht<=clk; |
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283 | if count=10 then --circuit de reset pour la HT |
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284 | ht_reset<='0'; |
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285 | else |
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286 | if rising_edge(clk) then |
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287 | count<=count+1; |
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288 | end if; |
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289 | ht_reset<='1'; |
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290 | end if; |
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291 | else |
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292 | count<=0; |
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293 | clk_ht<='0'; |
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294 | Ht_reset<='1'; |
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295 | end if; |
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296 | end if; |
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297 | end process horloge_ht; |
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298 | |
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299 | Hold1: Hold_fsm port map ( |
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300 | clk=>clk , |
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301 | reset =>reset, |
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302 | Ram_Busy=>Ram_busy, |
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303 | Hold_Ack=>Hold_Ack, |
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304 | Hold_req =>Core_Hold_Req, |
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305 | RamSel => RamSel_i); |
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306 | Core_Hold_Ack<=Hold_Ack; |
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307 | |
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308 | --================RAM signals ====================== |
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309 | sram.I.data_out<=PE_ram_do; |
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310 | --pe_Ram_addra<=sram.O.addr_wr; |
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311 | --pe_Ram_addrb<=sram.O.addr_rd ; |
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312 | --PE_Ram_we<=sram.O.we; |
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313 | --PE_Ram_ena<=sram.O.ena; |
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314 | --PE_Ram_enb<=sram.O.enb; |
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315 | --PE_ram_din<=sram.O.data_in; |
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316 | --==========MPI HCL signals ============================ |
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317 | --RAZ de la RAM de communication |
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318 | raz_ram: process(et_ht_ena,m_count,lib_enable,sram,reset,raz_en, |
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319 | en_task,Core_hold_req,RamSel_i,Core_pushout,Libr.O) |
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320 | --valeurs par défaut ! |
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321 | begin |
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322 | pe_Ram_addra<=sram.O.addr_wr; |
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323 | pe_Ram_addrb<=sram.O.addr_rd ; |
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324 | PE_Ram_we<=sram.O.we; |
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325 | PE_Ram_ena<=sram.O.ena; |
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326 | PE_Ram_enb<=sram.O.enb; |
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327 | PE_ram_din<=sram.O.data_in; |
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328 | |
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329 | Instruction<=Libr.O.Instruction; |
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330 | Instruction_en<=Libr.O.Instr_en; |
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331 | Libr.I.Instr_ack<=Core_pushout(0); |
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332 | Libr.I.InitOk<=Core_pushout(4); |
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333 | Libr.I.Spawned<=Lib_enable; |
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334 | Libr.I.Hold_Req<=Core_Hold_req; |
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335 | Libr.I.RamSel<=RamSel_i; |
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336 | en_task<='0'; |
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337 | raz_en<='0'; |
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338 | --************************************ |
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339 | case et_ht_ena is |
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340 | when ht_lock=> |
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341 | |
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342 | --si le HT n'est pas activé ces valeurs sont à 0 ! |
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343 | Instruction<=(others=>'0'); |
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344 | Ram_busy<='0'; |
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345 | PE_Instr_EN<='0'; |
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346 | when ht_raz => |
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347 | |
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348 | pe_Ram_addra<=std_logic_vector(to_unsigned(m_count,ADRLEN)); |
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349 | pe_Ram_addrb<=std_logic_vector(to_unsigned(m_count,ADRLEN)) ; |
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350 | PE_Ram_we<='1'; |
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351 | PE_Ram_ena<='1'; |
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352 | PE_Ram_enb<='1'; |
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353 | PE_ram_din<=(others=>'0'); |
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354 | raz_en<='1'; |
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355 | Libr.I.Instr_ack<='0'; |
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356 | Libr.I.InitOk<='0'; |
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357 | Libr.I.Spawned<=Lib_enable; |
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358 | Libr.I.Hold_Req<='1'; |
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359 | Libr.I.RamSel<='1'; |
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360 | when ht_stop => |
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361 | en_task<='0'; |
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362 | Instruction_en<='0'; |
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363 | when ht_on=> |
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364 | en_task<= '1'; --l'activation d'une HT peut être directe ou commandée |
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365 | |
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366 | Instruction<=Libr.O.Instruction; |
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367 | Instruction_en<=Libr.O.Instr_en; |
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368 | Ram_busy<=Libr.O.membusy; |
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369 | PE_Instr_EN<=Libr.O.instr_en; |
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370 | pe_Ram_addra<=sram.O.addr_wr; |
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371 | pe_Ram_addrb<=sram.O.addr_rd ; |
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372 | PE_Ram_we<=sram.O.we; |
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373 | PE_Ram_ena<=sram.O.ena; |
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374 | PE_Ram_enb<=sram.O.enb; |
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375 | PE_ram_din<=sram.O.data_in; |
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376 | |
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377 | assert not(Lib_enable='1') |
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378 | report "Spawn Activé" |
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379 | severity WARNING ; |
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380 | |
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381 | end case; |
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382 | |
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383 | end process; |
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384 | |
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385 | ht_ena_proc:process (clk,reset) |
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386 | begin |
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387 | if (clk'event and clk='1') then |
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388 | case et_ht_ena is |
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389 | when ht_lock=> |
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390 | if CE='1' then |
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391 | et_ht_ena<=ht_raz; |
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392 | elsif Lib_enable='1' then |
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393 | et_ht_ena<=ht_raz; |
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394 | else |
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395 | et_ht_ena<=ht_lock; |
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396 | end if; |
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397 | |
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398 | m_count<=core_base_adr; --adresse de base du Core MPI-HCL |
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399 | when ht_raz=> |
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400 | if m_count<core_base_adr+1023 then |
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401 | m_count<=m_count+1; |
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402 | else |
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403 | raz_en<='0'; |
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404 | m_count<=core_base_adr; |
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405 | et_ht_ena<=ht_on; |
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406 | end if; |
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407 | When ht_stop => |
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408 | if reset='1' then |
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409 | et_ht_ena<=ht_raz; |
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410 | elsif CE='1' or Lib_enable='1' then |
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411 | et_ht_ena<=ht_on; |
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412 | end if; |
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413 | when ht_on=> |
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414 | if reset='1' then |
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415 | et_ht_ena<=ht_lock; |
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416 | elsif CE='0' and Lib_enable='0' then |
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417 | et_ht_ena<=ht_stop; |
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418 | |
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419 | end if; |
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420 | end case; |
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421 | end if; |
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422 | end process ht_ena_proc; |
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423 | --======================================================================= |
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424 | --MAE du PE |
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425 | --======================================================================= |
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426 | |
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427 | |
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428 | end Behavioral; |
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429 | |
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