1 | -------------------------------------------------------------------------------- |
---|
2 | -- This file is owned and controlled by Xilinx and must be used solely -- |
---|
3 | -- for design, simulation, implementation and creation of design files -- |
---|
4 | -- limited to Xilinx devices or technologies. Use with non-Xilinx -- |
---|
5 | -- devices or technologies is expressly prohibited and immediately -- |
---|
6 | -- terminates your license. -- |
---|
7 | -- -- |
---|
8 | -- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY -- |
---|
9 | -- FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY -- |
---|
10 | -- PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE -- |
---|
11 | -- IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS -- |
---|
12 | -- MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY -- |
---|
13 | -- CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY -- |
---|
14 | -- RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY -- |
---|
15 | -- DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE -- |
---|
16 | -- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR -- |
---|
17 | -- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF -- |
---|
18 | -- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A -- |
---|
19 | -- PARTICULAR PURPOSE. -- |
---|
20 | -- -- |
---|
21 | -- Xilinx products are not intended for use in life support appliances, -- |
---|
22 | -- devices, or systems. Use in such applications are expressly -- |
---|
23 | -- prohibited. -- |
---|
24 | -- -- |
---|
25 | -- (c) Copyright 1995-2014 Xilinx, Inc. -- |
---|
26 | -- All rights reserved. -- |
---|
27 | -------------------------------------------------------------------------------- |
---|
28 | -------------------------------------------------------------------------------- |
---|
29 | -- You must compile the wrapper file mem8k8.vhd when simulating |
---|
30 | -- the core, mem8k8. When compiling the wrapper file, be sure to |
---|
31 | -- reference the XilinxCoreLib VHDL simulation library. For detailed |
---|
32 | -- instructions, please refer to the "CORE Generator Help". |
---|
33 | |
---|
34 | -- The synthesis directives "translate_off/translate_on" specified |
---|
35 | -- below are supported by Xilinx, Mentor Graphics and Synplicity |
---|
36 | -- synthesis tools. Ensure they are correct for your synthesis tool(s). |
---|
37 | |
---|
38 | LIBRARY ieee; |
---|
39 | USE ieee.std_logic_1164.ALL; |
---|
40 | -- synthesis translate_off |
---|
41 | LIBRARY XilinxCoreLib; |
---|
42 | -- synthesis translate_on |
---|
43 | ENTITY mem8k8 IS |
---|
44 | PORT ( |
---|
45 | clka : IN STD_LOGIC; |
---|
46 | ena : IN STD_LOGIC; |
---|
47 | wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0); |
---|
48 | addra : IN STD_LOGIC_VECTOR(12 DOWNTO 0); |
---|
49 | dina : IN STD_LOGIC_VECTOR(7 DOWNTO 0); |
---|
50 | clkb : IN STD_LOGIC; |
---|
51 | enb : IN STD_LOGIC; |
---|
52 | addrb : IN STD_LOGIC_VECTOR(12 DOWNTO 0); |
---|
53 | doutb : OUT STD_LOGIC_VECTOR(7 DOWNTO 0) |
---|
54 | ); |
---|
55 | END mem8k8; |
---|
56 | |
---|
57 | ARCHITECTURE mem8k8_a OF mem8k8 IS |
---|
58 | -- synthesis translate_off |
---|
59 | COMPONENT wrapped_mem8k8 |
---|
60 | PORT ( |
---|
61 | clka : IN STD_LOGIC; |
---|
62 | ena : IN STD_LOGIC; |
---|
63 | wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0); |
---|
64 | addra : IN STD_LOGIC_VECTOR(12 DOWNTO 0); |
---|
65 | dina : IN STD_LOGIC_VECTOR(7 DOWNTO 0); |
---|
66 | clkb : IN STD_LOGIC; |
---|
67 | enb : IN STD_LOGIC; |
---|
68 | addrb : IN STD_LOGIC_VECTOR(12 DOWNTO 0); |
---|
69 | doutb : OUT STD_LOGIC_VECTOR(7 DOWNTO 0) |
---|
70 | ); |
---|
71 | END COMPONENT; |
---|
72 | |
---|
73 | -- Configuration specification |
---|
74 | FOR ALL : wrapped_mem8k8 USE ENTITY XilinxCoreLib.blk_mem_gen_v6_2(behavioral) |
---|
75 | GENERIC MAP ( |
---|
76 | c_addra_width => 13, |
---|
77 | c_addrb_width => 13, |
---|
78 | c_algorithm => 1, |
---|
79 | c_axi_id_width => 4, |
---|
80 | c_axi_slave_type => 0, |
---|
81 | c_axi_type => 1, |
---|
82 | c_byte_size => 9, |
---|
83 | c_common_clk => 0, |
---|
84 | c_default_data => "0", |
---|
85 | c_disable_warn_bhv_coll => 0, |
---|
86 | c_disable_warn_bhv_range => 0, |
---|
87 | c_family => "virtex7", |
---|
88 | c_has_axi_id => 0, |
---|
89 | c_has_ena => 1, |
---|
90 | c_has_enb => 1, |
---|
91 | c_has_injecterr => 0, |
---|
92 | c_has_mem_output_regs_a => 0, |
---|
93 | c_has_mem_output_regs_b => 0, |
---|
94 | c_has_mux_output_regs_a => 0, |
---|
95 | c_has_mux_output_regs_b => 0, |
---|
96 | c_has_regcea => 0, |
---|
97 | c_has_regceb => 0, |
---|
98 | c_has_rsta => 0, |
---|
99 | c_has_rstb => 0, |
---|
100 | c_has_softecc_input_regs_a => 0, |
---|
101 | c_has_softecc_output_regs_b => 0, |
---|
102 | c_init_file_name => "no_coe_file_loaded", |
---|
103 | c_inita_val => "0", |
---|
104 | c_initb_val => "0", |
---|
105 | c_interface_type => 0, |
---|
106 | c_load_init_file => 0, |
---|
107 | c_mem_type => 1, |
---|
108 | c_mux_pipeline_stages => 0, |
---|
109 | c_prim_type => 1, |
---|
110 | c_read_depth_a => 8191, |
---|
111 | c_read_depth_b => 8191, |
---|
112 | c_read_width_a => 8, |
---|
113 | c_read_width_b => 8, |
---|
114 | c_rst_priority_a => "CE", |
---|
115 | c_rst_priority_b => "CE", |
---|
116 | c_rst_type => "SYNC", |
---|
117 | c_rstram_a => 0, |
---|
118 | c_rstram_b => 0, |
---|
119 | c_sim_collision_check => "ALL", |
---|
120 | c_use_byte_wea => 0, |
---|
121 | c_use_byte_web => 0, |
---|
122 | c_use_default_data => 0, |
---|
123 | c_use_ecc => 0, |
---|
124 | c_use_softecc => 0, |
---|
125 | c_wea_width => 1, |
---|
126 | c_web_width => 1, |
---|
127 | c_write_depth_a => 8191, |
---|
128 | c_write_depth_b => 8191, |
---|
129 | c_write_mode_a => "WRITE_FIRST", |
---|
130 | c_write_mode_b => "WRITE_FIRST", |
---|
131 | c_write_width_a => 8, |
---|
132 | c_write_width_b => 8, |
---|
133 | c_xdevicefamily => "virtex7" |
---|
134 | ); |
---|
135 | -- synthesis translate_on |
---|
136 | BEGIN |
---|
137 | -- synthesis translate_off |
---|
138 | U0 : wrapped_mem8k8 |
---|
139 | PORT MAP ( |
---|
140 | clka => clka, |
---|
141 | ena => ena, |
---|
142 | wea => wea, |
---|
143 | addra => addra, |
---|
144 | dina => dina, |
---|
145 | clkb => clkb, |
---|
146 | enb => enb, |
---|
147 | addrb => addrb, |
---|
148 | doutb => doutb |
---|
149 | ); |
---|
150 | -- synthesis translate_on |
---|
151 | |
---|
152 | END mem8k8_a; |
---|