1 | -------------------------------------------------------------------------------- |
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2 | -- |
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3 | -- BLK MEM GEN v6.2 Core - Top-level core wrapper |
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4 | -- |
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5 | -------------------------------------------------------------------------------- |
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6 | -- |
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7 | -- (c) Copyright 2006-2010 Xilinx, Inc. All rights reserved. |
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8 | -- |
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9 | -- This file contains confidential and proprietary information |
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10 | -- of Xilinx, Inc. and is protected under U.S. and |
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11 | -- international copyright and other intellectual property |
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12 | -- laws. |
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13 | -- |
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14 | -- DISCLAIMER |
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15 | -- This disclaimer is not a license and does not grant any |
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16 | -- rights to the materials distributed herewith. Except as |
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17 | -- otherwise provided in a valid license issued to you by |
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18 | -- Xilinx, and to the maximum extent permitted by applicable |
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19 | -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND |
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20 | -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES |
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21 | -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING |
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22 | -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- |
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23 | -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and |
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24 | -- (2) Xilinx shall not be liable (whether in contract or tort, |
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25 | -- including negligence, or under any other theory of |
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26 | -- liability) for any loss or damage of any kind or nature |
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27 | -- related to, arising under or in connection with these |
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28 | -- materials, including for any direct, or any indirect, |
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29 | -- special, incidental, or consequential loss or damage |
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30 | -- (including loss of data, profits, goodwill, or any type of |
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31 | -- loss or damage suffered as a result of any action brought |
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32 | -- by a third party) even if such damage or loss was |
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33 | -- reasonably foreseeable or Xilinx had been advised of the |
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34 | -- possibility of the same. |
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35 | -- |
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36 | -- CRITICAL APPLICATIONS |
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37 | -- Xilinx products are not designed or intended to be fail- |
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38 | -- safe, or for use in any application requiring fail-safe |
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39 | -- performance, such as life-support or safety devices or |
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40 | -- systems, Class III medical devices, nuclear facilities, |
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41 | -- applications related to the deployment of airbags, or any |
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42 | -- other applications that could lead to death, personal |
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43 | -- injury, or severe property or environmental damage |
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44 | -- (individually and collectively, "Critical |
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45 | -- Applications"). Customer assumes the sole risk and |
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46 | -- liability of any use of Xilinx products in Critical |
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47 | -- Applications, subject only to applicable laws and |
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48 | -- regulations governing limitations on product liability. |
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49 | -- |
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50 | -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS |
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51 | -- PART OF THIS FILE AT ALL TIMES. |
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52 | |
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53 | -------------------------------------------------------------------------------- |
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54 | -- |
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55 | -- Filename: bmg_wrapper.vhd |
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56 | -- |
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57 | -- Description: |
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58 | -- This is the actual BMG core wrapper. |
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59 | -- |
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60 | -------------------------------------------------------------------------------- |
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61 | -- Author: IP Solutions Division |
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62 | -- |
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63 | -- History: August 31, 2005 - First Release |
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64 | -------------------------------------------------------------------------------- |
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65 | -- |
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66 | -------------------------------------------------------------------------------- |
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67 | -- Library Declarations |
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68 | -------------------------------------------------------------------------------- |
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69 | |
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70 | LIBRARY IEEE; |
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71 | USE IEEE.STD_LOGIC_1164.ALL; |
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72 | USE IEEE.STD_LOGIC_ARITH.ALL; |
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73 | USE IEEE.STD_LOGIC_UNSIGNED.ALL; |
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74 | |
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75 | LIBRARY UNISIM; |
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76 | USE UNISIM.VCOMPONENTS.ALL; |
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77 | |
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78 | -------------------------------------------------------------------------------- |
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79 | -- Entity Declaration |
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80 | -------------------------------------------------------------------------------- |
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81 | ENTITY blk_mem_gen_v6_2_top IS |
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82 | PORT ( |
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83 | --Inputs - Port A |
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84 | ENA : IN STD_LOGIC; --opt port |
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85 | |
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86 | WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0); |
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87 | ADDRA : IN STD_LOGIC_VECTOR(12 DOWNTO 0); |
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88 | |
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89 | DINA : IN STD_LOGIC_VECTOR(7 DOWNTO 0); |
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90 | |
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91 | CLKA : IN STD_LOGIC; |
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92 | |
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93 | |
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94 | --Inputs - Port B |
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95 | ENB : IN STD_LOGIC; --opt port |
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96 | ADDRB : IN STD_LOGIC_VECTOR(12 DOWNTO 0); |
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97 | DOUTB : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); |
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98 | CLKB : IN STD_LOGIC |
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99 | |
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100 | ); |
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101 | |
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102 | END blk_mem_gen_v6_2_top; |
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103 | |
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104 | |
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105 | ARCHITECTURE xilinx OF blk_mem_gen_v6_2_top IS |
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106 | |
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107 | COMPONENT BUFG IS |
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108 | PORT ( |
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109 | I : IN STD_ULOGIC; |
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110 | O : OUT STD_ULOGIC |
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111 | ); |
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112 | END COMPONENT; |
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113 | |
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114 | COMPONENT blk_mem_gen_v6_2 IS |
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115 | PORT ( |
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116 | --Port A |
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117 | ENA : IN STD_LOGIC; --opt port |
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118 | |
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119 | WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0); |
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120 | ADDRA : IN STD_LOGIC_VECTOR(12 DOWNTO 0); |
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121 | |
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122 | DINA : IN STD_LOGIC_VECTOR(7 DOWNTO 0); |
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123 | |
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124 | |
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125 | CLKA : IN STD_LOGIC; |
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126 | |
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127 | |
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128 | --Port B |
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129 | ENB : IN STD_LOGIC; --opt port |
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130 | ADDRB : IN STD_LOGIC_VECTOR(12 DOWNTO 0); |
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131 | DOUTB : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); |
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132 | CLKB : IN STD_LOGIC |
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133 | |
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134 | |
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135 | ); |
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136 | END COMPONENT; |
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137 | |
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138 | SIGNAL CLKA_buf : STD_LOGIC; |
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139 | SIGNAL CLKB_buf : STD_LOGIC; |
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140 | SIGNAL S_ACLK_buf : STD_LOGIC; |
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141 | |
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142 | BEGIN |
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143 | |
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144 | bufg_A : BUFG |
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145 | PORT MAP ( |
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146 | I => CLKA, |
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147 | O => CLKA_buf |
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148 | ); |
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149 | |
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150 | bufg_B : BUFG |
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151 | PORT MAP ( |
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152 | I => CLKB, |
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153 | O => CLKB_buf |
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154 | ); |
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155 | |
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156 | |
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157 | bmg0 : blk_mem_gen_v6_2 |
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158 | PORT MAP ( |
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159 | --Port A |
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160 | ENA => ENA, |
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161 | |
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162 | WEA => WEA, |
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163 | ADDRA => ADDRA, |
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164 | |
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165 | DINA => DINA, |
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166 | |
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167 | CLKA => CLKA_buf, |
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168 | |
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169 | |
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170 | --Port B |
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171 | ENB => ENB, |
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172 | ADDRB => ADDRB, |
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173 | DOUTB => DOUTB, |
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174 | CLKB => CLKB_buf |
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175 | |
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176 | ); |
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177 | |
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178 | END xilinx; |
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