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46 | |
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47 | |
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48 | set device xc7a100tcsg324-3 |
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49 | set projName mem8k8 |
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50 | set design mem8k8 |
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51 | set projDir [file dirname [info script]] |
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52 | create_project $projName $projDir/results/$projName -part $device -force |
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53 | set_property design_mode RTL [current_fileset -srcset] |
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54 | set top_module mem8k8_top |
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55 | add_files -norecurse {../../example_design/mem8k8_top.vhd} |
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56 | add_files -norecurse {./mem8k8.edf} |
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57 | import_files -fileset [get_filesets constrs_1] -force -norecurse {../../example_design/mem8k8_top.xdc} |
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58 | set_property top mem8k8_top [get_property srcset [current_run]] |
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59 | synth_design |
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60 | opt_design |
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61 | place_design |
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62 | route_design |
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63 | set_param sta.dlyMediator true |
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64 | write_sdf -rename_top_module mem8k8_top -file routed.sdf |
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65 | write_verilog -nolib -mode sim -sdf_anno false -rename_top_module mem8k8_top routed.vhd |
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66 | report_timing -nworst 30 -path_type full -file routed.twr |
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67 | report_drc -file routed.drc |
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68 | #write_bitstream |
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