Context Navigation

← Previous Revision
Latest Revision
Next Revision →
Blame
Revision Log

EX1_FSM.vhd.bak @ 100

Last change on this file since 100 was 100, checked in by rolagamo, 10 years ago

File size: 47.5 KB

Line
1	----------------------------------------------------------------------------------
2	-- Company:
3	-- Engineer:GAMOM /KIEGAING
4	--
5	-- Create Date: 08:12:29 06/16/2011
6	-- Design Name:
7	-- Module Name: EX1_FSM - Behavioral
8	-- Project Name:
9	-- Target Devices:
10	-- Tool versions:
11	-- Description: Ce module est chargé de recevoir les instructions du programme MPI et
12	-- de les exécuter (PUT) il coopère avec EX2 qui reçoit les instructions venant du NoC
13	-- (GET)
14	--
15	-- Dependencies:
16	--
17	-- Revision: 09/07/2012
18	-- Revision 0.03 - File updated
19	-- Additional Comments:
20	--
21	----------------------------------------------------------------------------------
22	library IEEE;
23	use IEEE.STD_LOGIC_1164.ALL;
24	--use IEEE.STD_LOGIC_ARITH.ALL;
25	use IEEE.STD_LOGIC_UNSIGNED.ALL;
26	library NocLib ;
27	use Work.Packet_type.ALL;
28	USE ieee.numeric_std.ALL;
29
30
31	use NocLib.CoreTypes.all;
32	---- Uncomment the following library declaration if instantiating
33	---- any Xilinx primitives in this code.
34	--library UNISIM;
35	--use UNISIM.VComponents.all;
36
37	entity EX1_FSM is
38	-- parametres generiques du module :
39
40
41	Port (
42	--instruction_available : in STD_LOGIC;
43	clk : in STD_LOGIC;
44	reset : in STD_LOGIC;
45	instruction : in std_logic_vector(Word-1 downto 0);
46	instruction_en : in std_logic:='0'; -- active le module instruction
47	pid : in std_logic_vector(3 downto 0) ; -- id du processeur
48	nprocs : in std_logic_vector(3 downto 0);-- nombre de processeur du MPSOC - 1
49	Result : out STD_LOGIC_VECTOR (7 downto 0):=(others=>'0'); -- le résultat de l'exécution de ce module
50	Ready : out std_logic; --indique la fin de l'éxécution d'une instruction
51	AppInitReq :out STD_LOGIC:='0'; -- requête d'initialisation de l'application
52	AppInitAck :in STD_LOGIC; -- Acquitement d'initialisation
53	Initialized:in std_logic ; -- état de la Lib
54	-- Accès au Fifo d'instructions
55	priority_rotation : out STD_LOGIC:='0';
56	fifo_rd_en : out STD_LOGIC:='0';
57	fifo_empty : in STD_LOGIC;
58	fifo_data_out : in STD_LOGIC_VECTOR (7 downto 0);
59	fifo_src : in STD_LOGIC; --permet de désigner le fifo qui est en service
60
61
62	Snd_Data : IN Typ_PortIO(0 to 3);
63	Snd_Start : IN std_logic;
64	Snd_Ack : OUT std_logic;
65
66	-- Accès au réseau sur puce
67	switch_port_in_full : in std_logic;
68	switch_port_in_data : out STD_LOGIC_VECTOR (7 downto 0):=(others=>'0');
69	switch_port_in_wr_en : out STD_LOGIC:='0';
70	-- Accès à la mémoire RAM du PE
71	ram_data_in : in std_logic_vector(7 downto 0);
72	ram_data_out : out std_logic_vector(7 downto 0):=(others=>'0');
73	ram_rd,ram_wr : out std_logic:='0';
74	ram_address : out std_logic_vector(15 downto 0):=(others=>'0');
75
76	dma_wr_request : OUT std_logic:='0';
77	dma_rd_request : OUT std_logic:='0';
78	dma_wr_grant : in STD_LOGIC;
79	dma_rd_grant : in STD_LOGIC);
80	end EX1_FSM;
81
82	architecture Behavioral of EX1_FSM is
83
84	component proto_send is
85	generic (sizemem : natural := 64);
86	port (
87	clk,reset : in std_logic;
88	fifo_in_empty,fifo_in_full : in std_logic; --signaux pour le fifo d'entrée
89	fifo_out_empty,fifo_out_full : in std_logic; --signaux pour le fifo de sortie
90	fifo_out_wr_en : out std_logic:='0'; --écriture autorisée dans la fifo de sortie
91	fifo_in_rd_en : out std_logic:='0'; --lecture autorisée dans la fifo d'entrée
92	fifo_in_data_out : in std_logic_vector(Word-1 downto 0);
93	fifo_out_data_in : out std_logic_vector(Word-1 downto 0);
94	packet_len : in std_logic_vector(Word-1 downto 0); --la longueur du paquet
95	copy_mode : in std_logic; --Fifo_to_mem ou Fifo_to_fifo
96	snd_start : in std_logic; --début de la réception
97	snd_ack :in std_logic; -- acquittement de la réception
98	snd_comp : out std_logic; -- fin de la réception
99	mem :in memory(0 to sizemem-1)); --données à copier vers le fifo
100
101
102	end component proto_send;
103	-- definition du type etat pour le codage des etats des fsm
104	type fsm_states is (fifo_select, fetch_packet_type, decode_packet_type, fetch_addresses,
105	decode_packet_type2, read_status1,read_status2,ex1_barrier1, ex1_barrier2, ex1_barrier3, ex1_barrier4,
106	ex1_get1, ex1_get2,ex1_get3,ex1_get4, ex1_put1, ex1_put2, ex1_put3, ex1_put4,ex1_put5,
107	ex1_init1,ex1_init_run,ex1_init2,ex1_init3,ex1_spawn,ex1_ready,ex1_send_ack,ex1_Wsync);
108	-- machine a etat du module
109	signal ex1_state,Next_Ex1_state : fsm_states;
110
111	-- les variables utilisées dans la fsm
112	signal snd_start1,snd_start_sync,snd_comp,snd_ack1,push:std_logic:='0';
113	signal mem,mem_i : memory(0 to 3);
114	signal data_to_send,data_to_send_i,result_i,result1,noc_fifo_in : std_logic_vector(Word-1 downto 0);
115	signal packet_type,packet_type_i : std_logic_vector(3 downto 0);
116	--signal dpid : std_logic_vector(3 downto 0);
117	signal pid_counter,pid_counter_i : std_logic_vector(3 downto 0);
118	signal p_len,p_len_i: std_logic_vector(Word-1 downto 0);
119	signal src_address,src_address_i : std_logic_vector(ADRLEN-1 downto 0);
120	signal dma_rd,dma_wr,Wr_ok,rd_ok:std_logic:='0';
121	--signal res_address : std_logic_vector(15 downto 0);
122	signal dest_address,dest_address_i : std_logic_vector(ADRLEN-1 downto 0);
123	signal n,n_i : natural range 0 to 15;
124	signal len,len_i : natural range 0 to 255;
125	signal fifo_rd,fifo_wr,fifo_copy:std_logic:='0';
126	signal fifo_sel:std_logic:='0';
127	signal run_init,run_init_i:std_logic:='0';
128	begin
129	-- connection des signaux avec les ports
130	ram_address <= src_address;
131	result<=Result1;
132	sw_send: proto_send generic map (sizemem=>4)
133	port map (
134	clk=>clk,
135	reset=>reset,
136	fifo_in_empty=>fifo_empty,
137	fifo_in_full=>'0',--pas utilisé
138	fifo_out_empty=>'0',
139	packet_len=>p_len,
140	copy_mode=>fifo_copy,
141	fifo_out_full => switch_port_in_full,
142	fifo_in_rd_en=>fifo_rd,
143	fifo_in_data_out=>fifo_data_out,
144	fifo_out_wr_en =>fifo_wr,
145
146	fifo_out_data_in =>noc_fifo_in,
147	snd_start =>snd_start_sync,
148	snd_ack =>snd_ack1,
149	snd_comp=>snd_comp,
150	mem =>mem
151	);
152	ex1_fsm_sync:process(clk)
153
154	begin
155	if rising_edge(clk) then
156	if reset = '1' then
157	ex1_state <= fifo_select;
158	n<=0;
159	len<=0;
160	p_len<=(others=>'0');
161	snd_ack<='0';
162	src_address<=(others=>'0');
163	dest_address<=(others=>'0');
164	run_init<='0';
165	else
166	ex1_state<=next_ex1_state;
167	n<=n_i;
168	len<=len_i;
169	p_len<=p_len_i;
170	dest_address<=dest_address_i;
171	Packet_type<=Packet_type_i;
172	Pid_counter<=Pid_counter_i;
173	Data_to_send<=Data_to_send_i;
174	Result1<=Result_i;
175	run_init<=Run_init_i;
176	for i in 0 to 3 loop
177	mem(i)<=mem_i(i);
178	end loop;
179	src_address <= src_address_i;
180	snd_ack<=snd_ack1; --acquittement de l'envoie des données pour EX4
181	snd_start_sync<=snd_start1;
182	end if;
183	end if;
184	end process ex1_fsm_sync;
185	-- processus de transistion entre les etats
186	fsm_nst_logic : process(ex1_state,n,instruction_en,fifo_empty,fifo_data_out, switch_port_in_full,pid,
187	pid_counter,len,p_len,snd_start,snd_comp, ram_data_in,dma_rd_grant,dma_wr_grant,AppInitAck,src_address,
188	fifo_src,dest_address,packet_type,mem,snd_data,run_init,data_to_send)
189	variable tempval : std_logic_vector(Word-1 downto 0);
190	variable onepop,fifo_vide : std_logic:='0'; --indique que le fifo a été dépilé
191	begin
192	snd_ack1<='0';
193	fifo_copy<='0';
194	snd_start1<='0';
195	n_i<=n; --valeur par défaut
196	Next_ex1_state <=Ex1_state;
197	Src_address_i<=src_address;
198	dest_address_i<=dest_address;
199	P_len_i<=P_len;
200	Packet_type_i<=Packet_type;
201	Pid_counter_i<=Pid_counter;
202	run_init_i<=Run_init;
203	Len_i<=Len;
204	Data_to_send_i<=Data_to_send;
205	dma_rd<='0'; --attention ceci peut changer le code
206	dma_wr<='0'; --il faut donc le vérifier
207	for i in 0 to 3 loop
208	mem_i(i)<=mem(i);
209	end loop;
210	case ex1_state is
211	when fifo_select => if instruction_en='1' and fifo_empty ='0' then
212	Next_ex1_state <= fetch_packet_type;
213	else
214	Next_ex1_state <= fifo_select;
215	end if;
216	rd_ok<='0';
217	wr_ok<='0';
218	if instruction_en='1' and snd_start='1' then
219	run_init_i<='1';
220	Next_ex1_state<=ex1_init_run;
221	else
222	run_init_i<='0';
223	end if;
224	--lecture du registre status de la mib MPI
225	when read_status1 => if dma_rd_grant = '1' then -- fin du mpi_put
226	Next_ex1_state <= read_status2;
227	else
228	Next_ex1_state <= read_status1;
229	end if;
230	src_address_i<=std_logic_vector(to_unsigned(core_base_adr,16));
231	when read_status2 =>
232	Next_ex1_state <= fifo_select;
233	when fetch_packet_type => rd_ok<='0';
234	if fifo_empty ='1' then
235	Next_ex1_state <= fifo_select;
236	else
237	packet_type_i <= fifo_data_out(7 downto 4);
238	data_to_send_i <= fifo_data_out;
239	Next_ex1_state <= decode_packet_type;
240	rd_ok<='1';
241	end if;
242	when decode_packet_type => rd_ok<='0';
243	if fifo_empty='0' then
244	if packet_type = MPI_PUT then
245	p_len_i <= fifo_data_out + 4;
246	n_i <= 0;rd_ok<='1';
247	Next_ex1_state <= fetch_addresses;
248	elsif packet_type = MPI_GET then
249	len_i <= to_integer(unsigned(fifo_data_out));
250	p_len_i <= fifo_data_out;
251	n_i <= 0; rd_ok<='1';
252	Next_ex1_state <= fetch_addresses;
253	elsif packet_type = MPI_BARRIER_REACHED or packet_type = MPI_BARRIER_COMPLETED then
254	p_len_i <= "00000011"; -- = 3
255	pid_counter_i <= "0000";
256	rd_ok<='1';
257	Next_ex1_state <= ex1_barrier1;
258	elsif packet_type = MPI_INIT then
259	Next_ex1_state<=ex1_init1;
260	len_i <= to_integer(unsigned(fifo_data_out));
261	p_len_i<=fifo_data_out;
262	n_i<=0;rd_ok<='1';
263	elsif packet_type = MPI_ACK then
264	len_i <= to_integer(unsigned(fifo_data_out));
265	p_len_i<=fifo_data_out;
266	n_i <= 0; rd_ok<='0';
267	Next_ex1_state <= ex1_send_Ack;
268	elsif packet_type = MPI_WIN_SYNC then
269	len_i <= to_integer(unsigned(fifo_data_out));
270	p_len_i<=fifo_data_out;
271	n_i <= 0; rd_ok<='0';
272	Next_ex1_state <= ex1_WSynC;
273	elsif packet_type = MPI_SPAWN then
274	Next_ex1_state<=ex1_SPAWN;
275	len_i <= to_integer(unsigned(fifo_data_out));
276	p_len_i<=fifo_data_out;
277	onepop:='1';--il y a une donnée lue
278	src_address_i<=std_logic_vector(to_unsigned(Core_spawn_adr+1,16));
279	rd_ok<='0';
280	else -- packet non reconnu
281	--synthesis translate_off
282	report "Ex1 : ATTENTION paquet non reconnu !!!!!!!!!" ;
283	--synthesis translate_on
284	if fifo_empty = '1' then
285	Next_ex1_state <= fifo_select;
286
287	else
288	rd_ok<='1';
289	packet_type_i <= fifo_data_out(7 downto 4); --lire le prochain paquet
290	data_to_send_i <= fifo_data_out;
291	Next_ex1_state <= decode_packet_type;-- pas necessaire mais plus sure
292	end if;
293	end if;
294	end if;
295	when fetch_addresses => n_i<=n;rd_ok<='1';
296	if fifo_empty = '0' and n = 0 then
297	src_address_i(15 downto 8) <= fifo_data_out;
298	n_i <= n + 1;
299	Next_ex1_state <= fetch_addresses;
300	elsif fifo_empty = '0' and n = 1 then
301	src_address_i(7 downto 0) <= fifo_data_out;
302	n_i <= n + 1;
303	Next_ex1_state <= fetch_addresses;
304	elsif fifo_empty = '0' and n = 2 then
305	dest_address_i(15 downto 8) <= fifo_data_out;
306	n_i <= n + 1;
307	Next_ex1_state <= fetch_addresses;
308	elsif fifo_empty = '0' and n = 3 then
309	dest_address_i(7 downto 0) <= fifo_data_out;
310	n_i <= n+1;
311	elsif n=4 then
312	rd_ok<='0';
313	n_i<=0;
314	Next_ex1_state <= decode_packet_type2;
315	elsif fifo_empty='1' then
316	rd_ok<='0';
317	Next_ex1_state <= fetch_addresses; --attendre les données manquantes
318	else
319	Next_ex1_state <= fifo_select;
320	end if;
321	when decode_packet_type2 => if packet_type = MPI_PUT then
322	Next_ex1_state <= ex1_put1;
323	elsif packet_type = MPI_GET then
324	Next_ex1_state <= ex1_get1;
325	end if;
326	-- execution du mpi put
327	when ex1_put1 => if dma_rd_grant = '1' then
328	Next_ex1_state <= ex1_put2;
329	else
330	Next_ex1_state <= ex1_put1;
331	end if;
332	Wr_ok<='0';
333	when ex1_put2 =>Wr_ok<='0';
334	if switch_port_in_full = '0' and n = 0 then
335	--envoie du code MPI_PUT
336	n_i<= n + 1;
337	wr_ok<='0';
338	Next_ex1_state <= ex1_put2;
339	elsif switch_port_in_full = '0' and n = 1 then
340	data_to_send_i <= p_len;
341	n_i<= n + 1;
342	wr_ok<='1';
343	Next_ex1_state <= ex1_put2;
344	elsif switch_port_in_full = '0' and n = 2 then
345	data_to_send_i <= dest_address(15 downto 8);
346	n_i<= n + 1;
347	wr_ok<='1';
348	Next_ex1_state <= ex1_put2;
349	elsif switch_port_in_full = '0' and n = 3 then
350	data_to_send_i <= dest_address(7 downto 0);
351	n_i<= n +1;
352	wr_ok<='1';
353	Next_ex1_state <= ex1_put2;
354	elsif switch_port_in_full = '0' and n = 4 then
355	p_len_i <= p_len - 4;
356	-- Next_ex1_state <= ex1_put3;
357	Wr_ok<='0';
358	n_i<=n+1;
359	elsif n=5 and dma_rd_grant='1' then
360	Next_ex1_state <= ex1_put3;
361	n_i<=0;
362	Wr_ok<='1';
363	else
364	Next_ex1_state <= ex1_put2;
365	end if;
366	when ex1_put3 => wr_ok<='0';
367	if unsigned(p_len)>0 then
368	--if n=0 then
369	-- n_i<=1; --cycle d'attente pour la RAM
370	-- Wr_ok<='0';
371	-- elsif n=1 then
372	if switch_port_in_full = '0' then
373	if n=1 then --creer un délai sur ces signaux par rapport à src_adress
374	p_len_i <= p_len - 1;
375	Wr_Ok<='1';
376	end if;
377	n_i<=1;
378	src_address_i <= src_address+1;
379	Next_ex1_state <= ex1_put3;
380
381
382	else
383	Wr_Ok<='0';
384	src_address_i <= src_address;
385	n_i<=0;
386	end if;
387	--elsif n=2 then
388	-- n_i<=0; --cycle d'attente pour la RAM
389	-- Wr_ok<='0';
390	-- src_address_i <= src_address ; --prochaine lecture
391	--
392	-- end if;
393	else
394	Wr_Ok<='0';
395	Next_ex1_state <= ex1_put4;
396	end if;
397	when ex1_put4 =>rd_ok<='1';
398	wr_ok<='0';
399	if dma_rd_grant = '1' then -- fin du mpi_put
400	Next_ex1_state <= ex1_put5;
401	rd_ok<='0';
402	n_i<=0;
403	data_to_send_i<="00000001";
404	else
405	Next_ex1_state <= ex1_put4;
406	end if;
407
408	if fifo_src='0' then --détection Put ou Get
409	src_address_i<=std_logic_vector(to_unsigned(core_base_adr+5,16));
410	else
411	src_address_i<=std_logic_vector(to_unsigned(core_base_adr+4,16));
412	end if;
413	when ex1_put5 => if n >0 then
414
415	dma_wr<='1'; --demander un accès exclusif au bus
416	dma_rd<='1'; -- pour éviter une mauvaise mise à jour des données
417	else
418	dma_wr<='0';
419	dma_rd<='0';
420	end if;
421	rd_ok<='0';wr_ok<='0';
422	if n=0 then
423
424	n_i<=n+1;
425	elsif n=1 then
426	if dma_rd_grant='1' then
427	n_i<=n+1;
428
429	end if;
430	rd_ok<='1';
431	wr_ok<='0';
432	dma_wr<='1';
433	dma_rd<='1';
434	elsif n=2 then
435	if dma_rd_grant='1' then
436	n_i<=n+1;
437	dma_wr<='1';
438	tempval:=Ram_data_in;
439	data_to_send_i<=ram_data_in;
440	end if;
441	rd_ok<='1';
442	wr_ok<='0';
443
444	dma_rd<='1';
445	elsif n=3 then
446	dma_rd<='1';
447	if dma_rd_grant='1' and dma_wr_grant='1' then
448	n_i<=n+1;
449	tempval:=Ram_data_in;
450	data_to_send_i<=ram_data_in;
451	--src_address_i<=std_logic_vector(to_unsigned(core_base_adr+5,16));
452	tempval(5):='1'; -- SET du bit DSENT
453	data_to_send_i(5)<='1';
454	if fifo_src='0' then -- c'est un put qui est exécuté
455	tempval(5):='1'; -- SET du bit DSENT
456	--data_to_send_i<=ram_data_in or "00100000";
457	else -- c'est un Get qui est exécuté
458	--tempval(2):='1'; -- ne pas annuler le sending après un GET
459	--data_to_send_i<=ram_data_in or "00000100";
460	end if;
461	--data_to_send_i<=tempval; --A tester
462	rd_ok<='0';
463	wr_ok<='1';
464	dma_wr<='1';
465	dma_rd<='1';
466	else
467	rd_ok<='1';
468	wr_ok<='0';
469	dma_rd<='0'; --libérer le bus et revenir en arrière
470	dma_wr<='0';
471	n_i<=0;
472	end if;
473	elsif n=3 then
474	if dma_wr_grant = '1' and dma_rd_grant='1' then
475	n_i<=n+1;
476
477	--src_address_i<=std_logic_vector(to_unsigned(core_base_adr+5,16));
478	end if;
479	rd_ok<='0';
480	wr_ok<='1';
481	dma_wr<='1';
482	dma_rd<='1';
483	elsif n=4 then
484	if dma_wr_grant = '1' and dma_rd_grant='1' then
485	n_i<=n+1;
486
487	src_address_i<=std_logic_vector(to_unsigned(core_put_adr+6,16));
488
489	end if;
490	rd_ok<='0';
491	wr_ok<='1';
492	dma_wr<='1';
493	dma_rd<='1';
494	elsif n=5 then
495	if dma_wr_grant = '1' then
496	n_i<=n+1;
497
498	-- SET du bit DSENT
499	data_to_send_i<="00000001";
500	end if;
501	rd_ok<='0';
502	wr_ok<='1';
503	dma_wr<='1';
504	dma_rd<='0';
505	elsif n=6 then
506	n_i<=0;
507	Next_ex1_state <= fifo_select;
508	rd_ok<='0';
509	wr_ok<='0';
510	dma_wr<='0';
511	dma_rd<='0';
512	end if;
513
514
515	when ex1_get1 => wr_ok<='0';
516	if switch_port_in_full = '0' and n = 0 then -- execution du mpi get
517	--écrire l'entête de la fonction
518	n_i<= n + 1;
519	Wr_ok<='0';
520	Next_ex1_state <= ex1_get1;
521	elsif switch_port_in_full = '0' and n = 1 then -- execution du mpi get
522	data_to_send_i <= "00001000"; -- longueur du paquet sur le réseau ?
523	n_i<= n + 1;
524	Wr_ok<='1';
525	Next_ex1_state <= ex1_get1;
526	elsif switch_port_in_full = '0' and n = 2 then
527	data_to_send_i <= "0000"&pid; -- Rang source
528	n_i<= n + 1;
529	Wr_ok<='1';
530	Next_ex1_state <= ex1_get1;
531	elsif switch_port_in_full = '0' and n = 3 then
532	data_to_send_i <= p_len;
533	n_i<= n + 1;
534	Wr_ok<='1';
535	Next_ex1_state <= ex1_get1;
536	elsif switch_port_in_full = '0' and n = 4 then
537	data_to_send_i <= src_address(15 downto 8);
538	n_i<= n + 1;
539	Wr_ok<='1';
540	Next_ex1_state <= ex1_get1;
541	elsif switch_port_in_full = '0' and n = 5 then
542	data_to_send_i <= src_address(7 downto 0);
543	n_i<= n + 1;
544	Wr_ok<='1';
545	Next_ex1_state <= ex1_get1;
546	elsif switch_port_in_full = '0' and n = 6 then
547	data_to_send_i <= dest_address(15 downto 8);
548	n_i<= n + 1;
549	Wr_ok<='1';
550	Next_ex1_state <= ex1_get1;
551	elsif switch_port_in_full = '0' and n = 7 then
552	data_to_send_i <= dest_address(7 downto 0);
553	n_i<= n + 1;
554	Wr_ok<='1';
555	Next_ex1_state <= ex1_get1;
556	elsif switch_port_in_full = '0' and n = 8 then
557	Next_ex1_state <= ex1_get2;
558	n_i<=0;
559	Wr_ok<='1';
560	else
561	Next_ex1_state <= ex1_get1;
562	end if;
563	when ex1_get2 => if dma_wr_grant = '1' then
564	Next_ex1_state <= ex1_get3;
565	src_address_i<=std_logic_vector(to_unsigned(core_get_adr+6,16));
566	data_to_send_i<="00000001";
567	else
568	Next_ex1_state <= ex1_get2;
569	end if;
570	dma_wr<='1';
571	when ex1_send_ack \|ex1_Wsync=> rd_ok<='0';
572	if n = 0 then -- execution du mpi ack /ou Mpi_Win_sync
573	if switch_port_in_full = '0' then
574
575	wr_Ok<='0'; --envoie de la première donnée(code ack)
576	n_i<= n + 1;
577	onepop:='0';
578
579	end if;
580	elsif n = 1 then
581	if fifo_empty='0' and onepop='0' then
582	data_to_send_i <=p_len ;
583
584	rd_Ok<='1'; --passe la longueur
585	onepop:=not onepop; --une donnée lue il faut arrêter de dépiler
586
587	else
588	rd_Ok<='0';
589	end if;
590
591	if (switch_port_in_full = '0') and onepop='1' then wr_ok<='1';
592	onepop:=not onepop;
593	n_i<= n + 1;
594	wr_ok<='1';
595	elsif (switch_port_in_full = '1') then
596	wr_Ok<='0';
597
598	end if;
599
600	elsif (n= 2) then
601	if fifo_empty='0' and onepop='0' then
602
603	data_to_send_i <=fifo_data_out;
604	rd_Ok<='1';
605	onepop:=not onepop; --une donnée lue il faut arrêter de dépiler
606
607	else
608	rd_Ok<='0';
609	end if;
610
611	if (switch_port_in_full = '0') and onepop='1' then wr_ok<='1';
612	onepop:=not onepop;
613	n_i<= n + 1;
614	wr_ok<='1';
615	else
616	wr_Ok<='0';
617
618	end if;
619	elsif (n= 3) then
620	if fifo_empty='0' and onepop='0' then
621
622	data_to_send_i <=fifo_data_out;
623	rd_Ok<='1';
624	onepop:=not onepop; --une donnée lue il faut arrêter de dépiler
625
626	else
627	rd_Ok<='0';
628	end if;
629
630	if (switch_port_in_full = '0') and onepop='1' then wr_ok<='1';
631	onepop:=not onepop;
632	n_i<= n + 1;
633	wr_ok<='1';
634
635	else
636	wr_Ok<='0';
637
638	end if;
639	elsif n = 4 then
640	n_i<=0;
641	Wr_Ok<='1';
642	rd_ok<='0';--vider le tampon
643	Next_ex1_state <= fifo_select;
644
645	end if;
646
647	when ex1_get3 =>if n<2 then --ecriture de la fin d'envoie
648	if dma_wr_grant = '1' then -- fin du post de mpi_get
649
650	n_i<=n+1;
651	data_to_send_i<="00000001";
652	wr_ok<='1';
653	rd_ok<='0';
654	end if;
655
656	elsif n=2 then
657	n_i<=0;
658	Next_ex1_state <= ex1_get4;
659	end if;
660	src_address_i<=std_logic_vector(to_unsigned(core_get_adr+6,16));
661	when ex1_get4 => wr_ok<='0';
662	rd_ok<='0';
663	dma_wr<='1';
664	dma_rd<='1';
665	src_address_i<=std_logic_vector(to_unsigned(core_base_adr+5,16));
666
667	if n=0 then
668
669	if dma_rd_grant='1' then
670	n_i<=n+1;
671
672	end if;
673	rd_ok<='1';
674	wr_ok<='0';
675
676	elsif n=1 then
677	src_address_i<=std_logic_vector(to_unsigned(core_base_adr+5,16));
678	if dma_rd_grant='1' then
679	n_i<=n+1;
680
681	end if;
682	rd_ok<='1';
683	wr_ok<='0';
684
685	elsif n=2 then
686	if dma_rd_grant='1' then
687	n_i<=n+1;
688	rd_ok<='1';
689	src_address_i<=std_logic_vector(to_unsigned(core_base_adr+5,16));
690	else
691	n_i<=1;
692	end if;
693
694	elsif n=3 then
695	if dma_rd_grant='1' and dma_wr_grant='1' then
696	n_i<=n+1;
697	tempval:=Ram_data_in;
698	data_to_send_i<=Ram_data_in;
699	rd_ok<='1';
700	wr_ok<='0';
701	dma_wr<='1';
702	dma_rd<='1';
703	else
704	dma_wr<='0';
705	dma_rd<='0';
706	n_i<=n-1;
707	end if;
708	src_address_i<=std_logic_vector(to_unsigned(core_base_adr+5,16));
709	elsif n=4 then
710	if dma_wr_grant = '1' and dma_rd_grant='1' then
711	n_i<=n+1;
712	rd_ok<='0';
713	wr_ok<='1';
714	tempval(6):='1'; --SET du bit Windows Busy --car réception Get
715	tempval(1):='1'; -- SET du bit DReceiving
716	data_to_send_i(6)<='1';
717	data_to_send_i(1)<='1';
718	--data_to_send_i<=tempval; -- à tester absolument !!!
719	else
720	rd_ok<='0';
721	wr_ok<='1';
722	n_i<=1;
723	end if;
724	dma_wr<='1';
725	dma_rd<='1';
726	elsif n=5 then
727	wr_ok<='1';
728	if dma_wr_grant = '1' then
729	n_i<=n+1;
730	end if;
731	elsif n=6 then
732	n_i<=0;
733	Next_ex1_state <= fifo_select;
734	dma_wr<='0';
735	dma_rd<='0';
736	end if;
737
738	when ex1_spawn => rd_ok<='0';
739	if n = 0 then -- execution du mpi spawn
740	if switch_port_in_full = '0' then
741
742	wr_Ok<='0';
743	n_i<= n + 1;
744	onepop:='0';
745	--data_to_send_i<=len;
746	end if;
747	elsif n = 1 then
748	if fifo_empty='0' and onepop='0' then
749	data_to_send_i <=p_len ;
750
751	rd_Ok<='1';
752	onepop:='1'; --une donnée lue il faut arrêter de dépiler
753
754	end if;
755
756	if (switch_port_in_full = '0') and onepop='1' then wr_ok<='1';
757	onepop:='0';
758	n_i<= n + 1;
759	wr_ok<='1';
760	else
761	wr_Ok<='0';
762
763	end if;
764
765	elsif (n= 2) or (n=3) then
766	if fifo_empty='0' and onepop='0' then
767
768	data_to_send_i <=fifo_data_out;
769	rd_Ok<='1';
770	onepop:='1'; --une donnée lue il faut arrêter de dépiler
771
772	end if;
773
774	if (switch_port_in_full = '0') and onepop='1' then wr_ok<='1';
775	onepop:='0';
776	n_i<= n + 1;
777	wr_ok<='1';
778	else
779	wr_Ok<='0';
780
781	end if;
782	elsif n=4 then
783	n_i<=0;
784	Wr_Ok<='1';
785	rd_ok<='0';
786	Next_ex1_state <= fifo_select;
787	end if;
788	-- execution du barrier
789	when ex1_barrier1 => if switch_port_in_full = '0' then
790	Next_ex1_state <= ex1_barrier2;
791	else
792	Next_ex1_state <= ex1_barrier1;
793	end if;
794	when ex1_barrier2 => if switch_port_in_full = '0' then
795	Next_ex1_state <= ex1_barrier3;
796	else
797	Next_ex1_state <= ex1_barrier2;
798	end if;
799	when ex1_barrier3 => if switch_port_in_full = '0' then
800	Next_ex1_state <= ex1_barrier4;
801	else
802	Next_ex1_state <= ex1_barrier3;
803	end if;
804	when ex1_barrier4 => if packet_type = MPI_BARRIER_COMPLETED and pid_counter < nprocs then
805	pid_counter_i <= pid_counter + 1;
806	Next_ex1_state <= ex1_barrier1;
807	else
808	Next_ex1_state <= fifo_select;
809	end if;
810	when ex1_init1 => rd_ok<='0';
811	if n=0 then
812	n_i<=n+1;
813	Len_i<=len-2; --deux données a été dépilée
814	elsif n=1 then --vider le fifo instruction
815	if len>0 then
816	if fifo_empty='0' then
817	rd_ok<='1';
818	Len_i<=len-1;
819
820	else
821	rd_ok<='0';
822	Len_i<=Len;
823	end if;
824	else
825	n_i<=n+1;
826	end if;
827	elsif n=2 then --
828	n_i<=0;
829	rd_ok<='0';
830	Next_ex1_state<=ex1_init_run;
831
832	end if;
833
834	when ex1_init_run=> if n=0 then
835	if snd_start='1' then --le module ex4 veut envoyer des données
836
837	n_i<=n+1;
838
839	for i in 0 to 3 loop
840	mem_i(i)<=snd_data(i);
841	end loop;
842	if snd_data(0)(7 downto 4)=MPI_INIT or
843	snd_data(0)(7 downto 4)=MPI_SPAWN or
844	snd_data(0)(7 downto 4)=MPI_ACK then
845
846	else
847	report "Ex1 : Une instruction inconnue a été envoyé par Ex4 sur le réseau !";
848	end if;
849	P_len_i<=x"04";
850	fifo_copy<='0';
851	snd_ack1<='0';
852
853	end if;
854	if AppInitAck='1' then
855	Next_ex1_state<=ex1_init2;
856	end if;
857	elsif n=1 then
858	fifo_sel<='0';--pas de rotation du fifo instruction
859	snd_start1<='1';
860	P_len_i<=x"04";
861	fifo_copy<='0';
862	snd_ack1<='0';
863
864	n_i<=n+1;
865	elsif n=2 then
866	snd_start1<='1';
867	if snd_comp='1' then
868	snd_ack1<='1';
869
870	snd_start1<='0';
871	n_i<=n+1;
872	end if;
873	elsif n=3 then
874	snd_start1<='0';
875	snd_ack1<='1';
876	fifo_sel<='0';
877	if snd_start='0' then --attente l'annulation de l'envoie
878	n_i<=0;
879	snd_ack1<='0';
880	if run_init='1' then
881	Next_EX1_state<=fifo_select;
882	--run_init<='0';
883	end if;
884	end if;
885	end if;
886
887
888	when ex1_init2 => -- écriture dans le registre status reg.
889	src_address_i<=std_logic_vector(to_unsigned(core_base_adr,16));
890	if n=0 then --envoie du message Spawn Ack sur le réseau
891	if instruction(6)='1' then --Spawned=1 ?
892	n_i<=1; --envoie du message Spawn à main lib
893	data_to_send_i<="01010000"; --init+spawn
894	else
895	n_i<=4; --écrire le résultat de la fn
896	data_to_send_i<="00010000"; --init seul
897	end if;
898
899	elsif n=1 then
900	n_i<=n+1;
901	mem_i(0)<=MPI_INIT & x"0"; --répondre au premier
902	mem_i(1)<=x"04";
903	mem_i(2)<=x"00";
904	mem_i(3)<=INIT_SPAWN & pid;-- indiquer qui répond au
905	elsif n=2 then
906	snd_start1<='1';
907	n_i<=n+1;
908	fifo_copy<='0';
909	elsif n=3 then
910	fifo_copy<='0';
911	snd_start1<='1';
912	if snd_comp='1' then
913	snd_ack1<='1';
914	snd_start1<='0';
915	n_i<=n+1;
916	end if;
917	elsif n=4 then --écriture du registre status
918	dma_wr<='1';
919	wr_ok<='1';
920	if dma_wr_grant = '1' then -- fin du mpi_init
921	n_i<=n+1;
922	end if;
923	elsif n=5 then
924	wr_ok<='1';
925	dma_wr<='1';
926	if dma_wr_grant = '1' then -- fin du mpi_init
927	n_i<=n+1;
928	end if;
929	elsif n=6 then
930	Next_ex1_state <= ex1_init3;
931	n_i<=0;
932	wr_ok<='0';
933	end if;
934
935
936	when ex1_init3 =>--if AppInitAck='1' then
937	Next_ex1_state <= fifo_select;
938	--end if;
939	when ex1_ready => Next_ex1_state <= fifo_select;
940	when others => Next_ex1_state <= fifo_select;
941	end case;
942
943	end process;
944
945	-- sortie de la machine à etat
946	ex1_fsm_action : process(ex1_state, fifo_empty, switch_port_in_full, p_len,pid,
947	pid_counter, dma_rd,dma_wr,ram_data_in,AppInitAck,fifo_wr,noc_fifo_in,data_to_send, packet_type, wr_ok,rd_ok,
948	fifo_rd)
949	variable status_reg : std_logic_vector(word-1 downto 0):=(others=>'0');
950	begin
951	-- code fonctionnel
952	Result_i<=Result1;
953	case ex1_state is
954	when fifo_select => priority_rotation <='1'; -- on peut changer la priorité
955	fifo_rd_en <= '0';
956	switch_port_in_data <= (others =>'0');
957	switch_port_in_wr_en <= '0';
958	dma_rd_request <= '0';
959	dma_wr_request <= '0';
960	Ram_rd<='0';
961	Ram_wr<='0';
962	Ram_data_out<=(others=>'0');
963	AppInitReq<='0';
964	Result_i <=(others=>'0');
965	Ready<='1';
966	when read_status1 => priority_rotation <='0';
967	fifo_rd_en <= '0';
968	switch_port_in_data <= (others =>'0');
969	switch_port_in_wr_en <= '0';
970	dma_rd_request <= '1';
971	dma_wr_request <= '0';
972	Ram_rd<='0';
973	Ram_wr<='0';
974	Ram_data_out<=(others=>'0');
975	AppInitReq<='0';
976	Result_i <=(others=>'0');
977	Ready<='0';
978	when read_status2 => priority_rotation <='0';
979	fifo_rd_en <= '0';
980	switch_port_in_data <= (others =>'0');
981	switch_port_in_wr_en <= '0';
982	dma_rd_request <= '1';
983	dma_wr_request <= '0';
984	Ram_rd<='1';
985	Ram_wr<='0';
986	Ram_data_out<=(others=>'0');
987	AppInitReq<='0';
988	status_reg:=Ram_data_in;
989	Result_i <=(others=>'0');
990	Ready<='0';
991	when fetch_packet_type => priority_rotation <='0';
992	fifo_rd_en <= rd_ok;
993	switch_port_in_data <= (others =>'0');
994	AppInitReq<='0';
995	switch_port_in_wr_en <= '0';
996	Ram_rd<='0';
997	Ram_wr<='0';
998	dma_rd_request <= '0';
999	dma_wr_request <= '0';
1000	Ram_data_out<=(others=>'0');
1001	Result_i <=(others=>'0');
1002	Ready<='0';
1003
1004	when decode_packet_type => priority_rotation <='0';
1005	fifo_rd_en <= rd_ok;
1006	switch_port_in_data <= Data_To_Send;
1007	switch_port_in_wr_en <= '0';
1008	AppInitReq<='0';
1009	Ram_rd<='0';
1010	Ram_wr<='0';
1011	dma_rd_request <= '0';
1012	dma_wr_request <= '0';
1013	Ram_data_out<=(others=>'0');
1014	Result_i <=(others=>'0');
1015	Ready<='0';
1016	when fetch_addresses => priority_rotation <='0';
1017	fifo_rd_en <= rd_ok;
1018	switch_port_in_data <= (others =>'0');
1019	switch_port_in_wr_en <= '0';
1020	AppInitReq<='0';
1021	Ram_rd<='0';
1022	Ram_wr<='0';
1023	dma_rd_request <= '0';
1024	dma_wr_request <= '0';
1025	Ram_data_out<=(others=>'0');
1026	Result_i <=(others=>'0');
1027	Ready<='0';
1028	when decode_packet_type2 =>priority_rotation <='0';
1029	fifo_rd_en <= '0';
1030	switch_port_in_data <= data_to_send;
1031	switch_port_in_wr_en <= '0';
1032	AppInitReq<='0';
1033	Ram_rd<='0';
1034	Ram_wr<='0';
1035	dma_rd_request <= '0';
1036	dma_wr_request <= '0';
1037	Ram_data_out<=(others=>'0');
1038	Result_i <=(others=>'0');
1039	Ready<='0'; -- fin du module
1040
1041	when ex1_barrier1 => priority_rotation <='0';
1042	fifo_rd_en <= '0';
1043	switch_port_in_data <= packet_type & pid_counter;
1044	switch_port_in_wr_en <= not(switch_port_in_full);
1045	AppInitReq<='0';
1046	Ram_rd<='0';
1047	Ram_wr<='0';
1048	dma_rd_request <= '0';
1049	dma_wr_request <= '0';
1050	Ram_data_out<=(others=>'0');
1051	Result_i <=(others=>'0');
1052	Ready<='0'; -- fin du module
1053
1054	when ex1_barrier2 => priority_rotation <='0';
1055	fifo_rd_en <= '0';
1056	switch_port_in_data <= p_len;
1057	switch_port_in_wr_en <= not(switch_port_in_full);
1058	AppInitReq<='0';
1059	Ram_rd<='0';
1060	Ram_wr<='0';
1061	dma_rd_request <= '0';
1062	dma_wr_request <= '0';
1063	Ram_data_out<=(others=>'0');
1064	Result_i <=(others=>'0');
1065	Ready<='0'; -- fin du module
1066
1067	when ex1_barrier3 => priority_rotation <='0';
1068	fifo_rd_en <= '0';
1069	switch_port_in_data <= "0000" & pid;
1070	switch_port_in_wr_en <= not(switch_port_in_full);
1071	AppInitReq<='0';
1072	Ram_rd<='0';
1073	Ram_wr<='0';
1074	dma_rd_request <= '0';
1075	dma_wr_request <= '0';
1076	Ram_data_out<=(others=>'0');
1077	Result_i <=(others=>'0');
1078	Ready<='0'; -- fin du module
1079
1080	when ex1_barrier4 => priority_rotation <='0';
1081	fifo_rd_en <= '0';
1082	switch_port_in_data <= "0000" & pid;
1083	switch_port_in_wr_en <= '0';
1084	AppInitReq<='0';
1085	dma_rd_request <= '0';
1086	Ram_rd<='0';
1087	Ram_wr<='0';
1088	dma_wr_request <= '0';
1089	Ram_data_out<=(others=>'0');
1090	Result_i <=(others=>'0');
1091	Ready<='0'; -- fin du module
1092
1093	when ex1_get1 => priority_rotation <='0';
1094	fifo_rd_en <= '0';
1095	switch_port_in_data <= data_to_send;
1096	switch_port_in_wr_en <= Wr_ok;
1097	AppInitReq<='0';
1098	Ram_rd<='0';
1099	Ram_wr<='0';
1100	dma_rd_request <= '0';
1101	dma_wr_request <= '0';
1102	Ram_data_out<=(others=>'0');
1103	Result_i <=(others=>'0');
1104	Ready<='0'; -- fin du module
1105	when ex1_get2 => priority_rotation <='0';
1106	fifo_rd_en <= '0';
1107	switch_port_in_data <= data_to_send;
1108	switch_port_in_wr_en <='0';
1109	AppInitReq<='0';
1110	Ram_rd<='0';
1111	Ram_wr<='0';
1112	dma_rd_request <= '0';
1113	dma_wr_request <= dma_Wr;
1114	Ram_rd<='0';
1115	Ram_wr<='0';
1116	Ram_data_out<=(others=>'0');
1117	Result_i <=(others=>'0');
1118	Ready<='0'; -- fin du module
1119
1120	when ex1_get3 => priority_rotation <='0';
1121	fifo_rd_en <= '0';
1122	switch_port_in_data <= (others=>'0');---???
1123	switch_port_in_wr_en <= '0';
1124	AppInitReq<='0';
1125	dma_rd_request <= '0';
1126	dma_wr_request <= '1';
1127	Ram_rd<='0';
1128	Ram_wr<=wr_ok;
1129	Ram_data_out<=data_to_send; -- le résultat de l'exécution
1130	Ready<='0'; -- fin du module
1131	Result_i <=(2=>'1',others=>'0');--Get completed
1132	when ex1_get4 => priority_rotation <='0';
1133	fifo_rd_en <= '0';
1134	switch_port_in_data <= ram_Data_in;
1135	switch_port_in_wr_en <= '0';
1136	AppInitReq<='0';
1137	dma_rd_request <= dma_rd;
1138	dma_wr_request <= dma_wr;
1139	Ram_rd<=rd_ok;
1140	Ram_wr<=wr_ok;
1141	Ram_data_out<=data_to_send; --"00000001";
1142	Result_i <=(2=>'1',others=>'0'); --get completed
1143	Ready<='0'; -- fin du module
1144	when ex1_put1 => priority_rotation <='0';
1145	fifo_rd_en <= '0';
1146	switch_port_in_data <= data_to_send;
1147	switch_port_in_wr_en <= '0';
1148	AppInitReq<='0';
1149	dma_rd_request <= '1';
1150	dma_wr_request <= '0';
1151	Ram_rd<='0';
1152	Ram_wr<='0';
1153	Ram_data_out<=(others=>'0');
1154	Result_i <=(others=>'0');
1155	Ready<='0'; -- fin du module
1156
1157	when ex1_put2 => priority_rotation <='0';
1158	fifo_rd_en <= '0';
1159	switch_port_in_data <= data_to_send;
1160	switch_port_in_wr_en <= wr_ok;
1161	AppInitReq<='0';
1162	Ram_rd<='1';
1163	Ram_wr<='0';
1164	dma_rd_request <= '1';
1165	dma_wr_request <= '0';
1166	Ram_data_out<=(others=>'0');
1167	Result_i <=(others=>'0');
1168	Ready<='0'; -- fin du module
1169
1170	when ex1_put3 => priority_rotation <='0';
1171	fifo_rd_en <= '0';
1172	switch_port_in_data <= ram_data_in;
1173	switch_port_in_wr_en <= wr_ok;
1174	AppInitReq<='0';
1175	dma_rd_request <= '1';
1176	dma_wr_request <= '0';
1177	Ram_rd<='1';
1178	Ram_wr<='0';
1179	Ram_data_out<=(others=>'0');
1180	Result_i <=(others=>'0');
1181	Ready<='0'; -- fin du module
1182
1183	when ex1_put4 => priority_rotation <='0';
1184	fifo_rd_en <= '0';
1185	switch_port_in_data <= ram_data_in;---???
1186	switch_port_in_wr_en <= '0';
1187	AppInitReq<='0';
1188	dma_rd_request <= rd_ok;
1189	dma_wr_request <= wr_ok;
1190	Ram_rd<=rd_ok;
1191	Ram_wr<=wr_ok;
1192	Ram_data_out<=data_to_send; --"00000001"; -- le résultat de l'exécution
1193	--result(1)<='1';
1194	Result_i <=(1=>'1',others=>'0');--put completed
1195	Ready<='0'; -- fin du module
1196	when ex1_put5 => priority_rotation <='0';
1197	fifo_rd_en <= '0';
1198	switch_port_in_data <= ram_Data_in;
1199	switch_port_in_wr_en <= '0';
1200	AppInitReq<='0';
1201	dma_rd_request <= dma_rd;
1202	dma_wr_request <= dma_wr;
1203	Ram_rd<=rd_ok;
1204	Ram_wr<=wr_ok;
1205	Ram_data_out<=data_to_send; --"00000001";
1206	Result_i <=(1=>'1',others=>'0'); --put completed
1207	Ready<='0'; -- fin du module
1208	when ex1_init1 => priority_rotation <='0';
1209	if fifo_empty='0' then
1210	fifo_rd_en <= rd_ok;
1211	else
1212	fifo_rd_en<='0';
1213	end if;
1214	switch_port_in_data <= data_to_send;
1215	switch_port_in_wr_en <= wr_ok;
1216	dma_rd_request <= '0';
1217	dma_wr_request <= '0';
1218	Ram_rd<='0';
1219	Ram_wr<='0';
1220	Ram_data_out<=(others=>'0');
1221	AppInitReq<='1';
1222	Result_i <=(others=>'0');
1223	Ready<='0';
1224	when ex1_init_run => priority_rotation <='0';
1225
1226	fifo_rd_en <= fifo_rd;
1227
1228	switch_port_in_data <= noc_fifo_in;
1229	switch_port_in_wr_en <= fifo_wr;
1230	dma_rd_request <= '0';
1231	dma_wr_request <= '0';
1232	Ram_rd<='0';
1233	Ram_wr<='0';
1234	Ram_data_out<=(others=>'0');
1235	AppInitReq<='1';
1236	Result_i <=(others=>'0');
1237	Ready<='0';
1238
1239	when ex1_init2=> priority_rotation <='0';
1240	fifo_rd_en <= '0';
1241	switch_port_in_data <= noc_fifo_in;
1242	switch_port_in_wr_en <= fifo_wr;
1243	AppInitReq<='0';
1244	dma_rd_request <= '0';
1245	dma_wr_request <= '1';
1246	Ram_rd<='0';
1247	Ram_wr<=wr_ok;
1248	Ram_data_out<=Data_to_send; -- le résultat de l'exécution
1249	Ready<='0'; -- dans le registre status
1250	Result_i <=(others=>'0');--
1251	when ex1_init3=> priority_rotation <='0';
1252	fifo_rd_en <= '0';
1253	switch_port_in_data <= ram_Data_in;
1254	switch_port_in_wr_en <= '0';
1255	AppInitReq<='0';
1256	dma_rd_request <= '0';
1257	dma_wr_request <= '1';
1258	Ram_rd<='0';
1259	Ram_wr<='1';
1260	Ram_data_out<="00010000";
1261	Ready<='0'; -- fin du module
1262	Result_i<=(0=>'1',others=>'0'); --le résultat de l'initialisation est écrit
1263
1264	when ex1_spawn => priority_rotation <='0';
1265	fifo_rd_en <= rd_ok;
1266	switch_port_in_data <= Data_to_send;
1267	switch_port_in_wr_en <= wr_ok;
1268	AppInitReq<='0';
1269	dma_rd_request <= '0';
1270	dma_wr_request <= '0';
1271	Ram_rd<='0';
1272	Ram_wr<='0';
1273	Ram_data_out<=(others=>'0');
1274	Result_i <=(others=>'0');
1275	Ready<='0';
1276	when ex1_send_ack\|ex1_Wsync => priority_rotation <='0';
1277	fifo_rd_en <= rd_ok;
1278	switch_port_in_data <= Data_to_send;
1279	switch_port_in_wr_en <= wr_ok;
1280	AppInitReq<='0';
1281	dma_rd_request <= '0';
1282	dma_wr_request <= '0';
1283	Ram_rd<='0';
1284	Ram_wr<='0';
1285	Ram_data_out<=(others=>'0');
1286	Result_i <=(others=>'0');
1287	Ready<='0';
1288	when ex1_ready =>
1289	Ready<='1'; -- fin du module
1290	priority_rotation <='0';
1291	fifo_rd_en <= '0';
1292	switch_port_in_data <= (others =>'0');
1293	switch_port_in_wr_en <= '0';
1294	dma_rd_request <= '0';
1295	dma_wr_request <= '0';
1296	Ram_rd<='0';
1297	Ram_wr<='0';
1298	Ram_data_out<=(others=>'0');
1299	AppInitReq<='0';
1300	Ready<='0';
1301
1302	when others => priority_rotation <='0';
1303	fifo_rd_en <= '0';
1304	switch_port_in_data <= (others =>'0');
1305	switch_port_in_wr_en <= '0';
1306	dma_rd_request <= '0';
1307	dma_wr_request <= '0';
1308	Ram_rd<='0';
1309	Ram_wr<='0';
1310	Ram_data_out<=(others=>'0');
1311	AppInitReq<='0';
1312	Result_i <=(others=>'0');
1313	Ready<='0';
1314	end case;
1315
1316	end process;
1317
1318	end Behavioral;
1319

Note: See TracBrowser for help on using the repository browser.

Download in other formats:

Original Format