[100] | 1 | ---------------------------------------------------------------------------------- |
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| 2 | -- Company: GRIIA - ETIS - LIP6 |
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| 3 | -- Engineer: GAMOM, KIEGAING |
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| 4 | -- |
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| 5 | -- Create Date: 01:02:10 06/17/2011 |
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| 6 | -- Design Name: |
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| 7 | -- Module Name: EX2_FSM - Behavioral |
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| 8 | -- Project Name: |
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| 9 | -- Target Devices: |
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| 10 | -- Tool versions: |
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| 11 | -- Description: |
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| 12 | -- machine a etat qui execute la reception des packet dans le core mpi |
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| 13 | -- Dependencies: |
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| 14 | --ss |
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| 15 | -- Revision: 26/01/2012 |
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| 16 | -- Revision 0.01 - File Created |
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| 17 | -- Additional Comments: |
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| 18 | -- |
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| 19 | ---------------------------------------------------------------------------------- |
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| 20 | library IEEE; |
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| 21 | library NocLib ; |
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| 22 | use IEEE.STD_LOGIC_1164.ALL; |
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| 23 | use IEEE.Numeric_std.ALL; |
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| 24 | use IEEE.STD_LOGIC_UNSIGNED.ALL; |
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| 25 | use Work.Packet_type.ALL; |
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| 26 | use NocLib.CoreTypes.all; |
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| 27 | ---- Uncomment the following library declaration if instantiating |
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| 28 | ---- any Xilinx primitives in this code. |
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| 29 | --library UNISIM; |
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| 30 | --use UNISIM.VComponents.all; |
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| 31 | |
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| 32 | entity EX2_FSM is |
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| 33 | |
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| 34 | generic ( |
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| 35 | pid : std_logic_vector(3 downto 0) :="0001"; -- id du processeur |
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| 36 | nprocs : std_logic_vector(3 downto 0):="0100"-- nombre de processeur du MPSOC - 1 |
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| 37 | ); |
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| 38 | Port ( clk : in STD_LOGIC; |
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| 39 | reset : in STD_LOGIC; |
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| 40 | |
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| 41 | Instruction_en : in std_logic; |
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| 42 | |
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| 43 | dma_wr_grant : in STD_LOGIC; |
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| 44 | dma_wr_request : out STD_LOGIC; |
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| 45 | dma_rd_grant : in STD_LOGIC; |
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| 46 | dma_rd_request : out STD_LOGIC; |
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| 47 | ram_rd : out std_logic; |
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| 48 | ram_wr : out std_logic; |
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| 49 | ram_address : out std_logic_vector(ADRLEN-1 downto 0); |
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| 50 | Ram_data_in : out STD_LOGIC_VECTOR (Word-1 downto 0); |
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| 51 | Ram_data_out : in STD_LOGIC_VECTOR (Word-1 downto 0); |
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| 52 | |
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| 53 | fifo_data : out STD_LOGIC_VECTOR (Word-1 downto 0); |
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| 54 | fifo_wr_en : out STD_LOGIC; |
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| 55 | fifo_full : in STD_LOGIC; |
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| 56 | Rec_Rdy : OUT std_logic; |
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| 57 | Rec_Data : buffer Typ_PortIO(0 to 3); |
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| 58 | Rec_Ack : IN std_logic; |
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| 59 | AppRank : in STD_LOGIC_VECTOR(3 downto 0); |
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| 60 | AppSize : in STD_LOGIC_VECTOR(3 downto 0); |
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| 61 | packet_received : out STD_LOGIC; |
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| 62 | packet_ack : in STD_LOGIC; |
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| 63 | barrier_completed : out STD_LOGIC; |
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| 64 | Ready : Out std_logic; |
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| 65 | AppInitReq :out STD_LOGIC; -- requête d'initialisation de l'application |
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| 66 | AppInitAck :in STD_LOGIC; -- Acquitement d'initialisation |
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| 67 | Initialized:in std_logic ; -- état de la Lib |
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| 68 | Result : out STD_LOGIC_VECTOR (Word-1 downto 0):=(others=>'0'); -- le résultat de l'exécution de ce module |
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| 69 | switch_data_available : in STD_LOGIC; |
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| 70 | switch_port_out_data : in STD_LOGIC_VECTOR (Word-1 downto 0); |
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| 71 | switch_port_out_rd_en : out STD_LOGIC |
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| 72 | |
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| 73 | |
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| 74 | |
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| 75 | ); |
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| 76 | end EX2_FSM; |
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| 77 | |
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| 78 | architecture Behavioral of EX2_FSM is |
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| 79 | --module pour la lecture des données sur le réseau |
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| 80 | CONSTANT MSIZE : natural :=4; --taille de la mémoire tampon pour les messages reçu |
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| 81 | component Proto_receiv is |
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| 82 | generic (sizemem : natural := 64); |
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| 83 | port ( |
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| 84 | clk,reset : in std_logic; |
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| 85 | fifo_empty,fifo_full : in std_logic; |
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| 86 | rcv_start : in std_logic; --début de la réception |
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| 87 | rcv_ack :in std_logic; -- acquittement de la réception |
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| 88 | rcv_comp : out std_logic; -- fin de la réception |
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| 89 | pop : out std_logic:='0'; |
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| 90 | fifo_out : in std_logic_vector(Word-1 downto 0); |
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| 91 | mem :out memory(0 to sizemem-1)); |
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| 92 | end component Proto_receiv; |
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| 93 | |
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| 94 | COMPONENT SetBit |
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| 95 | PORT( |
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| 96 | clk : IN std_logic; |
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| 97 | reset : IN std_logic; |
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| 98 | BitMask : IN std_logic_vector(7 downto 0); |
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| 99 | BitVal : IN std_logic; |
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| 100 | start : in std_logic; |
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| 101 | whole : in std_logic; |
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| 102 | done : out std_logic; |
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| 103 | dma_wr_grant : IN std_logic; |
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| 104 | dma_rd_grant : IN std_logic; |
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| 105 | Ram_data_in : out std_logic_vector(7 downto 0); |
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| 106 | dma_wr_request : OUT std_logic; |
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| 107 | dma_rd_request : OUT std_logic; |
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| 108 | ram_rd : OUT std_logic; |
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| 109 | ram_wr : OUT std_logic; |
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| 110 | ram_address : IN std_logic_vector(15 downto 0); |
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| 111 | Ram_data_out : in std_logic_vector(7 downto 0) |
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| 112 | ); |
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| 113 | End component SetBit; |
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| 114 | -- définition du type etat de la machine à etat |
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| 115 | type fsm_states is (Ex2_Ready,fetch_packet_type, decode_packet_type, decode_packet_type2, |
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| 116 | fetch_addresses,ex2_spawn1,ex2_spawn2,ex2_put1,ex2_put2,ex2_put3 ,ex2_put4, |
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| 117 | ex2_put5,ex2_get1, ex2_get2,ex2_get3,ex2_get4,ex2_ack1,ex2_ack2,ex2_ack3, |
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| 118 | Ex2_WSync,Ex2_WComp,ex2_barrier1, ex2_barrier2, ex2_barrier3, ex2_barrier4, |
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| 119 | ex2_barrier5, ex2_barrier6, ex2_barrier7,ex2_init1,ex2_init2,Ex2_Set_Busy); |
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| 120 | type fsm_ack is(ack0,ack1,ack2,ack3,ack4,ack5,ack6); |
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| 121 | type mem32 is array (natural range <>) of std_logic_vector (31 downto 0); |
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| 122 | signal Next_Ex2_state,ex2_state :fsm_states; |
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| 123 | signal ack_state,next_ack_state : fsm_ack; |
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| 124 | -- machine a etat du module |
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| 125 | signal packet_type : std_logic_vector(3 downto 0); |
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| 126 | signal P_len_i,P_len : std_logic_vector(Word-1 downto 0); |
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| 127 | signal barrier_counter : std_logic_vector(3 downto 0); |
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| 128 | signal pading_data,data_to_ram : std_logic_vector(Word-1 downto 0):=(others=>'0'); |
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| 129 | signal n,n_i : natural range 0 to 15; |
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| 130 | signal dest_address,dest_address_i : std_logic_vector(ADRLEN-1 downto 0):=(others=>'0'); |
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| 131 | signal data_to_write_fifo : std_logic_vector(Word-1 downto 0); |
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| 132 | --******************************************* |
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| 133 | --signaux pour la fonction SetBit |
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| 134 | signal sb_BitMask : std_logic_vector(7 downto 0):=(others=>'0'); |
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| 135 | signal sb_BitVal,sb_start,sb_done : std_logic:='0'; |
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| 136 | signal sb_whole : std_logic:='0'; --écrire le mot entier |
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| 137 | signal sb_Ram_data_in : std_logic_vector(7 downto 0); |
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| 138 | signal sb_dma_wr_request : std_logic; |
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| 139 | signal sb_dma_rd_request : std_logic; |
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| 140 | signal sb_ram_rd : std_logic; |
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| 141 | signal sb_ram_wr : std_logic; |
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| 142 | signal sb_ram_address : std_logic_vector(15 downto 0):=(others=>'0'); |
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| 143 | signal sb_Ram_data_out : std_logic_vector(7 downto 0):=(others=>'0'); |
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| 144 | -- deuxième module pour set busy bit |
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| 145 | signal Set_Wbusy : std_logic:='0'; --choix du Mux |
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| 146 | signal GPost_Set,Gpost_Set_i : std_logic:='0'; --indique l'arrivée de Win_Compl |
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| 147 | |
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| 148 | --********************************************* |
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| 149 | signal Ex2_on : std_logic:='0'; |
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| 150 | signal dma_rd,dma_wr,rd_ok ,wr_ok:std_logic:='0'; |
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| 151 | signal sent_ack, sent_ack_i,wr_ack,instr_ack,Instr_ack_i:std_logic:='0'; --signaux pour la gesion de l'acquittement |
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| 152 | signal dest_ack:std_logic_vector(3 downto 0) :=(others=>'0'); |
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| 153 | signal to_fifo_ack :std_logic_vector(Word-1 downto 0):=(others=>'0'); |
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| 154 | signal Result_i : STD_LOGIC_VECTOR (Word-1 downto 0):=(others=>'0'); |
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| 155 | --signaux pour l'untilisation du composant de réception |
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| 156 | signal rfifo_empty,rfifo_full:std_logic; |
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| 157 | signal rcv_start,rcv_comp,rcv_ack:std_logic; |
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| 158 | signal rpop:std_logic; |
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| 159 | --signal mem:memory(0 to Msize-1)); |
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| 160 | --jusqu'à 16 Get peuvent être attendus! |
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| 161 | signal Wcomp : std_logic:='0'; --indique que tous les transferts sont terminés |
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| 162 | signal WStart,WPost,WBUSY ,RGET: std_logic:='0'; -- |
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| 163 | signal Rec_WPost,Rec_WPost_i,GComp,GComp_i, GPost_i,GPost: std_logic_vector(15 downto 0):=(others=>'0'); |
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| 164 | signal Waited_Get,Waited_Get_i : mem32(0 to 15); |
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| 165 | Signal Rec_Data_i : Typ_PortIO(0 to 3); |
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| 166 | signal Get_Instr,Put_instr :memory(0 to 8); |
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| 167 | signal Put_Id : std_logic_vector(31 downto 0):=(others=>'0'); |
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| 168 | signal P_G: natural range 0 to 3:=0; --Msg Ack : 1 -> Put, 2-->Get |
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| 169 | signal Ptr_Get,Ptr_Get_i : natural range 0 to 15:=0; |
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| 170 | signal Received_get : std_logic_vector(15 downto 0):=(others=>'0');--sera remis à 0 lorsque Wstart/WPost est reçu |
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| 171 | begin |
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| 172 | ram_address <= dest_address; |
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| 173 | --fifo_data <= data_to_write_fifo; |
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| 174 | Result<=Result_i; |
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| 175 | p_instr_fifo:process(ack_state,data_to_write_fifo,wr_ack,to_fifo_ack,instr_ack) |
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| 176 | begin |
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| 177 | if instr_ack='1' then |
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| 178 | fifo_data<=to_fifo_ack; |
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| 179 | else |
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| 180 | fifo_data<=data_to_write_fifo; |
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| 181 | end if; |
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| 182 | end process p_instr_fifo; |
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| 183 | |
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| 184 | |
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| 185 | |
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| 186 | R0:proto_receiv generic map (sizemem =>4) |
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| 187 | port map ( |
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| 188 | clk=>clk, |
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| 189 | reset=>reset, |
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| 190 | rcv_start=>rcv_start, |
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| 191 | rcv_comp=>rcv_comp, |
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| 192 | rcv_ack=>rcv_ack, |
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| 193 | fifo_empty=>rfifo_empty, |
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| 194 | fifo_full=>rfifo_full, |
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| 195 | fifo_out=>switch_port_out_data, |
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| 196 | pop=>rpop, |
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| 197 | mem=>open |
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| 198 | |
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| 199 | ); |
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| 200 | --envoie de l'acquittement |
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| 201 | setbit1:SetBit |
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| 202 | PORT MAP ( |
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| 203 | clk =>clk, |
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| 204 | reset =>reset, |
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| 205 | BitMask =>sb_bitMask, |
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| 206 | BitVal =>sb_bitval, |
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| 207 | dma_wr_grant =>dma_wr_grant, |
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| 208 | dma_rd_grant =>dma_rd_grant, |
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| 209 | Ram_data_in => sb_Ram_data_in, |
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| 210 | dma_wr_request =>sb_dma_wr_request, |
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| 211 | dma_rd_request =>sb_dma_rd_request, |
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| 212 | ram_rd =>sb_ram_rd, |
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| 213 | ram_wr =>sb_ram_wr, |
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| 214 | ram_address =>dest_address, |
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| 215 | Ram_data_out =>sb_ram_data_out, |
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| 216 | Start =>sb_start, |
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| 217 | whole=>sb_whole, |
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| 218 | done =>sb_done |
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| 219 | ); |
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| 220 | |
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| 221 | -- processus de transistion entre les etats |
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| 222 | ex2_fsm_logic : process(Ex2_state, Instruction_En,fifo_full,dma_rd_grant,dma_wr_grant,AppinitAck,Initialized, |
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| 223 | switch_data_available,switch_port_out_data,sb_ram_data_in,Data_to_Ram,Ram_data_out,sb_done,sb_dma_rd_request,n,P_len, |
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| 224 | sent_ack,wr_ack,to_fifo_ack,dest_address,WBusy,Ptr_Get,Get_Instr,P_G,Waited_get,Received_get,rget,GPost,GPost_Set,packet_type,barrier_counter, |
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| 225 | dest_ack,rec_wpost,Gcomp,rec_data) |
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| 226 | variable delai : natural range 0 to 1:=0; --permet de détecter que l'écriture en RAM doit être décalée |
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| 227 | variable tempval : std_logic_vector(Word-1 downto 0); |
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| 228 | variable n_e,i:natural range 0 to 15 :=0; |
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| 229 | variable mode_get,match_get:std_logic:='0'; |
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| 230 | --=================================================================- |
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| 231 | procedure read_nocdat_fsm(sdata_avail: std_logic; |
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| 232 | signal rd,wr:out std_logic; |
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| 233 | signal Plen : inout std_logic_vector(Word-1 downto 0); |
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| 234 | variable n:out natural range 0 to 15;signal n_e:in natural range 0 to 15) is |
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| 235 | --lit la suite des données qui sont dans le NoC et identifie le paramètre important |
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| 236 | begin |
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| 237 | if n_e<3 then |
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| 238 | wr<='0'; |
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| 239 | if sdata_avail='1' then |
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| 240 | n:=n_e+1; |
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| 241 | rd<='1'; |
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| 242 | plen <=plen-1; |
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| 243 | else |
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| 244 | rd<='0'; |
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| 245 | end if; |
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| 246 | --result_i<=(others=>'0'); |
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| 247 | elsif n_e=3 then |
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| 248 | if sdata_avail='1' then |
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| 249 | n:=n_e+1; |
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| 250 | rd<='0'; |
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| 251 | --P_len <=P_len_i -1; |
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| 252 | --data_to_ram<=sportdout; |
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| 253 | --Result_i<=sport_out_data; |
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| 254 | else |
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| 255 | rd<='0'; |
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| 256 | end if; |
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| 257 | end if; |
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| 258 | end procedure; |
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| 259 | |
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| 260 | begin |
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| 261 | |
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| 262 | Next_Ex2_state <= Ex2_state; |
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| 263 | Ex2_on<='0'; |
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| 264 | barrier_counter <= "0000"; |
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| 265 | GPost_Set_i<=GPost_Set; |
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| 266 | Rec_WPost_i<=Rec_WPost; |
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| 267 | GPost_i<=GPost; |
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| 268 | GComp_i<=GComp; |
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| 269 | dest_address_i<=dest_address; |
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| 270 | for i in 0 to 15 loop |
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| 271 | Waited_get_i(i)<=Waited_get(i); |
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| 272 | end loop; |
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| 273 | |
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| 274 | Ex2_on<=Instruction_en; --détermine si le module peut être activer ou non |
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| 275 | n_i<=n; --valeur par défaut de n_i |
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| 276 | P_len_i<=P_len; |
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| 277 | for i in 0 to 3 loop |
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| 278 | Rec_Data_i(i)<=Rec_Data(i); |
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| 279 | end loop; |
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| 280 | case ex2_state is |
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| 281 | when Ex2_ready => if Instruction_en='1' and switch_data_available='1' then |
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| 282 | Next_Ex2_state <= fetch_packet_type; |
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| 283 | end if; |
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| 284 | rd_ok<='0';wr_ok<='0'; |
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| 285 | when fetch_packet_type => if switch_data_available ='1' and Instruction_en='1' then --and initialized ='1' |
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| 286 | Next_Ex2_state <= decode_packet_type; |
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| 287 | packet_type<=switch_port_out_data(7 downto 4); |
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| 288 | Dest_ack<=switch_port_out_data(3 downto 0); |
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| 289 | Rec_Data_i(0)<=switch_port_out_data; --récupérer la première donnée reçue ! |
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| 290 | rd_ok<='1'; |
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| 291 | else |
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| 292 | --Next_Ex2_state <= Ex2_Ready; |
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| 293 | rd_ok<='0'; |
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| 294 | end if; |
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| 295 | n_i<=0; |
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| 296 | when decode_packet_type => rd_ok<='0'; |
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| 297 | if switch_data_available ='0' then |
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| 298 | Next_Ex2_state <= decode_packet_type; |
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| 299 | else |
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| 300 | rd_ok<='1'; |
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| 301 | Rec_Data_i(1)<=switch_port_out_data-2; |
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| 302 | if packet_type = MPI_PUT then |
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| 303 | P_len_i <= switch_port_out_data - 2; |
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| 304 | n_i<=0; |
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| 305 | |
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| 306 | Next_Ex2_state <= decode_packet_type2; |
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| 307 | elsif packet_type = MPI_GET then |
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| 308 | P_len_i <=switch_port_out_data-2; |
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| 309 | Next_Ex2_state <= decode_packet_type2; |
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| 310 | elsif packet_type = MPI_BARRIER_REACHED or packet_type = MPI_BARRIER_COMPLETED then |
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| 311 | P_len_i <= switch_port_out_data; |
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| 312 | n_i<=0; |
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| 313 | Next_Ex2_state <= ex2_barrier1; |
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| 314 | elsif packet_type = MPI_INIT or packet_type =INIT_SETRANK or packet_type =INIT_SEEKMAIN then |
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| 315 | n_i<=0; |
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| 316 | wr_ok<='0'; |
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| 317 | --rd_ok<='1'; |
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| 318 | P_len_i <= switch_port_out_data-2; |
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| 319 | Rec_Data_i(1)<=switch_port_out_data; |
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| 320 | Next_Ex2_state <= ex2_init1; |
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| 321 | elsif packet_type = MPI_ACK then |
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| 322 | n_i<=0; |
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| 323 | wr_ok<='0'; |
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| 324 | rd_ok<='0'; |
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| 325 | P_len_i <= switch_port_out_data-2; |
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| 326 | Next_Ex2_state <= ex2_ack1; |
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| 327 | elsif packet_type = MPI_WIN_SYNC then |
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| 328 | n_i<=0; |
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| 329 | wr_ok<='0'; |
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| 330 | rd_ok<='0'; |
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| 331 | P_len_i <= switch_port_out_data-2; |
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| 332 | Next_Ex2_state <= ex2_Wsync; |
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| 333 | elsif packet_type = MPI_SPAWN then |
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| 334 | Next_Ex2_state <= ex2_spawn1; |
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| 335 | wr_ok<='0'; |
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| 336 | rd_ok<='0'; |
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| 337 | else |
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| 338 | Next_Ex2_state <= decode_packet_type; |
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| 339 | rd_ok<='0'; |
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| 340 | end if; |
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| 341 | end if; |
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| 342 | when decode_packet_type2 => if packet_type = MPI_PUT then |
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| 343 | Next_Ex2_state <= fetch_addresses; |
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| 344 | else |
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| 345 | Next_Ex2_state <= ex2_get1; |
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| 346 | end if; |
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| 347 | when fetch_addresses => if n=0 then |
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| 348 | if switch_data_available = '1' then |
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| 349 | dest_address_i(15 downto 8) <= switch_port_out_data; |
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| 350 | Rec_data_i(2)<=switch_port_out_data; |
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| 351 | n_i <= n + 1; |
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| 352 | rd_ok<='1'; |
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| 353 | else |
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| 354 | rd_ok<='0'; |
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| 355 | end if; |
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| 356 | elsif n=1 then |
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| 357 | if switch_data_available = '1' then |
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| 358 | dest_address_i(Word-1 downto 0) <= switch_port_out_data; |
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| 359 | Rec_data_i(3)<=switch_port_out_data; |
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| 360 | P_len_i <= P_len - 2; |
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| 361 | Next_Ex2_state <= ex2_put1; |
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| 362 | n_i<=0; |
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| 363 | rd_ok<='1'; |
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| 364 | else |
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| 365 | rd_ok<='0'; |
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| 366 | Next_Ex2_state <= fetch_addresses; |
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| 367 | end if; |
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| 368 | end if; |
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| 369 | when Ex2_ack2 =>if unsigned(p_len)>0 then |
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| 370 | If Dma_rd_grant='1' then |
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| 371 | if n=0 then |
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| 372 | n_i<=n+1; --cycle d'attente pour la RAM |
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| 373 | elsif n=1 then |
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| 374 | dest_address_i <= dest_address+1; |
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| 375 | n_i<=2; |
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| 376 | elsif n>=2 then |
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| 377 | |
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| 378 | --creer un délai sur ces signaux par rapport à src_adress |
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| 379 | |
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| 380 | n_i<=n+1; |
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| 381 | rd_ok<='1'; |
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| 382 | -- if n>1 then |
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| 383 | dest_address_i <= dest_address+1; |
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| 384 | p_len_i <= p_len - 1; |
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| 385 | --end if; |
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| 386 | Get_Instr(n-2)<=Ram_data_out; --deux cycles de retard |
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| 387 | Next_ex2_state <= ex2_ack2; |
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| 388 | end if; |
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| 389 | end if; |
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| 390 | dma_rd<='1'; |
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| 391 | rd_ok<='1'; |
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| 392 | else |
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| 393 | if P_G=1 then |
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| 394 | dest_address_i<=std_logic_vector(to_unsigned(Core_Put_adr+7,16)); |
---|
| 395 | else |
---|
| 396 | dest_address_i<=std_logic_vector(to_unsigned(Core_Get_adr+7,16)); |
---|
| 397 | Waited_get_i(ptr_get)(7 downto 0)<=Get_instr(0); --id |
---|
| 398 | Waited_get_i(ptr_get)(15 downto 8)<=Get_instr(1); --longueur |
---|
| 399 | Waited_get_i(ptr_get)(23 downto 16)<=Get_instr(4); --adr dest bas |
---|
| 400 | Waited_get_i(ptr_get)(31 downto 24)<=Get_instr(5); --adr dest haut |
---|
| 401 | RGET<='1'; |
---|
| 402 | |
---|
| 403 | Ptr_Get_i<=Ptr_Get+1; --prochain Get à traiter |
---|
| 404 | end if; |
---|
| 405 | Next_ex2_state <= ex2_ack3; |
---|
| 406 | n_i<=0; --suite du process ack |
---|
| 407 | rd_ok<='0'; |
---|
| 408 | dma_rd<='0'; |
---|
| 409 | end if; |
---|
| 410 | when ex2_ack1 => rd_ok<='0'; |
---|
| 411 | if n<2 then --réception de l'acquittement. |
---|
| 412 | n_e:=n_i; |
---|
| 413 | read_nocdat_fsm(switch_data_available,rd_ok,wr_ok,P_len_i,n_e,n); |
---|
| 414 | n_i<=n_e; |
---|
| 415 | elsif n=2 then |
---|
| 416 | if switch_data_available='1' then |
---|
| 417 | n_i<=n+1; |
---|
| 418 | rd_ok<='1'; |
---|
| 419 | |
---|
| 420 | data_to_ram<=switch_port_out_data; |
---|
| 421 | Result_i<=switch_port_out_data; |
---|
| 422 | end if; |
---|
| 423 | |
---|
| 424 | elsif n=3 then |
---|
| 425 | n_i<=n+1;P_G<=0; |
---|
| 426 | if data_to_ram(7 downto 4)=MPI_PUT then |
---|
| 427 | Result_i<=data_to_ram; |
---|
| 428 | dest_address_i<=std_logic_vector(to_unsigned(Core_Put_adr,16)); |
---|
| 429 | wr_ok<='1'; |
---|
| 430 | P_G<=1; --put ou get |
---|
| 431 | P_len_i<=x"06"; --longueur de l'entête à parcourir |
---|
| 432 | elsif data_to_ram(7 downto 4)=MPI_GET then |
---|
| 433 | Result_i<=data_to_ram; |
---|
| 434 | wr_ok<='1'; -- |
---|
| 435 | P_G<=2; --put get |
---|
| 436 | P_len_i<=x"06";--taille de l'instruction en mémoire |
---|
| 437 | dest_address_i<=std_logic_vector(to_unsigned(Core_Get_adr,16)); |
---|
| 438 | elsif data_to_ram(7 downto 4)=MPI_SPAWN then |
---|
| 439 | Result_i<=data_to_ram; |
---|
| 440 | wr_ok<='1'; -- |
---|
| 441 | dest_address_i<=std_logic_vector(to_unsigned(Core_Spawn_adr+7,16)); |
---|
| 442 | elsif data_to_ram(7 downto 4)=MPI_INIT then |
---|
| 443 | Result_i<=data_to_ram; |
---|
| 444 | dest_address_i<=std_logic_vector(to_unsigned(Core_Init_adr+7,16)); |
---|
| 445 | wr_ok<='1'; -- |
---|
| 446 | -- |
---|
| 447 | else |
---|
| 448 | Result_i<="00000000"; |
---|
| 449 | wr_ok<='0'; -- |
---|
| 450 | n_i<=n; --code inconnu ! |
---|
| 451 | end if; |
---|
| 452 | elsif n=4 then |
---|
| 453 | if P_G=1 or P_G=2 then |
---|
| 454 | Next_ex2_state<=ex2_ack2; |
---|
| 455 | else |
---|
| 456 | Next_ex2_state<=ex2_ack3; |
---|
| 457 | end if; |
---|
| 458 | n_i<=0; |
---|
| 459 | end if; |
---|
| 460 | |
---|
| 461 | when ex2_ack3 => if n=0 then --set acknowlege bit of the instruction |
---|
| 462 | sb_start<='1'; |
---|
| 463 | sb_bitMask<=x"20";--cinquième bit à un |
---|
| 464 | sb_bitval<='1'; |
---|
| 465 | sb_whole<='0';--Modifier un seul bit ! |
---|
| 466 | if sb_done='1' then |
---|
| 467 | n_i<=1; |
---|
| 468 | sb_start<='0'; |
---|
| 469 | sb_bitval<='0'; |
---|
| 470 | dest_address_i<=dest_address+1; |
---|
| 471 | end if; |
---|
| 472 | |
---|
| 473 | elsif n=1 then |
---|
| 474 | sb_start<='1'; |
---|
| 475 | sb_bitMask<=Rec_Data(2); |
---|
| 476 | sb_bitval<='1'; |
---|
| 477 | sb_whole<='1'; |
---|
| 478 | if sb_done='1' then |
---|
| 479 | n_i<=n+1; |
---|
| 480 | sb_start<='0'; |
---|
| 481 | sb_bitval<='0'; |
---|
| 482 | sb_whole<='0'; |
---|
| 483 | end if; |
---|
| 484 | |
---|
| 485 | elsif n=2 then |
---|
| 486 | Next_Ex2_state<=Ex2_Ready; |
---|
| 487 | n_i<=0; |
---|
| 488 | end if; |
---|
| 489 | |
---|
| 490 | when ex2_Wsync => rd_ok<='0'; |
---|
| 491 | if n<2 then --réception de la synchronisation. |
---|
| 492 | n_e:=n; |
---|
| 493 | read_nocdat_fsm(switch_data_available,rd_ok,wr_ok,P_len_i,n_e,n); |
---|
| 494 | n_i<=n_e; |
---|
| 495 | elsif n=2 then |
---|
| 496 | if switch_data_available='1' then |
---|
| 497 | n_i<=n+1; |
---|
| 498 | rd_ok<='1'; |
---|
| 499 | |
---|
| 500 | data_to_ram<=switch_port_out_data; |
---|
| 501 | Result_i<=switch_port_out_data; |
---|
| 502 | end if; |
---|
| 503 | |
---|
| 504 | elsif n=3 then |
---|
| 505 | n_i<=n+1;P_G<=0; |
---|
| 506 | if data_to_ram(7 downto 4)=SYNC_WSTART then |
---|
| 507 | Result_i<=data_to_ram; |
---|
| 508 | dest_address_i<=std_logic_vector(to_unsigned(Win0_adr,16)); |
---|
| 509 | wr_ok<='1'; |
---|
| 510 | P_G<=1; --put ou get |
---|
| 511 | P_len_i<=x"06"; --longueur de l'entête à parcourir |
---|
| 512 | elsif data_to_ram(7 downto 4)=SYNC_WPOST then |
---|
| 513 | Result_i<=data_to_ram; |
---|
| 514 | wr_ok<='1'; -- |
---|
| 515 | P_G<=2; --put get |
---|
| 516 | P_len_i<=x"06";--taille de l'instruction en mémoire |
---|
| 517 | dest_address_i<=std_logic_vector(to_unsigned(Win0_adr,16)); |
---|
| 518 | elsif data_to_ram(7 downto 4)=SYNC_WWAIT then |
---|
| 519 | Result_i<=data_to_ram; |
---|
| 520 | wr_ok<='1'; -- |
---|
| 521 | dest_address_i<=std_logic_vector(to_unsigned(Win0_adr+7,16)); |
---|
| 522 | elsif data_to_ram(7 downto 4)=SYNC_WCOMP then |
---|
| 523 | Result_i<=data_to_ram; |
---|
| 524 | dest_address_i<=std_logic_vector(to_unsigned(Win0_adr+W_Gpost,16)); |
---|
| 525 | wr_ok<='1'; -- |
---|
| 526 | Next_Ex2_State<=Ex2_WCOMP; |
---|
| 527 | n_i<=0; |
---|
| 528 | else |
---|
| 529 | Result_i<="00000000"; |
---|
| 530 | wr_ok<='0'; -- |
---|
| 531 | n_i<=n; --code inconnu ! |
---|
| 532 | end if; |
---|
| 533 | |
---|
| 534 | end if; |
---|
| 535 | when Ex2_Wcomp => dma_rd<='1'; |
---|
| 536 | rd_ok<='1'; |
---|
| 537 | |
---|
| 538 | if n=0 then |
---|
| 539 | n_i<=n+1; --cycle d'attente pour la RAM |
---|
| 540 | i:=to_integer(unsigned(Rec_Data(0)(3 downto 0))); |
---|
| 541 | GComp_i(i)<='1'; |
---|
| 542 | elsif n=1 then |
---|
| 543 | dest_address_i<=std_logic_vector(to_unsigned(Win0_adr+W_Gpost,16)); |
---|
| 544 | If Dma_rd_grant='1' then |
---|
| 545 | n_i<=2; |
---|
| 546 | end if; |
---|
| 547 | elsif n=2 then |
---|
| 548 | If Dma_rd_grant='1' then |
---|
| 549 | --creer un délai sur ces signaux par rapport à dest_adress |
---|
| 550 | n_i<=n+1; |
---|
| 551 | rd_ok<='1'; |
---|
| 552 | dest_address_i <= dest_address+1; |
---|
| 553 | GPost_i(7 downto 0)<=Ram_data_out; --deux cycles de retard |
---|
| 554 | |
---|
| 555 | else |
---|
| 556 | n_i<=1; |
---|
| 557 | end if; |
---|
| 558 | elsif n=3 then |
---|
| 559 | If Dma_rd_grant='1' then |
---|
| 560 | GPost_i(15 downto 8)<=Ram_data_out; |
---|
| 561 | n_i<=n+1; |
---|
| 562 | rd_ok<='1'; |
---|
| 563 | dma_rd<='1'; |
---|
| 564 | end if; |
---|
| 565 | elsif n=4 then |
---|
| 566 | GPost_i(15 downto 8)<=Ram_data_out; |
---|
| 567 | rd_ok<='1'; |
---|
| 568 | dma_rd<='1'; |
---|
| 569 | n_i<=n+1; |
---|
| 570 | elsif n=5 then |
---|
| 571 | rd_ok<='0'; |
---|
| 572 | dma_rd<='0'; |
---|
| 573 | n_i<=0; |
---|
| 574 | If GPost=GComp then --le même nombre de post que de COmpleted ? |
---|
| 575 | GPost_Set_i<='1'; |
---|
| 576 | end if; |
---|
| 577 | |
---|
| 578 | Next_ex2_state <= ex2_set_busy; |
---|
| 579 | end if; |
---|
| 580 | |
---|
| 581 | |
---|
| 582 | when ex2_init1 => if n<2 then -- execution du mpi Init |
---|
| 583 | wr_ok<='0'; |
---|
| 584 | if switch_data_available='1' then |
---|
| 585 | n_i<=n+1; |
---|
| 586 | rd_ok<='1'; |
---|
| 587 | P_len_i <=P_len-1; |
---|
| 588 | Rec_Data_i(n+2)<=switch_port_out_data; |
---|
| 589 | data_to_ram<=switch_port_out_data; |
---|
| 590 | Result_i<=switch_port_out_data; |
---|
| 591 | else |
---|
| 592 | rd_ok<='0'; |
---|
| 593 | n_i<=n; |
---|
| 594 | end if; |
---|
| 595 | result_i<=(others=>'0'); |
---|
| 596 | elsif n=2 then |
---|
| 597 | n_i<=n+1; |
---|
| 598 | rd_ok<='0'; |
---|
| 599 | |
---|
| 600 | elsif n=3 then |
---|
| 601 | rd_ok<='0'; -- normalement plus rien à lire |
---|
| 602 | n_i<=n+1; |
---|
| 603 | if Initialized='1' then |
---|
| 604 | if data_to_ram(7 downto 4)=INIT_SEEKMAIN then |
---|
| 605 | Result_i<=data_to_ram; |
---|
| 606 | wr_ok<='1'; --permet d'activer Init de Ex_4 |
---|
| 607 | elsif data_to_ram(7 downto 4)=INIT_STAT then |
---|
| 608 | Result_i<=data_to_ram; |
---|
| 609 | wr_ok<='1'; --permet d'activer Init de Ex_4 |
---|
| 610 | elsif data_to_ram(7 downto 4)=INIT_REGISTER then |
---|
| 611 | Result_i<=data_to_ram; |
---|
| 612 | wr_ok<='0'; --permet d'activer Init de Ex_4 |
---|
| 613 | report "Mise à jour des données d'initialisation"; |
---|
| 614 | Next_Ex2_state<=ex2_ready; |
---|
| 615 | n_i<=0; |
---|
| 616 | elsif data_to_ram(7 downto 4)=INIT_SPAWN then |
---|
| 617 | Result_i<=data_to_ram; |
---|
| 618 | wr_ok<='1'; --permet d'activer Init de Ex_4 |
---|
| 619 | -- il faut mettre à jour l'état de Spawn |
---|
| 620 | else |
---|
| 621 | Result_i<="00000000"; |
---|
| 622 | wr_ok<='0'; --permet d'activer Init de Ex_4 |
---|
| 623 | end if; |
---|
| 624 | end if; |
---|
| 625 | elsif n=4 then |
---|
| 626 | n_i<=n+1; |
---|
| 627 | elsif n=5 then |
---|
| 628 | if p_len=0 then |
---|
| 629 | Next_Ex2_state<=ex2_init2; |
---|
| 630 | rd_ok<='0'; |
---|
| 631 | else |
---|
| 632 | p_len_i <=p_len -1; |
---|
| 633 | rd_ok<='1'; --vider le tampon de lecture pour ce paquet ! |
---|
| 634 | end if; |
---|
| 635 | |
---|
| 636 | end if; |
---|
| 637 | when ex2_init2=> if n=5 then |
---|
| 638 | if AppInitAck='1' then |
---|
| 639 | n_i<=n+1; |
---|
| 640 | Result_i<="00000001"; -- cette valeur permet d'acquitter la fonction Init |
---|
| 641 | end if; |
---|
| 642 | elsif n=6 then |
---|
| 643 | Next_Ex2_state<=Ex2_Ready; |
---|
| 644 | n_i<=0; |
---|
| 645 | end if; |
---|
| 646 | |
---|
| 647 | when ex2_put1 => rd_ok<='0'; --ne pas autoriser la lecture du switch |
---|
| 648 | wr_ok<='0'; |
---|
| 649 | if n=0 then |
---|
| 650 | instr_ack_i<='1'; --activer l'envoie de l'accusé de réception |
---|
| 651 | data_to_write_fifo<=to_fifo_ack; |
---|
| 652 | wr_ok<=wr_ack; |
---|
| 653 | if sent_ack='1' then |
---|
| 654 | n_i<=1; |
---|
| 655 | instr_ack_i<='0'; |
---|
| 656 | end if; |
---|
| 657 | |
---|
| 658 | elsif n=1 then |
---|
| 659 | if dma_wr_grant = '1' then |
---|
| 660 | Next_Ex2_state <= ex2_put2; |
---|
| 661 | data_to_ram<=switch_port_out_data; |
---|
| 662 | rd_ok<='0'; |
---|
| 663 | n_i<=0; |
---|
| 664 | delai:=0; |
---|
| 665 | else |
---|
| 666 | Next_Ex2_state <= ex2_put1; |
---|
| 667 | end if; |
---|
| 668 | end if; |
---|
| 669 | when ex2_put2 => rd_ok<='0'; |
---|
| 670 | n_i<=1; |
---|
| 671 | i:=to_integer(unsigned(Rec_Data_i(0)(3 downto 0))); |
---|
| 672 | --Rec_WPost_i(i)<='1'; --indiquer que ce port a emis des données ! |
---|
| 673 | if unsigned( P_len) > 0 then |
---|
| 674 | |
---|
| 675 | if switch_data_available = '1' and delai=0 then |
---|
| 676 | delai:=1; --une donné lue |
---|
| 677 | P_len_i <= P_len - 1; |
---|
| 678 | Next_Ex2_state <= ex2_put2; |
---|
| 679 | rd_ok<='1'; |
---|
| 680 | data_to_ram<=switch_port_out_data; |
---|
| 681 | end if; |
---|
| 682 | if dma_wr_grant='1' and delai=1 then |
---|
| 683 | -- if n=1 then |
---|
| 684 | wr_ok<='1'; |
---|
| 685 | dest_address_i <= dest_address + 1; |
---|
| 686 | delai:=0;--une donnée écrite |
---|
| 687 | -- else |
---|
| 688 | -- dest_address_i <= dest_address ; |
---|
| 689 | -- end if; |
---|
| 690 | --if delai=1 then |
---|
| 691 | --data_to_ram<=switch_port_out_data; --met en registre la donnée présente sur le port du switch |
---|
| 692 | --end if; |
---|
| 693 | |
---|
| 694 | else |
---|
| 695 | dest_address_i<=dest_address; |
---|
| 696 | wr_ok<='0'; |
---|
| 697 | n_i<=0; |
---|
| 698 | end if; |
---|
| 699 | |
---|
| 700 | Next_Ex2_state <= ex2_put2; |
---|
| 701 | |
---|
| 702 | else |
---|
| 703 | rd_ok<='0'; |
---|
| 704 | |
---|
| 705 | |
---|
| 706 | if dma_wr_grant='1' and n=1 then |
---|
| 707 | |
---|
| 708 | Next_Ex2_state <= ex2_put3; |
---|
| 709 | Wr_ok<='0'; |
---|
| 710 | n_i<=0; |
---|
| 711 | end if; |
---|
| 712 | end if; |
---|
| 713 | |
---|
| 714 | when ex2_put3 => if dma_rd_grant='1' then |
---|
| 715 | dest_address_i<=std_logic_vector(to_unsigned(core_base_adr+4,16)); |
---|
| 716 | Next_Ex2_state <= ex2_put4; |
---|
| 717 | n_i<=0; |
---|
| 718 | rd_ok<='1'; |
---|
| 719 | wr_ok<='0'; |
---|
| 720 | end if; |
---|
| 721 | |
---|
| 722 | when ex2_put4 => if n<=4 and n>0 then |
---|
| 723 | |
---|
| 724 | dma_wr<='1'; --demander un accès exclusif au bus |
---|
| 725 | dma_rd<='1'; -- pour éviter une mauvaise mise à jour des données |
---|
| 726 | else |
---|
| 727 | dma_wr<='0'; |
---|
| 728 | dma_rd<='0'; |
---|
| 729 | end if; |
---|
| 730 | if n=0 then |
---|
| 731 | if RGET='1' then |
---|
| 732 | L1: for i in 1 to 15 loop -- to Ptr_get normalement |
---|
| 733 | if i<=Ptr_Get then |
---|
| 734 | if waited_get(i-1)(3 downto 0)=rec_data(0)(3 downto 0) and |
---|
| 735 | waited_get(i-1)(15 downto 8)=(rec_data(1)-2) and |
---|
| 736 | waited_get(i-1)(23 downto 16)=rec_data(2) and |
---|
| 737 | waited_get(i-1)(31 downto 24)=rec_data(3) then |
---|
| 738 | if (waited_get(i-1)(7 downto 4)=MPI_GET) and (rec_data(0)(7 downto 4)=MPI_PUT) then |
---|
| 739 | received_get(i-1)<='1'; |
---|
| 740 | dest_address_i<=std_logic_vector(to_unsigned(core_base_adr+5,16)); |
---|
| 741 | mode_get:='1'; |
---|
| 742 | match_get:='1'; |
---|
| 743 | end if; |
---|
| 744 | else |
---|
| 745 | |
---|
| 746 | end if; |
---|
| 747 | end if; |
---|
| 748 | exit L1 when i= Ptr_get; |
---|
| 749 | end loop L1; |
---|
| 750 | end if; |
---|
| 751 | |
---|
| 752 | n_i<=n+1; |
---|
| 753 | rd_ok<='1'; |
---|
| 754 | wr_ok<='0'; |
---|
| 755 | |
---|
| 756 | elsif n=1 then |
---|
| 757 | if match_get='0' then |
---|
| 758 | i:=to_integer(unsigned(Rec_Data(0)(3 downto 0))); |
---|
| 759 | Rec_WPost_i(i)<='1'; --indiquer que ce port a emis des données ! |
---|
| 760 | end if; |
---|
| 761 | if dma_rd_grant='1' then |
---|
| 762 | if RGET='1' then --si on est en mode attente d'un Get |
---|
| 763 | RGET<='0'; --Supposons tous les Gets reçus ! |
---|
| 764 | test_wcomp:for i in 1 to 15 loop --Tous les Get reçus ? |
---|
| 765 | if Ptr_get>=i then |
---|
| 766 | if received_get(i-1)='0' then |
---|
| 767 | RGET<='1'; --Non ! |
---|
| 768 | end if; |
---|
| 769 | end if; |
---|
| 770 | exit test_wcomp when i=Ptr_get; |
---|
| 771 | end loop test_wcomp; |
---|
| 772 | |
---|
| 773 | end if; |
---|
| 774 | n_i<=n+1; |
---|
| 775 | else |
---|
| 776 | rd_ok<='1'; |
---|
| 777 | wr_ok<='0'; |
---|
| 778 | end if; |
---|
| 779 | elsif n=2 then |
---|
| 780 | if dma_rd_grant='1' and dma_wr_grant='1' then |
---|
| 781 | n_i<=n+1; |
---|
| 782 | tempval:=Ram_data_out; |
---|
| 783 | tempval(4):='1'; --SET du bit DReceived |
---|
| 784 | if Mode_Get='1' then --si get ack est détecté |
---|
| 785 | tempval(6):=RGET; -- Bit 6 Busy=0 si dernier get reçu !! |
---|
| 786 | mode_get:='1'; |
---|
| 787 | end if; |
---|
| 788 | data_to_ram<=tempval; |
---|
| 789 | rd_ok<='0'; |
---|
| 790 | wr_ok<='1'; |
---|
| 791 | else |
---|
| 792 | rd_ok<='1'; |
---|
| 793 | wr_ok<='0'; |
---|
| 794 | n_i<=0; |
---|
| 795 | end if; |
---|
| 796 | elsif n=3 then |
---|
| 797 | if dma_wr_grant='1' then |
---|
| 798 | rd_ok<='0'; |
---|
| 799 | wr_ok<='1'; |
---|
| 800 | n_i<=n+1; |
---|
| 801 | end if; |
---|
| 802 | elsif n=4 then |
---|
| 803 | if dma_wr_grant='1' then |
---|
| 804 | rd_ok<='0'; |
---|
| 805 | wr_ok<='1'; |
---|
| 806 | |
---|
| 807 | n_i<=5; |
---|
| 808 | end if; |
---|
| 809 | elsif n=5 then |
---|
| 810 | Next_Ex2_state <= ex2_set_busy; |
---|
| 811 | n_i<=0; |
---|
| 812 | rd_ok<='0'; |
---|
| 813 | wr_ok<='0'; |
---|
| 814 | mode_get:='0'; |
---|
| 815 | match_get:='0'; |
---|
| 816 | end if; |
---|
| 817 | |
---|
| 818 | |
---|
| 819 | |
---|
| 820 | -- dest_address_i<=std_logic_vector(to_unsigned(core_base_adr+4,16));--Adr de gest de la transaction |
---|
| 821 | when ex2_put5 => |
---|
| 822 | Next_Ex2_state <= Ex2_Ready; -- fin du mpi_put |
---|
| 823 | |
---|
| 824 | when ex2_spawn1 => |
---|
| 825 | |
---|
| 826 | if n<2 then |
---|
| 827 | n_e:=n; |
---|
| 828 | read_nocdat_fsm(switch_data_available,rd_ok,wr_ok,P_len_i,n_e,n); |
---|
| 829 | n_i<=n_e; |
---|
| 830 | Rec_Data_i(2)<=Switch_port_out_data; |
---|
| 831 | elsif n=2 then |
---|
| 832 | Rec_Data_i(3)<=Switch_port_out_data; |
---|
| 833 | Result_i<=Switch_port_out_data; |
---|
| 834 | Data_to_ram<=Switch_port_out_data; |
---|
| 835 | n_i<=n+1; |
---|
| 836 | rd_ok<='1'; |
---|
| 837 | elsif n=3 then |
---|
| 838 | if data_to_ram(7 downto 4)=SPAWN_LOAD then |
---|
| 839 | Result_i<=data_to_ram; |
---|
| 840 | wr_ok<='1'; --permet d'activer Init de Ex_4 |
---|
| 841 | elsif data_to_ram(7 downto 4)=SPAWN_COMP then |
---|
| 842 | Result_i<=data_to_ram; |
---|
| 843 | wr_ok<='0'; --permet d'activer Init de Ex_4 |
---|
| 844 | |
---|
| 845 | elsif data_to_ram(7 downto 4)=SPAWN_ERR then |
---|
| 846 | Result_i<=data_to_ram; |
---|
| 847 | wr_ok<='0'; --permet d'activer Init de Ex_4 |
---|
| 848 | else |
---|
| 849 | Result_i<=(others=>'0'); |
---|
| 850 | |
---|
| 851 | end if; |
---|
| 852 | n_i<=n+1; |
---|
| 853 | rd_ok<='0'; |
---|
| 854 | elsif n=4 then |
---|
| 855 | wr_ok<='1'; |
---|
| 856 | if AppInitAck='1' then |
---|
| 857 | wr_ok<='0'; |
---|
| 858 | rd_ok<='0'; |
---|
| 859 | n_i<=n+1; |
---|
| 860 | end if; |
---|
| 861 | elsif n=5 then |
---|
| 862 | wr_ok<='0'; |
---|
| 863 | rd_ok<='0'; |
---|
| 864 | n_i<=0; |
---|
| 865 | Next_Ex2_state <=Ex2_Ready; |
---|
| 866 | end if; |
---|
| 867 | when Ex2_Spawn2=> |
---|
| 868 | Next_Ex2_state <=Ex2_Ready; |
---|
| 869 | when ex2_get1 => rd_ok<='0'; --ne pas autoriser la lecture du switch |
---|
| 870 | --ack_state<=next_ack_state; --MAE d'envoie de AR |
---|
| 871 | if n=0 then |
---|
| 872 | instr_ack_i<='1'; --activer l'envoie de l'accusé de réception |
---|
| 873 | data_to_write_fifo<=to_fifo_ack; |
---|
| 874 | wr_ok<=wr_ack; |
---|
| 875 | if sent_ack='1' then |
---|
| 876 | n_i<=1; |
---|
| 877 | instr_ack_i<='0'; |
---|
| 878 | wr_ok<='0'; |
---|
| 879 | --if switch_data_available='1' then |
---|
| 880 | rd_ok<='0';-- |
---|
| 881 | --P_len<=P_len-1; |
---|
| 882 | --end if; |
---|
| 883 | end if; |
---|
| 884 | |
---|
| 885 | elsif n=1 then |
---|
| 886 | if switch_data_available='1' then |
---|
| 887 | if fifo_full = '0' then -- conversion du get en put en empilement dans le fifo |
---|
| 888 | data_to_write_fifo <= MPI_PUT & switch_port_out_data(3 downto 0);--la destination du Put |
---|
| 889 | wr_ok<='1'; |
---|
| 890 | rd_ok<='1'; --autoriser la lecture du crossbar |
---|
| 891 | P_len_i<=P_len-1; |
---|
| 892 | n_i<=n+1; |
---|
| 893 | else |
---|
| 894 | Wr_ok<='0'; |
---|
| 895 | Rd_ok<='0'; |
---|
| 896 | end if; |
---|
| 897 | else |
---|
| 898 | Wr_ok<='0'; |
---|
| 899 | rd_ok<='0'; |
---|
| 900 | end if; |
---|
| 901 | elsif n=2 then |
---|
| 902 | if switch_data_available='1' then |
---|
| 903 | if fifo_full = '0' then -- conversion du get en put en empilement dans le fifo |
---|
| 904 | --data_to_write_fifo <= MPI_PUT & switch_port_out_data(3 downto 0);--la destination du Put |
---|
| 905 | --P_len_i <= P_len-1;--le nombre d'octet qui restent à copier |
---|
| 906 | Next_Ex2_state <= ex2_get2; |
---|
| 907 | wr_ok<='0'; |
---|
| 908 | rd_ok<='0'; --autoriser la lecture du crossbar |
---|
| 909 | n_i<=0; |
---|
| 910 | else |
---|
| 911 | rd_ok<='0'; |
---|
| 912 | wr_ok<='0'; |
---|
| 913 | end if; |
---|
| 914 | else |
---|
| 915 | rd_ok<='0'; |
---|
| 916 | wr_ok<='0'; |
---|
| 917 | end if; |
---|
| 918 | end if; |
---|
| 919 | when ex2_get2 => if P_len>0 then |
---|
| 920 | if fifo_full = '0' and switch_data_available ='1' then |
---|
| 921 | data_to_write_fifo <= switch_port_out_data;--la longueur initiale du GET |
---|
| 922 | p_len_i <= P_len - 1; |
---|
| 923 | Next_Ex2_state <= ex2_get2; |
---|
| 924 | wr_ok<='1'; |
---|
| 925 | Rd_ok<='1'; |
---|
| 926 | elsE |
---|
| 927 | |
---|
| 928 | wr_ok<='0'; |
---|
| 929 | Rd_ok<='0'; |
---|
| 930 | END IF; |
---|
| 931 | else |
---|
| 932 | if n=0 then |
---|
| 933 | if fifo_full='0' then |
---|
| 934 | wr_ok<='0';--une impulsion en plus |
---|
| 935 | n_i<=n+1; |
---|
| 936 | Next_Ex2_state <= ex2_get2; |
---|
| 937 | else |
---|
| 938 | wr_ok<='0'; |
---|
| 939 | end if; |
---|
| 940 | |
---|
| 941 | else |
---|
| 942 | Next_Ex2_state <= ex2_get3; |
---|
| 943 | n_i<=0; |
---|
| 944 | wr_ok<='0'; |
---|
| 945 | end if; |
---|
| 946 | rd_ok<='0'; |
---|
| 947 | end if; |
---|
| 948 | i:=to_integer(unsigned(Rec_Data(0)(3 downto 0))); |
---|
| 949 | Rec_WPost_i(i)<='1'; --indiquer que ce port a emis des données ! |
---|
| 950 | |
---|
| 951 | --préparer en avance l'adresse de lecture/écriture |
---|
| 952 | dest_address_i<=std_logic_vector(to_unsigned(core_base_adr+4,16)); |
---|
| 953 | when ex2_get3 => wr_ok<='0'; |
---|
| 954 | if dma_rd_grant='1' then -- fin du mpi_get |
---|
| 955 | Next_Ex2_state <= ex2_get4; |
---|
| 956 | n_i<=0; |
---|
| 957 | --activer le bit sending du registre de transfert |
---|
| 958 | else |
---|
| 959 | Next_Ex2_state <= ex2_get3; |
---|
| 960 | end if; |
---|
| 961 | |
---|
| 962 | dest_address_i<=std_logic_vector(to_unsigned(core_base_adr+4,16)); |
---|
| 963 | when ex2_get4 => if n <4 then |
---|
| 964 | |
---|
| 965 | dma_wr<='1'; --demander un accès exclusif au bus |
---|
| 966 | dma_rd<='1'; -- pour éviter une mauvaise mise à jour des données |
---|
| 967 | else |
---|
| 968 | dma_wr<='0'; |
---|
| 969 | dma_rd<='0'; |
---|
| 970 | end if; |
---|
| 971 | if n=0 then |
---|
| 972 | if dma_rd_grant='1' then |
---|
| 973 | n_i<=n+1; |
---|
| 974 | |
---|
| 975 | end if; |
---|
| 976 | rd_ok<='1'; |
---|
| 977 | wr_ok<='0'; |
---|
| 978 | elsif n=1 then |
---|
| 979 | if dma_rd_grant='1' then |
---|
| 980 | n_i<=n+1; |
---|
| 981 | |
---|
| 982 | end if; |
---|
| 983 | rd_ok<='1'; |
---|
| 984 | wr_ok<='0'; |
---|
| 985 | |
---|
| 986 | elsif n=2 then |
---|
| 987 | if dma_rd_grant='1' and dma_wr_grant='1' then |
---|
| 988 | n_i<=n+1; |
---|
| 989 | tempval:=Ram_data_out; |
---|
| 990 | tempval(2):='1'; --mise à 1 du Bit DSending |
---|
| 991 | --tempval(5):='0'; --Mise à 0 du Bit Sent |
---|
| 992 | data_to_ram<=tempval; |
---|
| 993 | rd_ok<='1'; |
---|
| 994 | wr_ok<='0'; |
---|
| 995 | else |
---|
| 996 | rd_ok<='1'; |
---|
| 997 | wr_ok<='0'; |
---|
| 998 | n_i<=0; |
---|
| 999 | end if; |
---|
| 1000 | |
---|
| 1001 | elsif n=3 then |
---|
| 1002 | if dma_wr_grant = '1' then |
---|
| 1003 | n_i<=n+1; |
---|
| 1004 | rd_ok<='0'; |
---|
| 1005 | wr_ok<='1'; |
---|
| 1006 | end if; |
---|
| 1007 | elsif n=4 then |
---|
| 1008 | if dma_wr_grant = '1' then |
---|
| 1009 | n_i<=0; |
---|
| 1010 | Next_Ex2_state <= Ex2_Ready; -- fin du mpi_get |
---|
| 1011 | else |
---|
| 1012 | rd_ok<='0'; |
---|
| 1013 | wr_ok<='1'; |
---|
| 1014 | --n<=n-1; |
---|
| 1015 | end if; |
---|
| 1016 | end if; |
---|
| 1017 | |
---|
| 1018 | |
---|
| 1019 | dest_address_i<=std_logic_vector(to_unsigned(core_base_adr+4,16)); |
---|
| 1020 | when ex2_Set_Busy => if n=0 then --set busy bit of the instruction |
---|
| 1021 | dest_address_i<=std_logic_vector(to_unsigned(core_base_adr+4,16)); |
---|
| 1022 | n_i<=1; |
---|
| 1023 | if Gpost_Set='1' then |
---|
| 1024 | if (rec_wpost=gpost) and RGET='0' then |
---|
| 1025 | Wbusy<='0'; |
---|
| 1026 | Gpost_Set_i<='0'; |
---|
| 1027 | GComp_i<=(others=>'0'); |
---|
| 1028 | rec_wpost_i<=(others=>'0');--reset des messages reçu |
---|
| 1029 | else |
---|
| 1030 | Wbusy<='1'; |
---|
| 1031 | end if; |
---|
| 1032 | else |
---|
| 1033 | |
---|
| 1034 | n_i<=2; |
---|
| 1035 | end if; |
---|
| 1036 | if RGET='1' then |
---|
| 1037 | WBusy<='1'; |
---|
| 1038 | end if; |
---|
| 1039 | elsif n=1 then |
---|
| 1040 | sb_start<='1'; |
---|
| 1041 | sb_bitMask<=x"40";--6e bit à 1 |
---|
| 1042 | sb_bitval<=WBusy; |
---|
| 1043 | if sb_done='1' then |
---|
| 1044 | n_i<=2; |
---|
| 1045 | sb_start<='0'; |
---|
| 1046 | sb_bitval<='0'; |
---|
| 1047 | end if; |
---|
| 1048 | elsif n=2 then |
---|
| 1049 | Next_Ex2_state<=Ex2_Ready; |
---|
| 1050 | n_i<=0; |
---|
| 1051 | end if; |
---|
| 1052 | -- execution du barrier |
---|
| 1053 | when ex2_barrier1 => if switch_data_available = '1' then |
---|
| 1054 | pading_data <= switch_port_out_data; |
---|
| 1055 | Next_Ex2_state <= ex2_barrier2; |
---|
| 1056 | else |
---|
| 1057 | Next_Ex2_state <= ex2_barrier1; |
---|
| 1058 | end if; |
---|
| 1059 | when ex2_barrier2 => if packet_type = MPI_BARRIER_REACHED then |
---|
| 1060 | barrier_counter <= barrier_counter + 1; |
---|
| 1061 | Next_Ex2_state <= ex2_barrier4; |
---|
| 1062 | else |
---|
| 1063 | Next_Ex2_state <= ex2_barrier3; |
---|
| 1064 | end if; |
---|
| 1065 | when ex2_barrier3 => if n < 10 then |
---|
| 1066 | n_i<= n + 1; |
---|
| 1067 | Next_Ex2_state <= ex2_barrier3; |
---|
| 1068 | else |
---|
| 1069 | Next_Ex2_state <= Ex2_Ready; |
---|
| 1070 | end if; |
---|
| 1071 | when ex2_barrier4 => if barrier_counter = nprocs then -- entete du packet MPI_BARRIER_COMPLETED |
---|
| 1072 | data_to_write_fifo <= MPI_BARRIER_COMPLETED & "0000"; |
---|
| 1073 | Next_Ex2_state <= ex2_barrier5; |
---|
| 1074 | else |
---|
| 1075 | Next_Ex2_state <= Ex2_Ready; |
---|
| 1076 | end if; |
---|
| 1077 | when ex2_barrier5 => if fifo_full = '0' then -- taille du packet MPI_BARRIER_COMPLETED |
---|
| 1078 | data_to_write_fifo <= "00000011"; |
---|
| 1079 | Next_Ex2_state <= ex2_barrier6; |
---|
| 1080 | else |
---|
| 1081 | Next_Ex2_state <= ex2_barrier5; |
---|
| 1082 | end if; |
---|
| 1083 | when ex2_barrier6 => if fifo_full ='0' then -- troisième octet du packet MPI_BARRIER_COMPLETED |
---|
| 1084 | data_to_write_fifo <= "00000000"; |
---|
| 1085 | Next_Ex2_state <= ex2_barrier7; |
---|
| 1086 | else |
---|
| 1087 | Next_Ex2_state <= ex2_barrier6; |
---|
| 1088 | end if; |
---|
| 1089 | when ex2_barrier7 => if fifo_full = '0' then |
---|
| 1090 | barrier_counter <= "0000"; |
---|
| 1091 | Next_Ex2_state <= Ex2_Ready; |
---|
| 1092 | else |
---|
| 1093 | Next_Ex2_state <= ex2_barrier7; |
---|
| 1094 | end if; |
---|
| 1095 | |
---|
| 1096 | when others => Next_Ex2_state <= Ex2_Ready; |
---|
| 1097 | end case; |
---|
| 1098 | |
---|
| 1099 | end process; |
---|
| 1100 | |
---|
| 1101 | -- sortie de la machine à etat |
---|
| 1102 | -- |
---|
| 1103 | ex2_fsm_action : process(Ex2_state, Ex2_on,fifo_full, P_len, data_to_write_fifo, packet_type,Data_To_Ram,Dma_rd,Dma_wr, |
---|
| 1104 | switch_data_available,switch_port_out_data,sb_ram_data_in,Ram_data_out,rd_ok,wr_ok,sb_ram_wr,sb_ram_rd,sb_dma_wr_request,sb_dma_rd_request, |
---|
| 1105 | appInitAck,n) |
---|
| 1106 | variable transact : std_logic_vector(Word-1 downto 0); |
---|
| 1107 | begin |
---|
| 1108 | -- code fonctionnel |
---|
| 1109 | case Ex2_state is |
---|
| 1110 | when Ex2_Ready => fifo_wr_en <= '0'; |
---|
| 1111 | switch_port_out_rd_en <= '0'; |
---|
| 1112 | packet_received <= '0'; |
---|
| 1113 | dma_wr_request <= '0'; |
---|
| 1114 | dma_rd_request <= '0'; |
---|
| 1115 | barrier_completed <= '0'; |
---|
| 1116 | Ram_data_in<=(others=>'0'); |
---|
| 1117 | Ram_rd<='0'; |
---|
| 1118 | Ram_wr<='0'; |
---|
| 1119 | Ready<='1'; |
---|
| 1120 | AppInitReq<='0'; |
---|
| 1121 | when fetch_packet_type => fifo_wr_en <= '0'; |
---|
| 1122 | switch_port_out_rd_en <= rd_ok; |
---|
| 1123 | packet_received <= '0'; |
---|
| 1124 | dma_wr_request <= '0'; |
---|
| 1125 | dma_rd_request <= '0'; |
---|
| 1126 | barrier_completed <= '0'; |
---|
| 1127 | Ram_data_in<=(others=>'0'); |
---|
| 1128 | Ram_rd<='0'; |
---|
| 1129 | Ram_wr<='0'; |
---|
| 1130 | Ready<='0'; |
---|
| 1131 | AppInitReq<='0'; |
---|
| 1132 | |
---|
| 1133 | |
---|
| 1134 | when decode_packet_type => fifo_wr_en <= '0'; |
---|
| 1135 | switch_port_out_rd_en <= rd_ok; |
---|
| 1136 | packet_received <= '0'; |
---|
| 1137 | dma_wr_request <= '0'; |
---|
| 1138 | dma_rd_request <= '0'; |
---|
| 1139 | Ram_rd<='0'; |
---|
| 1140 | Ram_wr<='0'; |
---|
| 1141 | Ram_data_in<=(others=>'0'); |
---|
| 1142 | barrier_completed <= '0'; |
---|
| 1143 | AppInitReq<='0'; |
---|
| 1144 | Ready<='0'; |
---|
| 1145 | |
---|
| 1146 | when decode_packet_type2 => fifo_wr_en <= '0'; |
---|
| 1147 | switch_port_out_rd_en <= '0'; |
---|
| 1148 | packet_received <= '0'; |
---|
| 1149 | dma_wr_request <= '0'; |
---|
| 1150 | dma_rd_request <= '0'; |
---|
| 1151 | Ram_rd<='0'; |
---|
| 1152 | Ram_wr<='0'; |
---|
| 1153 | Ram_data_in<=(others=>'0'); |
---|
| 1154 | barrier_completed <= '0'; |
---|
| 1155 | AppInitReq<='0'; |
---|
| 1156 | Ready<='0'; |
---|
| 1157 | when fetch_addresses => fifo_wr_en <= '0'; |
---|
| 1158 | switch_port_out_rd_en <= rd_ok; |
---|
| 1159 | packet_received <= '0'; |
---|
| 1160 | dma_wr_request <= '0'; |
---|
| 1161 | dma_rd_request <= '0'; |
---|
| 1162 | Ram_rd<='0'; |
---|
| 1163 | Ram_wr<='0'; |
---|
| 1164 | Ram_data_in<=(others=>'0'); |
---|
| 1165 | barrier_completed <= '0'; |
---|
| 1166 | AppInitReq<='0'; |
---|
| 1167 | Ready<='0'; |
---|
| 1168 | when ex2_ack1 |ex2_Wsync => |
---|
| 1169 | Ready<='0'; |
---|
| 1170 | switch_port_out_rd_en<=rd_ok; |
---|
| 1171 | fifo_wr_en <= '0'; |
---|
| 1172 | packet_received <= '0'; |
---|
| 1173 | AppInitReq<='0'; |
---|
| 1174 | barrier_completed <= '0'; |
---|
| 1175 | dma_rd_request <= sb_dma_rd_request; |
---|
| 1176 | dma_wr_request <= sb_dma_wr_request; |
---|
| 1177 | Ram_rd<=sb_ram_rd; |
---|
| 1178 | Ram_wr<=sb_ram_wr; |
---|
| 1179 | sb_ram_data_out<=Ram_data_out; |
---|
| 1180 | Ram_data_in<=sb_ram_data_in; |
---|
| 1181 | when ex2_ack2|Ex2_WCOMP => |
---|
| 1182 | Ready<='0'; |
---|
| 1183 | switch_port_out_rd_en<='0'; |
---|
| 1184 | fifo_wr_en <= '0'; |
---|
| 1185 | packet_received <= '0'; |
---|
| 1186 | AppInitReq<='0'; |
---|
| 1187 | barrier_completed <= '0'; |
---|
| 1188 | dma_rd_request <= dma_rd; |
---|
| 1189 | dma_wr_request <= '0'; |
---|
| 1190 | Ram_rd<=rd_ok; |
---|
| 1191 | Ram_wr<='0'; |
---|
| 1192 | when ex2_ack3 => |
---|
| 1193 | Ready<='0'; |
---|
| 1194 | switch_port_out_rd_en<=rd_ok; |
---|
| 1195 | fifo_wr_en <= '0'; |
---|
| 1196 | packet_received <= '0'; |
---|
| 1197 | AppInitReq<='0'; |
---|
| 1198 | barrier_completed <= '0'; |
---|
| 1199 | dma_rd_request <= sb_dma_rd_request; |
---|
| 1200 | dma_wr_request <= sb_dma_wr_request; |
---|
| 1201 | Ram_rd<=sb_ram_rd; |
---|
| 1202 | Ram_wr<=sb_ram_wr; |
---|
| 1203 | sb_ram_data_out<=Ram_data_out; |
---|
| 1204 | Ram_data_in<=sb_ram_data_in; |
---|
| 1205 | when ex2_put1 => fifo_wr_en <= wr_ok; |
---|
| 1206 | switch_port_out_rd_en <= '0'; |
---|
| 1207 | packet_received <= '0'; |
---|
| 1208 | dma_wr_request <= '1'; |
---|
| 1209 | dma_rd_request <= '0'; |
---|
| 1210 | Ram_rd<='0'; |
---|
| 1211 | Ram_wr<='0'; |
---|
| 1212 | Ram_data_in<=(others=>'0'); |
---|
| 1213 | barrier_completed <= '0'; |
---|
| 1214 | AppInitReq<='0'; |
---|
| 1215 | Ready<='0'; |
---|
| 1216 | |
---|
| 1217 | when ex2_put2 => Ready<='0'; |
---|
| 1218 | fifo_wr_en <= '0'; |
---|
| 1219 | switch_port_out_rd_en <=rd_ok; |
---|
| 1220 | |
---|
| 1221 | if rd_ok = '1' then |
---|
| 1222 | |
---|
| 1223 | Ram_data_in<=switch_port_out_data; |
---|
| 1224 | else |
---|
| 1225 | Ram_data_in<=data_to_ram; |
---|
| 1226 | end if; |
---|
| 1227 | Ram_wr<=wr_ok; |
---|
| 1228 | Ram_rd<='0'; |
---|
| 1229 | packet_received <= '0'; |
---|
| 1230 | dma_rd_request <= '0'; |
---|
| 1231 | dma_wr_request <= '1'; |
---|
| 1232 | AppInitReq<='0'; |
---|
| 1233 | barrier_completed <= '0'; |
---|
| 1234 | when ex2_put3 => Ready<='0'; |
---|
| 1235 | fifo_wr_en <= '0'; |
---|
| 1236 | switch_port_out_rd_en <='0'; |
---|
| 1237 | --ne pas corrompre le contenu de la RAM |
---|
| 1238 | --Ram_data_in<=data_to_ram; |
---|
| 1239 | Ram_wr<='0'; |
---|
| 1240 | Ram_rd<='1'; |
---|
| 1241 | packet_received <= '0'; |
---|
| 1242 | dma_rd_request <= '1'; |
---|
| 1243 | dma_wr_request <= '0'; |
---|
| 1244 | AppInitReq<='0'; |
---|
| 1245 | barrier_completed <= '0'; |
---|
| 1246 | |
---|
| 1247 | |
---|
| 1248 | when ex2_put4 => fifo_wr_en <= '0'; |
---|
| 1249 | Ready<='0'; |
---|
| 1250 | switch_port_out_rd_en <= '0'; |
---|
| 1251 | packet_received <= '1'; |
---|
| 1252 | dma_rd_request <= dma_rd; |
---|
| 1253 | dma_wr_request <=dma_wr; |
---|
| 1254 | Ram_wr<=wr_ok; |
---|
| 1255 | Ram_rd<=rd_ok; |
---|
| 1256 | AppInitReq<='0'; |
---|
| 1257 | barrier_completed <= '0'; |
---|
| 1258 | Ram_data_in<=data_to_ram;--Ram_data_in or "00000010"; -- le résultat de l'exécution |
---|
| 1259 | |
---|
| 1260 | when ex2_put5 => |
---|
| 1261 | Ready<='0'; |
---|
| 1262 | switch_port_out_rd_en<='0'; |
---|
| 1263 | fifo_wr_en <= '0'; |
---|
| 1264 | packet_received <= '1'; |
---|
| 1265 | AppInitReq<='0'; |
---|
| 1266 | barrier_completed <= '0'; |
---|
| 1267 | dma_rd_request <= dma_rd; |
---|
| 1268 | dma_wr_request <= dma_wr; |
---|
| 1269 | Ram_rd<=rd_ok; |
---|
| 1270 | Ram_wr<=wr_ok; |
---|
| 1271 | Ram_data_in<=data_to_ram; |
---|
| 1272 | --Result <=(1=>'1',others=>'0'); --put completed |
---|
| 1273 | |
---|
| 1274 | when ex2_get1=> fifo_wr_en <= wr_ok; |
---|
| 1275 | switch_port_out_rd_en <= rd_ok; |
---|
| 1276 | packet_received <= '0'; |
---|
| 1277 | dma_wr_request <= '0'; |
---|
| 1278 | dma_rd_request <= '0'; |
---|
| 1279 | Ram_rd<='0'; |
---|
| 1280 | Ram_wr<='0'; |
---|
| 1281 | Ram_data_in<=(others=>'0'); |
---|
| 1282 | barrier_completed <= '0'; |
---|
| 1283 | AppInitReq<='0'; |
---|
| 1284 | Ready<='0'; |
---|
| 1285 | |
---|
| 1286 | when ex2_get2 => |
---|
| 1287 | switch_port_out_rd_en <=rd_ok; |
---|
| 1288 | fifo_wr_en <= Wr_ok; |
---|
| 1289 | Ready<='0'; |
---|
| 1290 | packet_received <= '0'; |
---|
| 1291 | dma_rd_request <= '0'; |
---|
| 1292 | dma_wr_request <= '0'; |
---|
| 1293 | Ram_rd<='0'; |
---|
| 1294 | Ram_wr<='0'; |
---|
| 1295 | Ram_data_in<=(others=>'0'); |
---|
| 1296 | barrier_completed <= '0'; |
---|
| 1297 | AppInitReq<='0'; |
---|
| 1298 | |
---|
| 1299 | when ex2_get3 => fifo_wr_en <= '0'; |
---|
| 1300 | Ready<='0'; |
---|
| 1301 | switch_port_out_rd_en <= '0'; |
---|
| 1302 | packet_received <= '1'; |
---|
| 1303 | dma_rd_request <= '1'; |
---|
| 1304 | dma_wr_request <='0'; |
---|
| 1305 | Ram_wr<='0'; |
---|
| 1306 | Ram_rd<='1'; |
---|
| 1307 | AppInitReq<='0'; |
---|
| 1308 | barrier_completed <= '0'; |
---|
| 1309 | --Ram_data_out<=Ram_data_in or "00000010"; -- activer le bit DSending |
---|
| 1310 | |
---|
| 1311 | when ex2_get4 => |
---|
| 1312 | Ready<='0'; |
---|
| 1313 | barrier_completed <= '0'; |
---|
| 1314 | switch_port_out_rd_en<='0'; |
---|
| 1315 | fifo_wr_en <= '0'; |
---|
| 1316 | packet_received <= '1'; |
---|
| 1317 | AppInitReq<='0'; |
---|
| 1318 | dma_rd_request <= dma_rd; |
---|
| 1319 | dma_wr_request <= dma_wr; |
---|
| 1320 | Ram_rd<=rd_ok; |
---|
| 1321 | Ram_wr<=wr_ok; |
---|
| 1322 | Ram_data_in<=data_to_ram; --activer le bit DSending |
---|
| 1323 | |
---|
| 1324 | |
---|
| 1325 | when ex2_barrier1 => fifo_wr_en <= '0'; |
---|
| 1326 | switch_port_out_rd_en <= switch_data_available; |
---|
| 1327 | packet_received <= '0'; |
---|
| 1328 | dma_wr_request <= '0'; |
---|
| 1329 | dma_rd_request <= '0'; |
---|
| 1330 | Ram_rd<='0'; |
---|
| 1331 | Ram_wr<='0'; |
---|
| 1332 | Ram_data_in<=(others=>'0'); |
---|
| 1333 | barrier_completed <= '0'; |
---|
| 1334 | Ready<='0'; |
---|
| 1335 | AppInitReq<='0'; |
---|
| 1336 | |
---|
| 1337 | when ex2_barrier2 => fifo_wr_en <= '0'; |
---|
| 1338 | Ready<='0'; |
---|
| 1339 | switch_port_out_rd_en <='0'; |
---|
| 1340 | packet_received <= '0'; |
---|
| 1341 | dma_wr_request <= '0'; |
---|
| 1342 | dma_rd_request <= '0'; |
---|
| 1343 | Ram_rd<='0'; |
---|
| 1344 | Ram_wr<='0'; |
---|
| 1345 | Ram_data_in<=(others=>'0'); |
---|
| 1346 | barrier_completed <= '0'; |
---|
| 1347 | AppInitReq<='0'; |
---|
| 1348 | |
---|
| 1349 | when ex2_barrier3 => fifo_wr_en <= '0'; |
---|
| 1350 | switch_port_out_rd_en <='0'; |
---|
| 1351 | Ready<='0'; |
---|
| 1352 | packet_received <= '0'; |
---|
| 1353 | dma_wr_request <= '0'; |
---|
| 1354 | dma_rd_request <= '0'; |
---|
| 1355 | Ram_rd<='0'; |
---|
| 1356 | Ram_wr<='0'; |
---|
| 1357 | Ram_data_in<=(others=>'0'); |
---|
| 1358 | barrier_completed <= '1'; |
---|
| 1359 | AppInitReq<='0'; |
---|
| 1360 | |
---|
| 1361 | when ex2_barrier4 => fifo_wr_en <= '0'; |
---|
| 1362 | switch_port_out_rd_en <='0'; |
---|
| 1363 | packet_received <= '0'; |
---|
| 1364 | dma_wr_request <= '0'; |
---|
| 1365 | dma_rd_request <= '0'; |
---|
| 1366 | Ram_rd<='0'; |
---|
| 1367 | Ram_wr<='0'; |
---|
| 1368 | Ram_data_in<=(others=>'0'); |
---|
| 1369 | barrier_completed <= '0'; |
---|
| 1370 | AppInitReq<='0'; |
---|
| 1371 | Ready<='0'; |
---|
| 1372 | |
---|
| 1373 | |
---|
| 1374 | when ex2_barrier5 => fifo_wr_en <= not(fifo_full); |
---|
| 1375 | switch_port_out_rd_en <='0'; |
---|
| 1376 | packet_received <= '0'; |
---|
| 1377 | dma_wr_request <= '0'; |
---|
| 1378 | dma_rd_request <= '0'; |
---|
| 1379 | Ram_rd<='0'; |
---|
| 1380 | Ram_wr<='0'; |
---|
| 1381 | Ram_data_in<=(others=>'0'); |
---|
| 1382 | barrier_completed <= '0'; |
---|
| 1383 | AppInitReq<='0'; |
---|
| 1384 | Ready<='0'; |
---|
| 1385 | |
---|
| 1386 | when ex2_barrier6 => fifo_wr_en <= not(fifo_full); |
---|
| 1387 | switch_port_out_rd_en <= '0'; |
---|
| 1388 | packet_received <= '0'; |
---|
| 1389 | dma_wr_request <= '0'; |
---|
| 1390 | dma_rd_request <= '0'; |
---|
| 1391 | Ram_rd<='0'; |
---|
| 1392 | Ram_wr<='0'; |
---|
| 1393 | Ram_data_in<=(others=>'0'); |
---|
| 1394 | barrier_completed <= '0'; |
---|
| 1395 | AppInitReq<='0'; |
---|
| 1396 | Ready<='0'; |
---|
| 1397 | |
---|
| 1398 | when ex2_barrier7 => fifo_wr_en <= not(fifo_full); |
---|
| 1399 | switch_port_out_rd_en <= '0'; |
---|
| 1400 | packet_received <= '0'; |
---|
| 1401 | dma_wr_request <= '0'; |
---|
| 1402 | dma_rd_request <= '0'; |
---|
| 1403 | Ram_rd<='0'; |
---|
| 1404 | Ram_wr<='0'; |
---|
| 1405 | Ram_data_in<=(others=>'0'); |
---|
| 1406 | barrier_completed <= '0'; |
---|
| 1407 | AppInitReq<='0'; |
---|
| 1408 | Ready<='0'; |
---|
| 1409 | |
---|
| 1410 | when ex2_spawn1 => fifo_wr_en <= '0'; |
---|
| 1411 | switch_port_out_rd_en <= rd_ok;--switch_data_available; |
---|
| 1412 | packet_received <= '0'; |
---|
| 1413 | dma_wr_request <= '0'; |
---|
| 1414 | dma_rd_request <= '0'; |
---|
| 1415 | Ram_rd<='0'; |
---|
| 1416 | Ram_wr<='0'; |
---|
| 1417 | barrier_completed <= '0'; |
---|
| 1418 | Ready<='0'; |
---|
| 1419 | Ram_data_in<=(others =>'0'); |
---|
| 1420 | AppInitReq<=wr_ok; |
---|
| 1421 | when ex2_Spawn2 => Ready<='0'; |
---|
| 1422 | fifo_wr_en <= '0'; |
---|
| 1423 | switch_port_out_rd_en <='0'; |
---|
| 1424 | |
---|
| 1425 | Ram_data_in<=data_to_ram; |
---|
| 1426 | |
---|
| 1427 | Ram_wr<=wr_ok; |
---|
| 1428 | Ram_rd<='0'; |
---|
| 1429 | packet_received <= '0'; |
---|
| 1430 | dma_rd_request <= '0'; |
---|
| 1431 | dma_wr_request <= '1'; |
---|
| 1432 | AppInitReq<='0'; |
---|
| 1433 | barrier_completed <= '0'; |
---|
| 1434 | when ex2_init1 => fifo_wr_en <= '0'; |
---|
| 1435 | switch_port_out_rd_en <= rd_ok;--switch_data_available; |
---|
| 1436 | packet_received <= '0'; |
---|
| 1437 | dma_wr_request <= '0'; |
---|
| 1438 | dma_rd_request <= '0'; |
---|
| 1439 | Ram_rd<='0'; |
---|
| 1440 | Ram_wr<='0'; |
---|
| 1441 | barrier_completed <= '0'; |
---|
| 1442 | Ready<='0'; |
---|
| 1443 | Ram_data_in<=(others =>'0'); |
---|
| 1444 | AppInitReq<=wr_ok; |
---|
| 1445 | |
---|
| 1446 | |
---|
| 1447 | when ex2_init2 => fifo_wr_en <= '0'; |
---|
| 1448 | switch_port_out_rd_en <='0'; |
---|
| 1449 | packet_received <= '0'; |
---|
| 1450 | dma_wr_request <= '0'; |
---|
| 1451 | dma_rd_request <= '0'; |
---|
| 1452 | Ram_rd<='0'; |
---|
| 1453 | Ram_wr<='0'; |
---|
| 1454 | barrier_completed <= '0'; |
---|
| 1455 | Ram_data_in<=(others =>'0'); |
---|
| 1456 | AppInitReq<= not(AppInitAck); |
---|
| 1457 | Ready<='0'; |
---|
| 1458 | |
---|
| 1459 | |
---|
| 1460 | when ex2_Set_Busy => |
---|
| 1461 | Ready<='0'; |
---|
| 1462 | switch_port_out_rd_en<='0'; |
---|
| 1463 | fifo_wr_en <= '0'; |
---|
| 1464 | packet_received <= '0'; |
---|
| 1465 | AppInitReq<='0'; |
---|
| 1466 | barrier_completed <= '0'; |
---|
| 1467 | dma_rd_request <= sb_dma_rd_request; |
---|
| 1468 | dma_wr_request <= sb_dma_wr_request; |
---|
| 1469 | Ram_rd<=sb_ram_rd; |
---|
| 1470 | Ram_wr<=sb_ram_wr; |
---|
| 1471 | sb_ram_data_out<=Ram_data_out; |
---|
| 1472 | Ram_data_in<=sb_ram_data_in; |
---|
| 1473 | when others => Ready<='1'; -- le module est à nouveau libre |
---|
| 1474 | fifo_wr_en <= '0'; |
---|
| 1475 | switch_port_out_rd_en <= '0'; |
---|
| 1476 | packet_received <= '0'; |
---|
| 1477 | dma_wr_request <= '0'; |
---|
| 1478 | dma_rd_request <= '0'; |
---|
| 1479 | barrier_completed <= '0'; |
---|
| 1480 | Ram_data_in<=(others=>'0'); |
---|
| 1481 | Ram_rd<='0'; |
---|
| 1482 | Ram_wr<='0'; |
---|
| 1483 | Ready<='1'; |
---|
| 1484 | AppInitReq<='0'; |
---|
| 1485 | end case; |
---|
| 1486 | |
---|
| 1487 | end process; |
---|
| 1488 | |
---|
| 1489 | ex2_fsm_sync:process(clk,reset) |
---|
| 1490 | |
---|
| 1491 | begin |
---|
| 1492 | |
---|
| 1493 | if reset = '1' then |
---|
| 1494 | ex2_state <= Ex2_Ready; |
---|
| 1495 | ack_state<=ack0; --MAE d'envoie de AR |
---|
| 1496 | n<=0; |
---|
| 1497 | P_len<=(others=>'0'); |
---|
| 1498 | GPost<=(others =>'0'); |
---|
| 1499 | else |
---|
| 1500 | if rising_edge(clk) then |
---|
| 1501 | ex2_state<=next_ex2_state; |
---|
| 1502 | ack_state<=next_ack_state; --MAE d'envoie de AR |
---|
| 1503 | n<=n_i; |
---|
| 1504 | P_len<=P_len_i; |
---|
| 1505 | dest_address <= dest_address_i; |
---|
| 1506 | Sent_ack<=sent_ack_i; |
---|
| 1507 | Instr_ack<=Instr_ack_i; |
---|
| 1508 | Ptr_Get<=Ptr_Get_i; |
---|
| 1509 | Rec_Wpost<=Rec_WPost_i; |
---|
| 1510 | GPost<=GPost_i; |
---|
| 1511 | GComp<=GComp_i; |
---|
| 1512 | GPost_set<=GPost_Set_i; |
---|
| 1513 | For i in 0 to 15 loop |
---|
| 1514 | Waited_get(i)<=Waited_get_i(i); |
---|
| 1515 | end loop; |
---|
| 1516 | for i in 0 to 3 loop |
---|
| 1517 | Rec_Data(i)<=Rec_Data_i(i); |
---|
| 1518 | end loop; |
---|
| 1519 | end if; |
---|
| 1520 | end if; |
---|
| 1521 | end process ex2_fsm_sync; |
---|
| 1522 | snd_ack:process (ack_state,reset,fifo_full,instr_ack,Dest_Ack,Packet_type) |
---|
| 1523 | --ce processus est chargé d'emettre l'accusé de réception pour chaque instruction reçu |
---|
| 1524 | begin |
---|
| 1525 | -- if rising_edge(clk) then |
---|
| 1526 | |
---|
| 1527 | if reset='1' then |
---|
| 1528 | next_ack_state<=ack0; |
---|
| 1529 | else |
---|
| 1530 | next_ack_state<=ack_state; |
---|
| 1531 | case ack_state is |
---|
| 1532 | when ack0 =>to_fifo_ack<=(others=>'0'); |
---|
| 1533 | Wr_ack<='0'; |
---|
| 1534 | if instr_ack='1' then |
---|
| 1535 | next_ack_state<=ack1; |
---|
| 1536 | to_fifo_ack <= MPI_ACK & Dest_ack; |
---|
| 1537 | wr_ack<='0'; |
---|
| 1538 | end if; |
---|
| 1539 | |
---|
| 1540 | sent_ack_i<='0'; |
---|
| 1541 | |
---|
| 1542 | when ack1 => if fifo_full = '0' then -- conversion envoie lack à l'emetteur |
---|
| 1543 | -- en empilement dans le fifo |
---|
| 1544 | to_fifo_ack <= MPI_ACK & Dest_ack; |
---|
| 1545 | next_ack_state <= ack2; |
---|
| 1546 | wr_ack<='1'; |
---|
| 1547 | else |
---|
| 1548 | wr_ack<='0'; |
---|
| 1549 | end if; |
---|
| 1550 | sent_ack_i<='0'; |
---|
| 1551 | when ack2 => if fifo_full = '0' then |
---|
| 1552 | to_fifo_ack <= "00000100";--la longueur |
---|
| 1553 | |
---|
| 1554 | next_ack_state <= ack3; |
---|
| 1555 | wr_ack<='1'; |
---|
| 1556 | else -- |
---|
| 1557 | next_ack_state <= ack2; |
---|
| 1558 | wr_ack<='0'; |
---|
| 1559 | |
---|
| 1560 | end if; |
---|
| 1561 | sent_ack_i<='0'; |
---|
| 1562 | when ack3 => if fifo_full = '0' then |
---|
| 1563 | to_fifo_ack <= "00000000";-- |
---|
| 1564 | next_ack_state <= ack4; |
---|
| 1565 | wr_ack<='1'; |
---|
| 1566 | else -- |
---|
| 1567 | next_ack_state <= ack3; |
---|
| 1568 | wr_ack<='0'; |
---|
| 1569 | |
---|
| 1570 | end if; |
---|
| 1571 | sent_ack_i<='0'; |
---|
| 1572 | when ack4 => if fifo_full = '0' then |
---|
| 1573 | to_fifo_ack <=packet_type & apprank ;--l'instruction et le rang de lacquitteur |
---|
| 1574 | next_ack_state <= ack5; |
---|
| 1575 | wr_ack<='1'; |
---|
| 1576 | sent_ack_i<='0'; |
---|
| 1577 | else -- |
---|
| 1578 | next_ack_state <= ack4; |
---|
| 1579 | wr_ack<='0'; |
---|
| 1580 | sent_ack_i<='0'; |
---|
| 1581 | end if; |
---|
| 1582 | when ack5 => if Instr_ack='0' then --dernier pulse |
---|
| 1583 | next_ack_state <= ack0; |
---|
| 1584 | else |
---|
| 1585 | next_ack_state <= ack6; |
---|
| 1586 | end if; |
---|
| 1587 | wr_ack<='0'; |
---|
| 1588 | sent_ack_i<='1'; |
---|
| 1589 | to_fifo_ack<=(others=>'1'); |
---|
| 1590 | when ack6 => if Instr_ack='0' then |
---|
| 1591 | next_ack_state <= ack0; |
---|
| 1592 | |
---|
| 1593 | end if; |
---|
| 1594 | wr_ack<='0'; |
---|
| 1595 | sent_ack_i<='1'; |
---|
| 1596 | to_fifo_ack<=(others=>'1'); |
---|
| 1597 | end case; |
---|
| 1598 | end if; |
---|
| 1599 | --end if; |
---|
| 1600 | end process; |
---|
| 1601 | |
---|
| 1602 | |
---|
| 1603 | end Behavioral; |
---|
| 1604 | |
---|