[100] | 1 | ---------------------------------------------------------------------------------- |
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| 2 | -- Company: |
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| 3 | -- Engineer: GAMOM |
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| 4 | -- |
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| 5 | -- Create Date: 05:37:34 03/06/2012 |
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| 6 | -- Design Name: |
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| 7 | -- Module Name: Ex0_Fsm - Behavioral |
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| 8 | -- Project Name: |
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| 9 | -- Target Devices: |
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| 10 | -- Tool versions: |
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| 11 | -- Description: Fournit le temps en µs depuis l'initialisation de la bibliothèque |
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| 12 | -- |
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| 13 | -- Dependencies: |
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| 14 | -- |
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| 15 | -- Revision: |
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| 16 | -- Revision 0.01 - File Created |
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| 17 | -- Additional Comments: |
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| 18 | -- |
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| 19 | ---------------------------------------------------------------------------------- |
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| 20 | library IEEE; |
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| 21 | use IEEE.STD_LOGIC_1164.ALL; |
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| 22 | library NocLib ; |
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| 23 | |
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| 24 | --use NocLib.CoreTypes.all; |
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| 25 | -- Uncomment the following library declaration if using |
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| 26 | -- arithmetic functions with Signed or Unsigned values |
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| 27 | use IEEE.NUMERIC_STD.ALL; |
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| 28 | |
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| 29 | -- Uncomment the following library declaration if instantiating |
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| 30 | -- any Xilinx primitives in this code. |
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| 31 | --library UNISIM; |
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| 32 | --use UNISIM.VComponents.all; |
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| 33 | |
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| 34 | entity Ex0_Fsm is |
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| 35 | Port ( Initialized : in STD_LOGIC; |
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| 36 | |
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| 37 | Instruction : in STD_LOGIC_VECTOR (7 downto 0); |
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| 38 | instruction_en: in STD_LOGIC; --ceci n'est pas nécessaire dans ce module |
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| 39 | -- car le module fonctionne en permanence. |
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| 40 | clk : in STD_LOGIC; |
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| 41 | reset : in STD_LOGIC; |
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| 42 | ClkRate : in STD_LOGIC_VECTOR; --la fréquence de l'horloge en Mhz |
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| 43 | uTimeResult : out STD_LOGIC_VECTOR; |
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| 44 | TickResult : out STD_LOGIC_VECTOR; |
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| 45 | OvFus : out STD_Logic:='0' |
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| 46 | ); |
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| 47 | end Ex0_Fsm; |
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| 48 | |
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| 49 | architecture Behavioral of Ex0_Fsm is |
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| 50 | |
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| 51 | --Use descriptive names for the states, like st1_reset, st2_search |
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| 52 | type state_type is (Init,COunt,UsOut,OverFlow); |
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| 53 | signal state, next_state : state_type; |
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| 54 | --Declare internal signals for all outputs of the state-machine |
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| 55 | signal Tick_Count: std_logic_vector(31 downto 0):=(others=>'0'); |
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| 56 | signal Time_Ucount :std_logic_vector(31 downto 0):=(others=>'0'); |
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| 57 | signal OvF,Ovf_us,ovF_i,zero :std_logic; -- overflow flag |
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| 58 | signal ClkR_Count : std_logic_vector(ClkRate'high downto ClkRate'low):=(others=>'0'); |
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| 59 | signal en : std_logic:='1'; |
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| 60 | --other outputs |
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| 61 | begin |
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| 62 | utime_PROC: process (clk) |
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| 63 | begin |
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| 64 | if (rising_edge(clk)) then |
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| 65 | if (reset = '1') or Initialized='0' then |
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| 66 | state <= init; |
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| 67 | -- Time_UCount<= (others=>'0'); |
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| 68 | -- Tick_Count <=(others=>'0'); |
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| 69 | else |
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| 70 | state <= next_state; |
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| 71 | TickResult<= Tick_Count; |
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| 72 | uTimeResult <=Time_ucount; |
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| 73 | OvF<=OvF_i; |
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| 74 | OvfUs<=Ovf_us; |
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| 75 | -- <output> <= <output>_i; |
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| 76 | -- assign other outputs to internal signals |
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| 77 | end if; |
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| 78 | end if; |
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| 79 | end process; |
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| 80 | |
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| 81 | --MOORE State-Machine - Outputs based on state only |
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| 82 | OUTPUT_DECODE: process (state) |
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| 83 | FUNCTION incr_vec(s1:std_logic_vector;en:std_logic) return std_logic_vector is |
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| 84 | --this function increments a std_logic_vector type by '1' |
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| 85 | VARIABLE V : std_logic_vector(s1'high downto s1'low) ; |
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| 86 | VARIABLE tb : std_logic_vector(s1'high downto s1'low); |
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| 87 | BEGIN |
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| 88 | tb(s1'low) := en; |
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| 89 | V := s1; |
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| 90 | for i in (V'low + 1) to V'high loop |
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| 91 | tb(i) := V(i - 1) and tb(i -1); |
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| 92 | end loop; |
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| 93 | for i in V'low to V'high loop |
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| 94 | if(tb(i) = '1') then |
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| 95 | V(i) := not(V(i)); |
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| 96 | end if; |
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| 97 | end loop; |
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| 98 | return V; |
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| 99 | end incr_vec; -- end function |
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| 100 | |
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| 101 | |
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| 102 | FUNCTION dcr_vec(s1:std_logic_vector;en:std_logic) return std_logic_vector is |
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| 103 | --this function decrements a std_logic_vector type by '1' |
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| 104 | VARIABLE V : std_logic_vector(s1'high downto s1'low) ; |
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| 105 | VARIABLE tb : std_logic_vector(s1'high downto s1'low); |
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| 106 | BEGIN |
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| 107 | tb(s1'low) := not(en); |
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| 108 | V := s1; |
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| 109 | for i in (V'low + 1) to V'high loop |
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| 110 | tb(i) := V(i - 1) or tb(i -1); |
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| 111 | end loop; |
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| 112 | for i in V'low to V'high loop |
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| 113 | if(tb(i) = '0') then |
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| 114 | V(i) := not(V(i)); |
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| 115 | end if; |
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| 116 | end loop; |
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| 117 | return V; |
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| 118 | end dcr_vec; -- end function |
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| 119 | FUNCTION all_ones(s1:std_logic_vector) return std_logic is |
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| 120 | --this function tells if all bits of a vector are '1' |
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| 121 | --return value Z is '1', then vector has all 1 bits |
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| 122 | --VARIABLE V : std_logic_vector(s1'high downto s1'low) ; |
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| 123 | VARIABLE Z : std_logic; |
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| 124 | BEGIN |
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| 125 | Z := s1(s1'low); |
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| 126 | FOR i IN (s1'low+1) to s1'high LOOP |
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| 127 | Z := Z AND s1(i); |
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| 128 | END LOOP; |
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| 129 | RETURN Z; |
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| 130 | END all_ones; -- end function |
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| 131 | FUNCTION all_zeros(s1:std_logic_vector) return std_logic is |
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| 132 | --this function tells if all bits of a vector are '0' |
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| 133 | --return value Z if '1', then vector has all 0 bits |
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| 134 | --VARIABLE V : std_logic_vector(s1'high downto s1'low) ; |
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| 135 | VARIABLE Z : std_logic; |
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| 136 | BEGIN |
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| 137 | Z := '0'; |
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| 138 | FOR i IN (s1'low) to s1'high LOOP |
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| 139 | Z := Z OR s1(i); |
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| 140 | END LOOP; |
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| 141 | RETURN not(Z); |
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| 142 | END all_zeros; -- end function |
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| 143 | |
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| 144 | begin |
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| 145 | --insert statements to decode internal output signals |
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| 146 | --below is simple example |
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| 147 | case state is |
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| 148 | When Init => |
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| 149 | Clkr_Count<=ClkRate; --initialiser le décompte |
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| 150 | Time_uCount<=( others =>'0'); -- mettre à 0 le compteur des µS |
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| 151 | Tick_Count<=(others =>'0'); --mettre à 0 les ticks |
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| 152 | When Count => |
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| 153 | Tick_count<=incr_vec(Tick_Count,en); |
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| 154 | ClkR_Count<=dcr_vec(Clkr_Count,en); --compteur de µs |
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| 155 | zero<=all_zeros(ClkR_Count); -- |
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| 156 | OvF_i<=All_ones(Tick_count); -- |
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| 157 | when UsOut => |
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| 158 | Time_Ucount<=incr_vec(time_ucount,en); |
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| 159 | Clkr_Count<=ClkRate; |
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| 160 | Tick_count<=incr_vec(Tick_Count,en); |
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| 161 | OvF_i<=All_ones(Tick_count); |
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| 162 | zero<='0'; |
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| 163 | OvF_us<=All_ones(Time_Ucount); |
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| 164 | when OverFlow => |
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| 165 | Tick_count<=incr_vec(Tick_Count,en); --compteur de tick |
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| 166 | ClkR_Count<=dcr_vec(Clkr_Count,en); |
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| 167 | OvF_us<=All_ones(Time_Ucount); |
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| 168 | OvF_i<=All_ones(Tick_count); |
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| 169 | end case; |
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| 170 | end process; |
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| 171 | |
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| 172 | NEXT_STATE_DECODE: process (state, Initialized, zero, OvF) |
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| 173 | begin |
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| 174 | --declare default state for next_state to avoid latches |
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| 175 | next_state <= state; --default is to stay in current state |
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| 176 | --insert statements to decode next_state |
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| 177 | --below is a simple example |
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| 178 | case (state) is |
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| 179 | when Init => |
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| 180 | if Initialized = '1' then |
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| 181 | |
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| 182 | next_state <= count; |
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| 183 | end if; |
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| 184 | when Count => |
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| 185 | if Zero = '0' then |
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| 186 | next_state <= Count; |
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| 187 | elsif Zero = '1' then |
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| 188 | next_state <=Usout; |
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| 189 | |
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| 190 | end if; |
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| 191 | when UsOut => |
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| 192 | If OvF='0' then |
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| 193 | next_state <= count; |
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| 194 | elsif OvF='1' then |
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| 195 | next_state <= OverFlow; |
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| 196 | end if; |
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| 197 | When OverFlow => |
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| 198 | next_state<=Count; |
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| 199 | -- when others => |
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| 200 | -- next_state <= Init; |
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| 201 | end case; |
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| 202 | end process; |
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| 203 | |
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| 204 | |
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| 205 | end Behavioral; |
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| 206 | |
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