[100] | 1 | ---------------------------------------------------------------------------------- |
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| 2 | -- Company: |
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| 3 | -- Engineer: |
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| 4 | -- |
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| 5 | -- Create Date: 04:35:05 10/15/2012 |
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| 6 | -- Design Name: |
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| 7 | -- Module Name: FIfo_mem - Behavioral |
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| 8 | -- Project Name: |
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| 9 | -- Target Devices: |
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| 10 | -- Tool versions: |
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| 11 | -- Description: |
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| 12 | -- |
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| 13 | -- Dependencies: |
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| 14 | -- |
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| 15 | -- Revision: |
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| 16 | -- Revision 0.01 - File Created |
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| 17 | -- Additional Comments: |
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| 18 | -- |
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| 19 | ---------------------------------------------------------------------------------- |
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| 20 | |
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| 21 | |
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| 22 | library IEEE; |
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| 23 | use IEEE.std_logic_1164.all; |
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| 24 | use IEEE.std_logic_unsigned.all; |
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| 25 | entity FIFO is |
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| 26 | generic (N: integer := 6; -- number of address bits for 2**N address locations |
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| 27 | M: integer := 8); -- number of data bits to/from FIFO |
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| 28 | port (CLK, PUSH, POP, INIT: in std_logic; |
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| 29 | DIN: in std_logic_vector(N-1 downto 0); |
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| 30 | DOUT: out std_logic_vector(N-1 downto 0); |
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| 31 | FULL, EMPTY, NOPUSH, NOPOP: out std_logic; |
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| 32 | clk: IN std_logic; |
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| 33 | |
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| 34 | rd_en: IN std_logic; |
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| 35 | srst: IN std_logic; |
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| 36 | wr_en: IN std_logic; |
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| 37 | |
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| 38 | empty: OUT std_logic; |
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| 39 | full: OUT std_logic); |
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| 40 | end entity FIFO; |
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| 41 | architecture TOP_HIER of FIFO is |
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| 42 | signal WE: std_logic; |
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| 43 | signal A: std_logic_vector(N-1 downto 0); |
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| 44 | signal PUSH, POP, INIT: std_logic; |
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| 45 | |
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| 46 | signal NOPUSH, NOPOP: std_logic; |
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| 47 | |
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| 48 | component FIFO_LOGIC is |
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| 49 | generic (N: integer); -- number of address bits |
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| 50 | port (CLK, PUSH, POP, INIT: in std_logic; |
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| 51 | ADD: out std_logic_vector(N-1 downto 0); |
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| 52 | FULL, EMPTY, WE, NOPUSH, NOPOP: buffer std_logic); |
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| 53 | end component FIFO_LOGIC; |
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| 54 | |
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| 55 | COMPONENT RAM_256 |
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| 56 | PORT( |
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| 57 | clka : IN std_logic; |
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| 58 | clkb : IN std_logic; |
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| 59 | wea : IN std_logic; |
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| 60 | ena : IN std_logic; |
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| 61 | enb : IN std_logic; |
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| 62 | addra : IN std_logic_vector(Word-1 downto 0); |
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| 63 | addrb : IN std_logic_vector(Word-1 downto 0); |
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| 64 | dia : IN std_logic_vector(Word-1 downto 0); |
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| 65 | dob : OUT std_logic_vector(Word-1 downto 0) |
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| 66 | ); |
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| 67 | END COMPONENT; |
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| 68 | begin |
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| 69 | -- example of component instantiation using positional notation |
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| 70 | FL: FIFO_LOGIC generic map (N) |
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| 71 | port map (CLK, PUSH, POP, INIT, A, FULL, EMPTY, WE, NOPUSH, NOPOP); |
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| 72 | Push<=wr_en; |
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| 73 | pop<=rd_en; |
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| 74 | nopush<=nopush; |
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| 75 | nopop<=nopop; |
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| 76 | init<=srst; |
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| 77 | -- example of component instantiation using keyword notation |
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| 78 | --R: RAM generic map (W => N, K => M) |
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| 79 | -- port map (DIN => DIN, ADDR => A, WR => WE, DOUT => DOUT); |
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| 80 | R: RAM_256 PORT MAP( |
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| 81 | clka => clk, |
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| 82 | clkb => clk, |
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| 83 | wea => we, |
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| 84 | ena => '1', |
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| 85 | enb => '1', |
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| 86 | addra => A, |
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| 87 | addrb => A, |
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| 88 | dia => din, |
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| 89 | dob => dout |
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| 90 | ); |
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| 91 | end architecture TOP_HIER; |
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