[100] | 1 | ---------------------------------------------------------------------------------- |
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| 2 | -- Company: |
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| 3 | -- Engineer: GAMOM NGOUNOU |
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| 4 | -- |
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| 5 | -- Create Date: 18:33:31 03/05/2012 |
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| 6 | -- Design Name: |
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| 7 | -- Module Name: RAM_32_32 - Behavioral |
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| 8 | -- Project Name: MPI_Core |
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| 9 | -- Target Devices: |
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| 10 | -- Tool versions: |
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| 11 | -- Description: permet de stocker les données locales de la librairie MPI |
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| 12 | -- |
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| 13 | -- Dependencies: |
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| 14 | -- |
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| 15 | -- Revision: |
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| 16 | -- Revision 0.01 - File Created |
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| 17 | -- Additional Comments: |
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| 18 | -- |
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| 19 | ---------------------------------------------------------------------------------- |
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| 20 | library IEEE; |
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| 21 | use IEEE.STD_LOGIC_1164.ALL; |
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| 22 | use IEEE.STD_LOGIC_ARITH.ALL; |
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| 23 | use IEEE.STD_LOGIC_UNSIGNED.ALL; |
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| 24 | -- Uncomment the following library declaration if using |
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| 25 | -- arithmetic functions with Signed or Unsigned values |
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| 26 | --use IEEE.NUMERIC_STD.ALL; |
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| 27 | |
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| 28 | -- Uncomment the following library declaration if instantiating |
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| 29 | -- any Xilinx primitives in this code. |
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| 30 | --library UNISIM; |
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| 31 | --use UNISIM.VComponents.all; |
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| 32 | |
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| 33 | entity RAM_v is |
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| 34 | generic(width : positive:=32; Size:positive:=16); |
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| 35 | Port ( clka, clkb : in std_logic; |
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| 36 | reset: in std_logic; |
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| 37 | wea : in std_logic; |
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| 38 | ena, enb : in std_logic; |
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| 39 | addra, addrb : in std_logic_vector(size-1 downto 0); --cinq lignes d'adresse |
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| 40 | dia : in std_logic_vector(width-1 downto 0); |
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| 41 | dob : out std_logic_vector(width-1 downto 0)); |
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| 42 | end RAM_v; |
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| 43 | |
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| 44 | architecture Behavioral of RAM_v is |
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| 45 | attribute RAM_STYLE : string; |
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| 46 | signal Lra,Lrb :std_logic:='0'; |
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| 47 | signal doado,dobdo:std_logic_vector(15 downto 0); |
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| 48 | signal DOPBDOP : std_logic_vector(1 downto 0); |
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| 49 | signal ADDRAWRADDR,ADDRBRDADDR :std_logic_vector(13 downto 0); |
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| 50 | signal REGCEA:std_logic; |
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| 51 | signal DIADI :std_logic_vector(15 downto 0); -- 16-bit input: A port data/LSB data input |
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| 52 | signal DIPADIP :std_logic_vector(1 downto 0); -- 2-bit input: A port parity/LSB parity input |
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| 53 | signal REGCEBREGCE :std_logic ; -- 1-bit input: B port register enable/Register enable input |
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| 54 | signal RSTBRST :std_logic ; -- 1-bit input: B port set/reset input |
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| 55 | signal WEBWEU :std_logic_vector(1 downto 0):=(others=>'0') ; -- 2-bit input: B port write enable input |
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| 56 | -- Port B Data: 16-bit (each) input: Port B data |
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| 57 | signal DIBDI :std_logic_vector(15 downto 0):=(others=>'1'); -- 16-bit input: B port data/MSB data input |
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| 58 | signal DIPBDIP :std_logic_vector(1 downto 0):=(others=>'1'); -- 2-bit input: B port parity/MSB parity input |
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| 59 | signal sel : std_logic_vector(1 downto 0); |
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| 60 | signal doa,dout : std_logic_vector(width-1 downto 0); |
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| 61 | type ram_type is array (2**(size-3)-1 downto 0) of std_logic_vector (width-1 downto 0); |
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| 62 | signal RAM: ram_type; |
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| 63 | attribute RAM_STYLE of RAM: signal is "BLOCK"; |
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| 64 | begin |
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| 65 | -- RAMB8BWER: 8k-bit Data and 1k-bit Parity Configurable Synchronous Block RAM |
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| 66 | -- Spartan-6 |
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| 67 | -- Xilinx HDL Language Template, version 13.3 |
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| 68 | |
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| 69 | RAMB8BWER_inst : RAMB8BWER |
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| 70 | generic map ( |
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| 71 | -- DATA_WIDTH_A/DATA_WIDTH_B: 'If RAM_MODE="TDP": 0, 1, 2, 4, 9 or 18; If RAM_MODE="SDP": 36' |
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| 72 | DATA_WIDTH_A => 9, |
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| 73 | DATA_WIDTH_B => 9, |
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| 74 | -- DOA_REG/DOB_REG: Optional output register (0 or 1) |
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| 75 | DOA_REG => 0, |
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| 76 | DOB_REG => 0, |
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| 77 | -- EN_RSTRAM_A/EN_RSTRAM_B: Enable/disable RST |
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| 78 | EN_RSTRAM_A => TRUE, |
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| 79 | EN_RSTRAM_B => TRUE, |
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| 80 | -- INITP_00 to INITP_03: Initial memory contents. |
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| 81 | INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000", |
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| 82 | INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000", |
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| 83 | INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000", |
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| 84 | INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000", |
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| 85 | -- INIT_00 to INIT_1F: Initial memory contents. |
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| 86 | INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000", |
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| 87 | INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000", |
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| 88 | INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000", |
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| 89 | INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000", |
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| 90 | INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000", |
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| 91 | INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000", |
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| 92 | INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000", |
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| 93 | INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000", |
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| 94 | INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000", |
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| 95 | INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000", |
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| 96 | INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000", |
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| 97 | INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000", |
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| 98 | INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000", |
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| 99 | INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000", |
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| 100 | INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000", |
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| 101 | INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000", |
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| 102 | INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000", |
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| 103 | INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000", |
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| 104 | INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000", |
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| 105 | INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000", |
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| 106 | INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000", |
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| 107 | INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000", |
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| 108 | INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000", |
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| 109 | INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000", |
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| 110 | INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000", |
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| 111 | INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000", |
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| 112 | INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000", |
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| 113 | INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000", |
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| 114 | INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000", |
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| 115 | INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000", |
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| 116 | INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000", |
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| 117 | INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000", |
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| 118 | -- INIT_A/INIT_B: Initial values on output port |
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| 119 | INIT_A => X"00000", |
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| 120 | INIT_B => X"00000", |
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| 121 | -- INIT_FILE: Not Supported |
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| 122 | INIT_FILE => "NONE", -- Do not modify |
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| 123 | -- RAM_MODE: "SDP" or "TDP" |
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| 124 | RAM_MODE => "TDP", |
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| 125 | -- RSTTYPE: "SYNC" or "ASYNC" |
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| 126 | RSTTYPE => "SYNC", |
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| 127 | -- RST_PRIORITY_A/RST_PRIORITY_B: "CE" or "SR" |
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| 128 | RST_PRIORITY_A => "CE", |
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| 129 | RST_PRIORITY_B => "CE", |
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| 130 | -- SIM_COLLISION_CHECK: Collision check enable "ALL", "WARNING_ONLY", "GENERATE_X_ONLY" or "NONE" |
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| 131 | SIM_COLLISION_CHECK => "ALL", |
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| 132 | -- SRVAL_A/SRVAL_B: Set/Reset value for RAM output |
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| 133 | SRVAL_A => X"00000", |
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| 134 | SRVAL_B => X"00000", |
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| 135 | -- WRITE_MODE_A/WRITE_MODE_B: "WRITE_FIRST", "READ_FIRST", or "NO_CHANGE" |
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| 136 | WRITE_MODE_A => "WRITE_FIRST", |
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| 137 | WRITE_MODE_B => "WRITE_FIRST" |
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| 138 | ) |
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| 139 | port map ( |
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| 140 | -- Port A Data: 16-bit (each) output: Port A data |
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| 141 | DOADO => DOADO, -- 16-bit output: A port data/LSB data output |
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| 142 | DOPADOP => DOPADOP, -- 2-bit output: A port parity/LSB parity output |
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| 143 | -- Port B Data: 16-bit (each) output: Port B data |
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| 144 | DOBDO => DOBDO, -- 16-bit output: B port data/MSB data output |
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| 145 | DOPBDOP => DOPBDOP, -- 2-bit output: B port parity/MSB parity output |
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| 146 | -- Port A Address/Control Signals: 13-bit (each) input: Port A address and control signals (write port |
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| 147 | -- when RAM_MODE="SDP") |
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| 148 | ADDRAWRADDR => ADDRAWRADDR, -- 13-bit input: A port address/Write address input |
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| 149 | CLKAWRCLK => CLKA, -- 1-bit input: A port clock/Write clock input |
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| 150 | ENAWREN => ENA, -- 1-bit input: A port enable/Write enable input |
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| 151 | REGCEA => REGCEA, -- 1-bit input: A port register enable input |
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| 152 | RSTA => Reset, -- 1-bit input: A port set/reset input |
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| 153 | WEAWEL => WEA, -- 2-bit input: A port write enable input |
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| 154 | -- Port A Data: 16-bit (each) input: Port A data |
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| 155 | DIADI => DIADI, -- 16-bit input: A port data/LSB data input |
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| 156 | DIPADIP => DIPADIP, -- 2-bit input: A port parity/LSB parity input |
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| 157 | -- Port B Address/Control Signals: 13-bit (each) input: Port B address and control signals (read port |
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| 158 | -- when RAM_MODE="SDP") |
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| 159 | ADDRBRDADDR => ADDRBRDADDR, -- 13-bit input: B port address/Read address input |
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| 160 | CLKBRDCLK => clkb, -- 1-bit input: B port clock/Read clock input |
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| 161 | ENBRDEN => ENB, -- 1-bit input: B port enable/Read enable input |
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| 162 | REGCEBREGCE => REGCEBREGCE, -- 1-bit input: B port register enable/Register enable input |
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| 163 | RSTBRST => reset, -- 1-bit input: B port set/reset input |
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| 164 | WEBWEU => WEBWEU, -- 2-bit input: B port write enable input |
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| 165 | -- Port B Data: 16-bit (each) input: Port B data |
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| 166 | DIBDI => DIBDI, -- 16-bit input: B port data/MSB data input |
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| 167 | DIPBDIP => DIPBDIP -- 2-bit input: B port parity/MSB parity input |
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| 168 | ); |
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| 169 | |
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| 170 | DIADI(width-1 downto 0)<=dia; |
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| 171 | ADDRAWRADDR <=addra(10 downto 0); |
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| 172 | ADDRBRDADDR <=addrb(10 downto 0); |
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| 173 | doa<=DOADO(width-1 downt0 0); |
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| 174 | dout<=DOBDO(width-1 downt0 0); |
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| 175 | process (clka) |
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| 176 | begin |
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| 177 | if clka'event and clka = '1' then |
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| 178 | if ena = '1' then |
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| 179 | if wea = '1' then |
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| 180 | if conv_integer(addra)>8191 then |
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| 181 | report "Erreur d'adresse"; |
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| 182 | else |
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| 183 | --RAM(conv_integer(addra)) <= dia; |
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| 184 | end if; |
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| 185 | end if; |
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| 186 | if conv_integer(addrb)>8191 then |
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| 187 | report "Erreur d'adresse"; |
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| 188 | else |
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| 189 | --doa<=RAM(conv_integer(addrb)); |
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| 190 | end if; |
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| 191 | Lra<='1'; |
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| 192 | else |
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| 193 | if lrb='1' then |
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| 194 | Lra<='0'; |
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| 195 | end if; |
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| 196 | end if; |
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| 197 | end if; |
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| 198 | end process; |
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| 199 | |
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| 200 | |
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| 201 | process (clkb) |
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| 202 | begin |
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| 203 | if clkb'event and clkb = '1' then |
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| 204 | if enb = '1' then |
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| 205 | Lrb<='1'; |
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| 206 | if conv_integer(addrb)>8191 then |
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| 207 | report "Erreur d'adresse"; |
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| 208 | else |
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| 209 | --dout <= RAM(conv_integer(addrb)) ; |
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| 210 | end if; |
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| 211 | else |
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| 212 | if Lra='1' then |
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| 213 | Lrb<='0'; |
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| 214 | end if; |
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| 215 | end if; |
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| 216 | end if; |
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| 217 | end process; |
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| 218 | |
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| 219 | sel<=(Lra,Lrb); |
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| 220 | With sel select |
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| 221 | dob <=dout when "11", |
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| 222 | doa when "10", |
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| 223 | dout when "01", |
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| 224 | dout when "00", |
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| 225 | dout when others; |
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| 226 | |
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| 227 | end Behavioral; |
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| 228 | |
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