source: PROJECT_CORE_MPI/MPI_HCL/TRUNK/CORE_MPI/RAM_block.vhd @ 100

Last change on this file since 100 was 100, checked in by rolagamo, 10 years ago
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1----------------------------------------------------------------------------------
2-- Company:
3-- Engineer:  GAMOM NGOUNOU
4--
5-- Create Date:    18:33:31 03/05/2012
6-- Design Name:
7-- Module Name:    RAM_32_32 - Behavioral
8-- Project Name: MPI_Core
9-- Target Devices:
10-- Tool versions:
11-- Description: permet de stocker les données locales de la librairie MPI
12--
13-- Dependencies:
14--
15-- Revision:
16-- Revision 0.01 - File Created
17-- Additional Comments:
18--
19----------------------------------------------------------------------------------
20library IEEE;
21use IEEE.STD_LOGIC_1164.ALL;
22use IEEE.STD_LOGIC_ARITH.ALL;
23use IEEE.STD_LOGIC_UNSIGNED.ALL;
24-- Uncomment the following library declaration if using
25-- arithmetic functions with Signed or Unsigned values
26--use IEEE.NUMERIC_STD.ALL;
27
28-- Uncomment the following library declaration if instantiating
29-- any Xilinx primitives in this code.
30--library UNISIM;
31--use UNISIM.VComponents.all;
32
33entity RAM_v is
34generic(width : positive:=32; Size:positive:=16);
35Port ( clka, clkb : in std_logic;
36                                reset: in std_logic;
37                          wea : in std_logic;
38                          ena, enb : in std_logic;
39                          addra, addrb : in std_logic_vector(size-1 downto 0); --cinq lignes d'adresse
40                          dia : in std_logic_vector(width-1 downto 0);
41                          dob : out std_logic_vector(width-1 downto 0));
42end RAM_v;
43
44architecture Behavioral of RAM_v is
45        attribute RAM_STYLE : string;
46        signal Lra,Lrb :std_logic:='0';
47        signal doado,dobdo:std_logic_vector(15 downto 0);
48        signal DOPBDOP : std_logic_vector(1 downto 0);
49        signal ADDRAWRADDR,ADDRBRDADDR :std_logic_vector(13 downto 0);
50        signal REGCEA:std_logic;
51        signal  DIADI :std_logic_vector(15 downto 0);  -- 16-bit input: A port data/LSB data input
52   signal  DIPADIP :std_logic_vector(1 downto 0);  -- 2-bit input: A port parity/LSB parity input
53        signal REGCEBREGCE :std_logic ; -- 1-bit input: B port register enable/Register enable input
54   signal  RSTBRST :std_logic ;         -- 1-bit input: B port set/reset input
55   signal  WEBWEU :std_logic_vector(1 downto 0):=(others=>'0') ;          -- 2-bit input: B port write enable input
56      -- Port B Data: 16-bit (each) input: Port B data
57   signal   DIBDI :std_logic_vector(15 downto 0):=(others=>'1');             -- 16-bit input: B port data/MSB data input
58   signal    DIPBDIP :std_logic_vector(1 downto 0):=(others=>'1');         -- 2-bit input: B port parity/MSB parity input
59        signal sel : std_logic_vector(1 downto 0);
60        signal doa,dout : std_logic_vector(width-1 downto 0);
61        type ram_type is array (2**(size-3)-1 downto 0) of std_logic_vector (width-1 downto 0);
62        signal RAM: ram_type;
63        attribute RAM_STYLE of RAM: signal is "BLOCK";
64begin
65 -- RAMB8BWER: 8k-bit Data and 1k-bit Parity Configurable Synchronous Block RAM
66   --            Spartan-6
67   -- Xilinx HDL Language Template, version 13.3
68
69   RAMB8BWER_inst : RAMB8BWER
70   generic map (
71      -- DATA_WIDTH_A/DATA_WIDTH_B: 'If RAM_MODE="TDP": 0, 1, 2, 4, 9 or 18; If RAM_MODE="SDP": 36'
72      DATA_WIDTH_A => 9,
73      DATA_WIDTH_B => 9,
74      -- DOA_REG/DOB_REG: Optional output register (0 or 1)
75      DOA_REG => 0,
76      DOB_REG => 0,
77      -- EN_RSTRAM_A/EN_RSTRAM_B: Enable/disable RST
78      EN_RSTRAM_A => TRUE,
79      EN_RSTRAM_B => TRUE,
80      -- INITP_00 to INITP_03: Initial memory contents.
81      INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
82      INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
83      INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
84      INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
85      -- INIT_00 to INIT_1F: Initial memory contents.
86      INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
87      INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
88      INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
89      INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
90      INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
91      INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
92      INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
93      INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
94      INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
95      INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
96      INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
97      INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
98      INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
99      INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
100      INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
101      INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
102      INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
103      INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
104      INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
105      INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
106      INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
107      INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
108      INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
109      INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
110      INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
111      INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
112      INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
113      INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
114      INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
115      INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
116      INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
117      INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
118      -- INIT_A/INIT_B: Initial values on output port
119      INIT_A => X"00000",
120      INIT_B => X"00000",
121      -- INIT_FILE: Not Supported
122      INIT_FILE => "NONE",                                                             -- Do not modify
123      -- RAM_MODE: "SDP" or "TDP"
124      RAM_MODE => "TDP",
125      -- RSTTYPE: "SYNC" or "ASYNC"
126      RSTTYPE => "SYNC",
127      -- RST_PRIORITY_A/RST_PRIORITY_B: "CE" or "SR"
128      RST_PRIORITY_A => "CE",
129      RST_PRIORITY_B => "CE",
130      -- SIM_COLLISION_CHECK: Collision check enable "ALL", "WARNING_ONLY", "GENERATE_X_ONLY" or "NONE"
131      SIM_COLLISION_CHECK => "ALL",
132      -- SRVAL_A/SRVAL_B: Set/Reset value for RAM output
133      SRVAL_A => X"00000",
134      SRVAL_B => X"00000",
135      -- WRITE_MODE_A/WRITE_MODE_B: "WRITE_FIRST", "READ_FIRST", or "NO_CHANGE"
136      WRITE_MODE_A => "WRITE_FIRST",
137      WRITE_MODE_B => "WRITE_FIRST" 
138   )
139   port map (
140      -- Port A Data: 16-bit (each) output: Port A data
141      DOADO => DOADO,             -- 16-bit output: A port data/LSB data output
142      DOPADOP => DOPADOP,         -- 2-bit output: A port parity/LSB parity output
143      -- Port B Data: 16-bit (each) output: Port B data
144      DOBDO => DOBDO,             -- 16-bit output: B port data/MSB data output
145      DOPBDOP => DOPBDOP,         -- 2-bit output: B port parity/MSB parity output
146      -- Port A Address/Control Signals: 13-bit (each) input: Port A address and control signals (write port
147      -- when RAM_MODE="SDP")
148      ADDRAWRADDR => ADDRAWRADDR, -- 13-bit input: A port address/Write address input
149      CLKAWRCLK => CLKA,     -- 1-bit input: A port clock/Write clock input
150      ENAWREN => ENA,         -- 1-bit input: A port enable/Write enable input
151      REGCEA => REGCEA,           -- 1-bit input: A port register enable input
152      RSTA => Reset,               -- 1-bit input: A port set/reset input
153      WEAWEL => WEA,           -- 2-bit input: A port write enable input
154      -- Port A Data: 16-bit (each) input: Port A data
155      DIADI => DIADI,             -- 16-bit input: A port data/LSB data input
156      DIPADIP => DIPADIP,         -- 2-bit input: A port parity/LSB parity input
157      -- Port B Address/Control Signals: 13-bit (each) input: Port B address and control signals (read port
158      -- when RAM_MODE="SDP")
159      ADDRBRDADDR => ADDRBRDADDR, -- 13-bit input: B port address/Read address input
160      CLKBRDCLK => clkb,     -- 1-bit input: B port clock/Read clock input
161      ENBRDEN => ENB,         -- 1-bit input: B port enable/Read enable input
162      REGCEBREGCE => REGCEBREGCE, -- 1-bit input: B port register enable/Register enable input
163      RSTBRST => reset,         -- 1-bit input: B port set/reset input
164      WEBWEU => WEBWEU,           -- 2-bit input: B port write enable input
165      -- Port B Data: 16-bit (each) input: Port B data
166      DIBDI => DIBDI,             -- 16-bit input: B port data/MSB data input
167      DIPBDIP => DIPBDIP          -- 2-bit input: B port parity/MSB parity input
168   );
169 
170 DIADI(width-1 downto 0)<=dia;
171 ADDRAWRADDR <=addra(10 downto 0);
172 ADDRBRDADDR <=addrb(10 downto 0);
173 doa<=DOADO(width-1 downt0 0);
174 dout<=DOBDO(width-1 downt0 0);
175 process (clka)
176        begin
177                if clka'event and clka = '1' then
178                        if ena = '1' then
179                                if wea = '1' then
180                                  if conv_integer(addra)>8191 then
181                                      report  "Erreur d'adresse";
182                                  else
183                                                --RAM(conv_integer(addra)) <= dia;
184                                        end if;
185                                end if;
186                                if conv_integer(addrb)>8191 then
187                                      report  "Erreur d'adresse";
188                                  else 
189                                --doa<=RAM(conv_integer(addrb));
190                           end if;
191                                Lra<='1';
192                        else 
193                                if lrb='1' then
194                                                Lra<='0';
195                                end if;
196                        end if;
197                 end if;
198 end process;
199
200 
201 process (clkb) 
202 begin
203                if clkb'event and clkb = '1' then
204                        if enb = '1' then
205                                Lrb<='1';       
206                                if conv_integer(addrb)>8191 then
207                                      report  "Erreur d'adresse";
208                                  else 
209                                  --dout <= RAM(conv_integer(addrb)) ;
210                                end if;
211                        else
212                                if Lra='1' then
213                                        Lrb<='0';
214                                end if;
215                        end if;
216                end if;
217 end process;
218 
219 sel<=(Lra,Lrb);
220 With  sel select
221 dob <=dout when "11",
222      doa  when "10",
223                dout when "01",
224                dout when "00",
225                dout when others;
226               
227end Behavioral;
228
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