[100] | 1 | ---------------------------------------------------------------------------------- |
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| 2 | -- Company: |
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| 3 | -- Engineer: |
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| 4 | -- |
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| 5 | -- Create Date: 20:30:11 08/01/2013 |
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| 6 | -- Design Name: |
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| 7 | -- Module Name: SetBit - Behavioral |
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| 8 | -- Project Name: |
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| 9 | -- Target Devices: |
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| 10 | -- Tool versions: |
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| 11 | -- Description: |
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| 12 | -- |
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| 13 | -- Dependencies: |
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| 14 | -- |
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| 15 | -- Revision: |
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| 16 | -- Revision 0.01 - File Created |
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| 17 | -- Additional Comments: |
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| 18 | -- |
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| 19 | ---------------------------------------------------------------------------------- |
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| 20 | library IEEE; |
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| 21 | use IEEE.STD_LOGIC_1164.ALL; |
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| 22 | Library NocLib; |
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| 23 | use NoCLib.CoreTypes.all; |
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| 24 | --use work.packet_type.all; |
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| 25 | -- Uncomment the following library declaration if using |
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| 26 | -- arithmetic functions with Signed or Unsigned values |
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| 27 | --use IEEE.NUMERIC_STD.ALL; |
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| 28 | |
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| 29 | -- Uncomment the following library declaration if instantiating |
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| 30 | -- any Xilinx primitives in this code. |
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| 31 | --library UNISIM; |
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| 32 | --use UNISIM.VComponents.all; |
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| 33 | |
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| 34 | entity SetBit is |
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| 35 | Port ( clk : in STD_LOGIC; |
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| 36 | reset : in STD_LOGIC; |
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| 37 | BitMask : in std_logic_vector(Word-1 downto 0); |
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| 38 | BitVal : in std_logic; |
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| 39 | whole : in std_logic; |
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| 40 | dma_wr_grant : in STD_LOGIC; |
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| 41 | dma_wr_request : out STD_LOGIC; |
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| 42 | dma_rd_grant : in STD_LOGIC; |
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| 43 | dma_rd_request : out STD_LOGIC; |
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| 44 | ram_rd : out std_logic; |
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| 45 | ram_wr : out std_logic; |
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| 46 | start : in std_logic; |
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| 47 | done : out std_logic; |
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| 48 | ram_address : in std_logic_vector(ADRLEN-1 downto 0);--accès au stockage |
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| 49 | Ram_data_in : out STD_LOGIC_VECTOR (Word-1 downto 0); |
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| 50 | Ram_data_out : in STD_LOGIC_VECTOR (Word-1 downto 0)); |
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| 51 | end SetBit; |
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| 52 | |
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| 53 | architecture Behavioral of SetBit is |
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| 54 | signal State,Next_State:natural range 0 to 15 :=0; |
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| 55 | signal dma_rd,dma_wr,rd_ok ,wr_ok:std_logic:='0'; |
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| 56 | signal tempval,tempval_i : std_logic_vector(Word-1 downto 0):=(others=>'1'); |
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| 57 | begin |
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| 58 | PSetBit_sync:process(clk,reset) |
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| 59 | |
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| 60 | begin |
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| 61 | if rising_edge(clk) then |
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| 62 | if reset='1' then |
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| 63 | State<=0; |
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| 64 | Tempval<=(others=>'0'); |
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| 65 | else |
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| 66 | State<=Next_State; |
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| 67 | Tempval<=tempval_i; |
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| 68 | end if; |
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| 69 | end if; |
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| 70 | end process; |
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| 71 | |
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| 72 | PSetBit:process (State,tempval,Start,whole,BitMask,BitVal,Dma_rd_grant,Dma_wr_grant,ram_data_out) |
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| 73 | begin |
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| 74 | Next_State<=State; |
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| 75 | |
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| 76 | tempval_i<=tempval; |
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| 77 | wr_ok<='0'; |
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| 78 | rd_ok<='0'; |
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| 79 | if State >0 then |
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| 80 | |
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| 81 | dma_wr<='1'; --demander un accès exclusif au bus |
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| 82 | dma_rd<='1'; -- pour éviter une mauvaise mise à jour des données |
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| 83 | else |
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| 84 | dma_wr<='0'; |
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| 85 | dma_rd<='0'; |
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| 86 | end if; |
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| 87 | case State is |
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| 88 | when 0 =>Ram_data_in<=tempval; |
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| 89 | rd_ok<='0'; |
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| 90 | Wr_ok<='0'; |
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| 91 | done<='0'; |
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| 92 | if start='1' and whole='1' then |
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| 93 | Next_State<=5; |
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| 94 | wr_ok<='1'; |
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| 95 | ram_data_in<=bitmask; |
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| 96 | elsif start='1' then |
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| 97 | Next_State<=State+1; |
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| 98 | end if; |
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| 99 | |
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| 100 | when 1=> Ram_data_in<=tempval; |
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| 101 | if dma_rd_grant='1' then |
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| 102 | Next_State<=State+1; |
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| 103 | |
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| 104 | end if; |
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| 105 | rd_ok<='1'; |
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| 106 | wr_ok<='0'; |
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| 107 | done<='0'; |
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| 108 | When 2|3=>Ram_data_in<=Ram_data_out; |
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| 109 | if dma_rd_grant='1' then --cycle d'attente |
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| 110 | Next_State<=State+1; |
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| 111 | else |
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| 112 | Next_State<=1; --recommencer l'attente si perte de priorité |
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| 113 | end if; |
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| 114 | rd_ok<='1'; |
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| 115 | wr_ok<='0'; |
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| 116 | done<='0'; |
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| 117 | When 4 => |
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| 118 | Ram_data_in<=ram_data_out; |
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| 119 | done<='0'; |
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| 120 | rd_ok<='1'; |
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| 121 | if dma_rd_grant='1' and dma_wr_grant='1' then |
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| 122 | Next_State<=5; |
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| 123 | --tempval<=Ram_data_out; |
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| 124 | -- if bitval='1' then |
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| 125 | -- tempval<= Ram_data_out or BitMask; |
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| 126 | -- else |
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| 127 | -- tempval<= Ram_data_out and not (BitMask); |
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| 128 | -- end if; |
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| 129 | if whole='1' then |
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| 130 | --ram_data_in<=bitmask; |
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| 131 | tempval_i<= BitMask; |
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| 132 | else |
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| 133 | if bitval='1' then |
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| 134 | --ram_data_in<=Ram_data_out or BitMask; |
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| 135 | tempval_i<= Ram_data_out or BitMask; |
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| 136 | else |
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| 137 | --Ram_data_in<=Ram_data_out and not (BitMask); |
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| 138 | tempval_i<= Ram_data_out and not (BitMask); |
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| 139 | end if; |
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| 140 | end if; |
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| 141 | rd_ok<='1'; |
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| 142 | wr_ok<='1'; |
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| 143 | else |
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| 144 | Next_State<=State; |
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| 145 | report "SetBit:Impossible d'avoir accès en R/W à la RAM"; |
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| 146 | end if; |
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| 147 | When 5 |6 => |
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| 148 | Ram_data_in<=tempval; |
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| 149 | if dma_wr_grant='1' then |
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| 150 | if whole='1' then |
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| 151 | ram_data_in<=bitmask; |
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| 152 | else |
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| 153 | ram_data_in<=tempval; |
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| 154 | end if; |
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| 155 | Next_State<=State+1; |
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| 156 | else |
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| 157 | Next_state<=5; |
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| 158 | end if; |
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| 159 | wr_ok<='1'; |
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| 160 | rd_ok<='1'; |
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| 161 | done<='0'; |
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| 162 | When 7=> |
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| 163 | done<='1'; |
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| 164 | if start='0' then |
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| 165 | Next_State<=0; |
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| 166 | wr_ok<='0'; |
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| 167 | end if; |
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| 168 | rd_ok<='0'; |
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| 169 | wr_ok<='0'; |
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| 170 | Ram_data_in<=tempval; |
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| 171 | When others => |
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| 172 | Next_State<=0; |
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| 173 | rd_ok<='0'; |
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| 174 | wr_ok<='0'; |
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| 175 | done<='0'; |
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| 176 | Ram_data_in<=tempval; |
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| 177 | end case; |
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| 178 | |
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| 179 | end process PSetBit; |
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| 180 | dma_rd_request <= dma_rd; |
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| 181 | dma_wr_request <=dma_wr; |
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| 182 | Ram_wr<=wr_ok; |
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| 183 | Ram_rd<=rd_ok; |
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| 184 | --Ram_data_out<=data_to_ram; |
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| 185 | |
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| 186 | end Behavioral; |
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| 187 | |
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