[100] | 1 | -- TestBench Template |
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| 2 | -- ce module permet de tester le FIFO et de valider son fonctionnement. |
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| 3 | LIBRARY ieee; |
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| 4 | USE ieee.std_logic_1164.ALL; |
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| 5 | USE ieee.numeric_std.ALL; |
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| 6 | Library NocLib ; |
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| 7 | use NocLib.CoreTypes.all; |
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| 8 | ENTITY testbench IS |
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| 9 | END testbench; |
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| 10 | |
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| 11 | ARCHITECTURE behavior OF testbench IS |
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| 12 | constant clk_period : time := 10 ns; |
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| 13 | constant MSIZE :natural :=256; |
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| 14 | signal clk : std_logic := '0'; |
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| 15 | signal reset : std_logic := '0'; |
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| 16 | -- Component Declaration |
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| 17 | |
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| 18 | component FIFO_256_FWFT --Le FIFO à tester |
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| 19 | port ( |
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| 20 | clk: IN std_logic; |
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| 21 | din: IN std_logic_VECTOR(7 downto 0); |
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| 22 | rd_en: IN std_logic; |
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| 23 | srst: IN std_logic; |
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| 24 | wr_en: IN std_logic; |
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| 25 | dout: OUT std_logic_VECTOR(7 downto 0); |
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| 26 | empty: OUT std_logic; |
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| 27 | full: OUT std_logic); |
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| 28 | end component; |
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| 29 | component proto_receiv -- permet de tester la lecture dans le FIFO |
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| 30 | generic (sizemem : natural := 64); |
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| 31 | port ( |
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| 32 | clk,reset : in std_logic; |
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| 33 | fifo_empty,fifo_full : in std_logic; |
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| 34 | pop : out std_logic:='0'; |
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| 35 | fifo_out : in std_logic_vector(Word-1 downto 0); |
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| 36 | rcv_start : in std_logic; --début de la réception |
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| 37 | rcv_ack :in std_logic; -- acquittement de la réception |
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| 38 | rcv_comp : out std_logic; -- fin de la réception |
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| 39 | mem :out memory(0 to sizemem-1)); |
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| 40 | end component; |
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| 41 | |
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| 42 | component proto_send |
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| 43 | generic (sizemem : natural := 64); |
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| 44 | port ( |
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| 45 | clk,reset : in std_logic; |
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| 46 | fifo_empty,fifo_full : in std_logic; |
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| 47 | push : out std_logic:='0'; |
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| 48 | fifo_in : out std_logic_vector(Word-1 downto 0); |
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| 49 | snd_start : in std_logic; --début de l'emission |
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| 50 | snd_ack :in std_logic; -- acquittement de l'émission |
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| 51 | snd_comp : out std_logic; -- fin de l'émission |
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| 52 | mem :in memory(0 to sizemem-1)); |
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| 53 | |
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| 54 | end component; |
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| 55 | |
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| 56 | type typ_snd_rec is ( fillmem,send1, send2, recv1,recv2); |
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| 57 | type typ_receiv is (r_wait,r_head,r_dlen,r_glen,r_start,r_end); |
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| 58 | signal storage1,storage2 : memory (0 to MSIZE-1); |
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| 59 | SIGNAL fifo_empty,fifo_full : std_logic:='0'; |
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| 60 | signal push,pop ,spush,spop: std_logic:='0'; |
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| 61 | SIGNAL data_in,data_out: std_logic_vector(7 downto 0); |
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| 62 | signal ROn,Rdone,RAck:std_logic:='0'; |
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| 63 | signal SOn,Sdone,SAck:std_logic:='0'; |
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| 64 | signal etreceiv :typ_receiv; |
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| 65 | |
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| 66 | signal pipo : typ_snd_rec; |
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| 67 | |
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| 68 | BEGIN |
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| 69 | |
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| 70 | |
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| 71 | |
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| 72 | uut : FIFO_256_FWFT |
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| 73 | port map ( |
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| 74 | clk => clk, |
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| 75 | din => data_in, |
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| 76 | rd_en => pop, |
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| 77 | srst => reset, |
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| 78 | wr_en => push, |
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| 79 | dout => data_out, |
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| 80 | empty => fifo_empty, |
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| 81 | full => fifo_full); |
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| 82 | |
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| 83 | rec_pro: proto_receiv generic map(sizemem =>MSIZE) |
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| 84 | port map (clk=>clk, |
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| 85 | reset=>reset, |
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| 86 | fifo_empty=>fifo_empty, |
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| 87 | fifo_full=>fifo_full, |
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| 88 | rcv_start =>Ron, |
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| 89 | rcv_ack => Rack, |
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| 90 | rcv_comp=> Rdone, |
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| 91 | pop=>pop, |
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| 92 | fifo_out =>data_out, |
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| 93 | mem=>storage2 |
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| 94 | ); |
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| 95 | snd_pro: proto_send generic map (sizemem =>MSIZE) |
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| 96 | port map (clk=>clk, |
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| 97 | reset=>reset, |
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| 98 | fifo_empty=>fifo_empty, |
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| 99 | fifo_full=>fifo_full, |
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| 100 | snd_start =>Son, |
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| 101 | snd_ack => Sack, |
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| 102 | snd_comp=> Sdone, |
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| 103 | push=>push, |
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| 104 | fifo_in =>data_in, |
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| 105 | mem=>storage1 |
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| 106 | ); |
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| 107 | clk_process :process |
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| 108 | begin |
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| 109 | clk <= '0'; |
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| 110 | wait for clk_period/2; |
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| 111 | clk <= '1'; |
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| 112 | wait for clk_period/2; |
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| 113 | |
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| 114 | end process; |
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| 115 | reset_proc: process |
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| 116 | begin |
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| 117 | -- hold reset state for 100 ns. |
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| 118 | reset<='0'; |
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| 119 | wait for 1 ns; |
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| 120 | reset<='1'; |
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| 121 | wait for clk_period*10; |
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| 122 | reset<='0'; |
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| 123 | wait; |
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| 124 | -- insert stimulus here |
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| 125 | end process; |
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| 126 | pr_pingpong : process(clk,reset) |
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| 127 | variable i: natural range 0 to MSIZE-1; |
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| 128 | begin |
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| 129 | if reset='1' then |
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| 130 | pipo<=fillmem; |
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| 131 | i:=0; |
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| 132 | else |
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| 133 | if rising_edge(clk) then |
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| 134 | case pipo is |
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| 135 | when fillmem => -- remplissage de la mémoire d'envoie |
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| 136 | if i=0 then |
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| 137 | storage1(0)<=x"51"; -- le code de la fonction |
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| 138 | elsif i=1 then |
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| 139 | storage1(1)<=x"05"; -- le nombre d'octets à envoyer dans le tampon. |
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| 140 | elsif (i>=2) and (i<= MSIZE-2) then |
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| 141 | storage1(i)<=std_logic_vector(to_unsigned(i-2,Word)); |
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| 142 | |
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| 143 | else |
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| 144 | pipo<=send1; |
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| 145 | i:=0; |
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| 146 | end if; |
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| 147 | i:=i+1; |
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| 148 | when send1 => |
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| 149 | |
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| 150 | Son<='1'; --activer l'emission des données |
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| 151 | Sack<='0'; |
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| 152 | if i=2 then --activer la réception des données |
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| 153 | Ron<='1'; |
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| 154 | else |
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| 155 | Ron<='0'; |
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| 156 | i:=i+1; |
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| 157 | end if; |
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| 158 | if sdone='1' then |
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| 159 | pipo<=send2; |
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| 160 | |
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| 161 | end if; |
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| 162 | when send2 => |
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| 163 | i:=0; |
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| 164 | Son<='0'; |
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| 165 | Sack<='1'; |
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| 166 | pipo<=recv1; |
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| 167 | when recv1 => |
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| 168 | ron<='1'; |
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| 169 | rack<='0'; |
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| 170 | if Rdone='1' then |
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| 171 | pipo<=recv2; |
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| 172 | end if; |
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| 173 | when recv2 => |
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| 174 | Ron<='0'; |
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| 175 | Rack<='1'; |
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| 176 | pipo<=send1; |
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| 177 | i:=0; |
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| 178 | end case; |
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| 179 | |
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| 180 | |
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| 181 | end if; |
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| 182 | end if; |
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| 183 | end process; |
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| 184 | |
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| 185 | END; |
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