Context Navigation

HT_process.vhd

Last change on this file was 103, checked in by rolagamo, 11 years ago

File size: 17.4 KB

Line
1	----------------------------------------------------------------------------------
2	-- Company:
3	-- Engineer:
4	--
5	-- Create Date: 12:04:21 04/22/2013
6	-- Design Name:
7	-- Module Name: HT_process - Behavioral
8	-- Project Name:
9	-- Target Devices:
10	-- Tool versions:
11	-- Description:
12	--
13	-- Dependencies:
14	--
15	-- Revision:
16	-- Revision 0.01 - File Created
17	-- Additional Comments:
18	--
19	----------------------------------------------------------------------------------
20	library IEEE;
21	use IEEE.STD_LOGIC_1164.ALL;
22	USE ieee.numeric_std.ALL;
23	library NocLib ;
24
25	use std.textio.all;
26	use NocLib.CoreTypes.all;
27	Library MPI_HCL;
28	use MPI_HCL.Packet_type.all;
29	use MPI_HCL.MPI_RMA.all;
30	-- Uncomment the following library declaration if using
31	-- arithmetic functions with Signed or Unsigned values
32	--use IEEE.NUMERIC_STD.ALL;
33
34	-- Uncomment the following library declaration if instantiating
35	-- any Xilinx primitives in this code.
36	--library UNISIM;
37	--use UNISIM.VComponents.all;
38
39	entity HT_process is
40	generic (Task_id : natural:=0);
41	Port ( clk : in STD_LOGIC;
42	reset : in STD_LOGIC;
43	en : in std_logic; -- active la tâche
44	Interf_i : in core_i; --signaux pour l'interface IO
45	Interf_o : out core_o; --signaux pour l'interface IO
46	mem_o : out typ_dpram_o; -- signaux pour l'accès à la mémoire
47	mem_i : in typ_dpram_i -- signaux pour l'accès à la mémoire
48	);
49	end HT_process;
50
51	architecture Behavioral of HT_process is
52	constant simres : time :=1 ps; --simulation resolution
53	constant realres : real :=1.0e-3; --ramener le temps en ns
54
55	type typ_mae is (start,Fillmem,NextFill,InitApp,GetRank,WInCreate,WinPost,WinStart,
56	putdata,getdata,WinWait,WinCompleted,MpiSpawn,finalize,st_timeout);
57	signal sram : typ_dpram;
58	signal MyGroup:mpi_group;
59	signal MyWin : mpi_win;
60	signal MyRank :std_logic_vector(3 downto 0);
61	signal intercomm,array_of_errcodes : natural;
62	signal ct_state:natural:=0;
63	signal Libr : Core_io; --regroupe tous les signaux IO de la bibliothèque
64	signal RunState : typ_mae;
65	signal load : std_logic;
66	signal start1 : std_logic;
67	signal loadval : std_logic_vector(31 downto 0);
68	signal outval : std_logic_vector(31 downto 0);
69	signal zero : std_logic;
70	COMPONENT IP_Timer
71	PORT(
72	clk : IN std_logic;
73	reset : IN std_logic;
74	upDn : IN std_logic;
75	load : IN std_logic;
76	start : IN std_logic;
77	loadval : IN std_logic_vector(31 downto 0);
78	outval : OUT std_logic_vector(31 downto 0);
79	zero : OUT std_logic
80	);
81	END COMPONENT;
82	begin
83	Inst_IP_Timer: IP_Timer PORT MAP(
84	clk =>clk ,
85	reset => reset,
86	upDn => '0',
87	load => load,
88	start => start1,
89	loadval => loadval,
90	outval => outval,
91	zero => zero
92	);
93
94	--MAE du PE
95	--=======================================================================
96	-- Interf<=Libr;
97
98
99	pPutGet:process(clk,reset,en)
100
101	constant DATAPTR : natural :=256;
102	variable nb_rma:natural range 0 to 15:=0;
103	variable bfill,destrank,pid,mport : natural range 0 to 15;
104	variable fsrc,ret : natural range 0 to 15:=0;
105	variable timeout,ct,dlen,dcount : natural range 0 to 511;
106	variable adrToset,SrcAdr,DestAdr : std_logic_vector(ADRLEN-1 downto 0);
107	variable mywin : Mpi_win;
108	variable command , argv , maxprocs , info , root : natural:=0; --variable pour le spawn
109	variable comm : natural :=0;
110	variable iack,spawn : std_logic:='0';
111	variable adresse,adresse_rd :natural range 0 to 65536;
112	variable status_reg,config_reg :std_logic_vector(Word-1 downto 0):=(others=>'0');
113
114	--=======================================================
115	--variables pour la création du fichier de résultats
116	-- synthesis translate_off
117	type char_file is file of character;
118	file f: text;
119	variable status :file_open_status ;
120	variable char_count: integer range 0 to 65536 := 0;
121	variable str: string (1 to 79) ;
122	variable L: line;
123	variable fopened: std_logic:='0';
124
125	-- constant simres : time :=1 ps; --simulation resolution
126	-- constant realres : real :=1.0e-3; --ramener le temps en ns
127	-- returns real value of time parameter using pure VHDL
128	function rt(t : time) return real is
129	begin
130	--if (simres=0) then
131	return real(t/1 ns) * realres;
132	-- else
133	-- return 0.0;
134	-- end if;
135	end;
136	-- synthesis translate_on
137	--======================================================
138	begin
139	--=== Partie combinatoire du process ===================================
140
141	--=== Fin de la partie combinatoire du process ==========================
142
143
144
145	--end loop;
146
147	if (clk'event and clk='1') and en='1' then
148
149
150	if reset='1' then
151	RunState<=start;
152
153	else
154	--==========================================================
155	--affectation des entrées sorties mémoires
156	sram.i.data_out<=mem_I.data_out;
157	mem_o.addr_wr<=sram.O.addr_wr;
158	mem_o.addr_rd<=sram.O.addr_rd ;
159	mem_o.we<=sram.O.we;
160	mem_o.ena<=sram.O.ena;
161	mem_o.enb<=sram.O.enb;
162	mem_o.data_in<=sram.O.data_in;
163	--affectation des entrées sorties MPI_HCL
164	Interf_o.Instr_EN<=Libr.O.instr_en;
165	Interf_o.Membusy<=Libr.O.MemBusy;
166	Interf_o.Instruction<=Libr.O.Instruction;
167	Libr.i.Instr_ack<=Interf_i.Instr_ack;
168	Libr.i.InitOk<=Interf_i.InitOk;
169	Libr.i.Hold_Req<=Interf_i.Hold_req;
170	Libr.I.Spawned<=Interf_i.Spawned;
171	--Libr.i.Hold_Ack<=Interf_i.Hold_Ack;
172	Libr.i.RamSel<=Interf_i.RamSel;
173	--ct_state<=ct; --pour débogage
174	--============================================================
175
176	case RunState is
177	when start =>
178	--Dcount<=0;
179	if bfill=0 then -- si le nombre de bloc de mémoire remplis est vide
180	--RunState<=InitApp;
181	runstate<=fillmem;
182	end if;
183	--Ram_busy<='0';
184	Libr.O.MemBusy<='0';
185	Libr.O.Instr_En<='0';
186	iack:='0';
187	adresse:=10;--DATAPTR;
188
189	adresse_rd:=0;
190	timeout:=0;
191	--dcount<=0;
192	sram.O.we<='0';
193	sram.O.ena<='0';
194	sram.O.enb<='0';
195	-- synthesis translate_off
196	if fopened='0' then
197	file_open(status,f, integer'image(Task_Id) & "test_file0.txt", APPEND_MODE);
198	--while not endfile(c_file_handle) loop
199	--end if;
200
201	--write (l,string'("Ce fichier contient des resultats de la simulation ; ;" & " started at time ; " & time'image(now)));
202	--report l.all;
203	-- writeline (f, l) ;
204	fopened:='1';
205	end if;
206	-- synthesis translate_on
207	when Fillmem =>
208	sram.O.we<='1';
209	sram.O.ena<='1';
210	sram.O.enb<='1';
211	if Libr.I.Ramsel='0' then
212	sram.O.addr_rd<=std_logic_vector(to_unsigned(adresse,ADRLEN));
213	sram.O.addr_wr<=std_logic_vector(to_unsigned(adresse,ADRLEN));
214	sram.O.data_in<=std_logic_vector(to_unsigned(dcount,8)); -- x"0f";
215	Libr.O.Instr_En<='0';
216	dcount:=dcount+1;
217	timeout:=0;
218	if dcount=250 then
219	bfill:=bfill+1;
220
221	if bfill=4 then
222	--RunState<=WinCreate;
223	Runstate<=InitApp;
224	else
225	RunState<=nextfill;
226	end if;
227	else
228	adresse:=adresse+1;
229	sram.O.addr_wr<=std_logic_vector(to_unsigned(adresse,ADRLEN));
230	RunState<=Fillmem;
231	end if;
232	else -- attente de la libéraion de la mémoire
233	timeout:=timeout+1;
234	if timeout=500 then
235	RunState<=st_timeout;
236	end if;
237
238	end if;
239	when nextfill => --prépare le prochain bloc mémoire qui sera rempli
240	adresse:=250*bfill+10;
241
242	dcount:=0;
243	ct:=0;
244	RunState<=Fillmem;
245	Libr.O.Instr_En<='0';
246	sram.O.we<='1';
247	sram.O.ena<='1';
248	sram.O.enb<='0';
249	when InitApp =>
250	--code pour Init
251	dlen:=248;
252	if ct=0 then
253	-- synthesis translate_off
254	write (l,string'("Dlen; ;INIT1 " & integer'image(Dlen)& "; " & image(MyRank) & "; started at ; " & real'image(rt(now))));
255
256	report l.all;
257	writeline (f, l) ;
258	-- synthesis translate_on
259	end if;
260	pMPI_Init(ct,Libr,Clk,SRam);
261
262	adresse:=to_integer(unsigned(sram.O.addr_wr));
263	adresse_rd:=to_integer(unsigned(sram.O.addr_rd));
264
265	--if Libr.InitOk='1' then
266	if ct=0 then
267	RunState<=GetRank;
268	-- synthesis translate_off
269	write (l,string'("Dlen;" & integer'image(Dlen) & ";INIT2 " & integer'image(Dlen) & ";" & image(MyRank) & "; ended at ; " & real'image(rt(now))));
270	report l.all;
271	writeline (f, l) ;
272	-- synthesis translate_on
273	end if;
274
275
276
277	when GetRank =>
278	if ct=0 then
279	-- synthesis translate_off
280	write (l,string'("Dlen;" & integer'image(Dlen)& ";Rank1 " & integer'image(Dlen) & "; ; started ; " & real'image(rt(now))));
281	report l.all;
282	writeline (f, l) ;
283	-- synthesis translate_on
284	end if;
285	pMPI_Comm_rank(ct,Libr,sram,MPI_COMM_WORLD,MyRank);
286	adresse_rd:=to_integer(unsigned(sram.O.addr_rd));
287
288
289	if ct=0 then
290	RunState<=Fillmem;
291	RunState<=Wincreate;
292	-- synthesis translate_off
293	write (l,string'("Dlen;"& integer'image(dlen) & ";Rank2 " & integer'image(Dlen) & ";" & image(MyRank) & "; ended at ; " & real'image(rt(now))));
294	report l.all;
295	writeline (f, l) ;
296	-- synthesis translate_on
297	end if;
298
299
300	when Wincreate => --par défaut la fenêtre 0 est utilisée !
301	case MyRank is
302	when x"0"=>
303	Mygroup.grp<=x"0002";-- rank 1
304	MyGroup.nb<=2;
305	destRank:=1;
306	DestAdr:=X"043F";
307	nb_rma:=1;
308	when x"1" =>
309	Mygroup.grp<=x"0001";-- rank 0
310	destRank:=0;
311	DestAdr:=X"043F";
312	when x"2" =>
313	Mygroup.grp<=x"0000";-- rank
314	destRank:=0;
315	DestAdr:=X"044F";
316	when x"3" =>
317	Mygroup.grp<=x"0000";-- rank
318	destRank:=0;
319	DestAdr:=X"045F";
320	when others => --cas des processus spawn
321	Mygroup.grp<=x"0000";-- rank 0
322	DestAdr:=X"022F";
323	destRank:=0;
324	end case;
325	RunState<=WinPost;
326	when WinPost =>
327	if ct=0 then
328	-- synthesis translate_off
329	write (l,string'("Dlen;"& integer'image(dlen) & ";WPost1 " & integer'image(Dlen) & "; ; started ; " & real'image(rt(now))));
330	report l.all;
331	writeline (f, l) ;
332	-- synthesis translate_on
333	end if;
334
335	pMPI_Win_Post(ct,Libr,sram,MyGroup,0,MyWin);
336
337	if ct=0 then
338	RunState<=WinStart;
339	-- synthesis translate_off
340	write (l,string'("Dlen;"& integer'image(dlen) & ";WPost2 " & integer'image(Dlen) & ";" & image(MyRank) & "; ended at ; " & real'image(rt(now))));
341	report l.all;
342	writeline (f, l) ;
343	-- synthesis translate_on
344	end if;
345
346	when WinStart =>
347	if ct=0 then
348	-- synthesis translate_off
349	write (l,string'("Dlen;" & integer'image(dlen) & ";WStart1 " & integer'image(Dlen) & "; ; started ; " & real'image(rt(now))));
350	report l.all;
351	writeline (f, l) ;
352	-- synthesis translate_on
353	end if;
354	pMPI_Win_start(ct,Libr,sram,MyGroup,0,MyWin);
355	adresse:=to_integer(unsigned(sram.O.addr_wr));
356	adresse_rd:=to_integer(unsigned(sram.O.addr_rd));
357
358	dcount:=ct;
359
360	if ct=0 then
361	if spawn='0' then
362	RunState<=PutData;
363	else
364	RunState<=WinCompleted;
365	end if;
366	-- synthesis translate_off
367	write (l,string'("Dlen;" & integer'image(dlen) & ";WStart2 " & integer'image(Dlen) & ";" & image(MyRank) & "; ended at ; " & real'image(rt(now))));
368	report l.all;
369	writeline (f, l) ;
370	-- synthesis translate_on
371	end if;
372
373
374	when putdata => --construire le packet pour le Put
375
376	--dlen:=251; ---
377	if ct=0 then
378	-- synthesis translate_off
379	write (l,string'("Dlen;" & integer'image(dlen) & ";PUT1 " & integer'image(dlen) & ";" & image(MyRank) & "; started at ; " & real'image(rt(now))));
380	report l.all;
381	writeline (f, l) ;
382	-- synthesis translate_on
383	end if;
384
385	SrcAdr:=X"0105";--std_logic_vector(to_unsigned(DATAPTR,ADRLEN));
386	--DestAdr:=X"033F";
387	pMPI_put(ct,Libr,Clk,Sram,SrcAdr,Dlen,MPI_int,destrank,DestAdr,Dlen,Mpi_int,Default_win);
388
389	adresse:=to_integer(unsigned(sram.O.addr_wr));
390	adresse_rd:=to_integer(unsigned(sram.O.addr_rd));
391
392	dcount:=ct;
393
394	if ct=0 then
395	RunState<=GetData;
396	-- synthesis translate_off
397	report "Put of Process n°; " & image(MyRank) & "; ended at ; " & real'image(rt(now));
398	write (l,string'("Dlen;" & integer'image(dlen) & ";PUT2 " & integer'image(dlen) & ";" & image(MyRank) & "; ended at time ; " & real'image(rt(now))));
399	report l.all;
400	writeline (f, l) ;
401	-- synthesis translate_on
402	end if;
403
404
405	when getdata => --positionnement du mot de longueur des données
406	--dlen:=251; ---
407	if ct=0 then
408	-- synthesis translate_off
409	write (l,string'("Dlen;" & integer'image(dlen) & ";GET1; " & image(MyRank) & "; started at ; " & real'image(rt(now))));
410	report l.all;
411	writeline (f, l) ;
412	-- synthesis translate_on
413	end if;
414
415	SrcAdr:=X"0104";
416	DestAdr:=X"1400";
417	if unsigned(MyRank) = 0 then
418	pMPI_GET(ct,Libr,Clk,Sram,SrcAdr,Dlen,MPI_int,destrank,DestAdr,Dlen,Mpi_int,Default_win);
419	else
420
421	pMPI_GET(ct,Libr,Clk,Sram,SrcAdr,Dlen,MPI_int,destrank,DestAdr,Dlen,Mpi_int,Default_win);
422	end if;
423	adresse:=to_integer(unsigned(sram.O.addr_wr));
424	adresse_rd:=to_integer(unsigned(sram.O.addr_rd));
425
426	dcount:=ct;
427
428	if ct=0 then
429	if unsigned(MyRank)/=0 then
430	RunState<=wincompleted;
431	else
432	nb_rma:=nb_rma+1;
433	if nb_rma=2 then
434	RunState<=wincompleted;
435	nb_rma:=0;
436	end if;
437	end if;
438	-- synthesis translate_off
439	assert ct/=0 report "GET_END " & integer'image(destrank)
440	severity Warning ;
441	write (l,string'("Dlen ;" & integer'image(dlen) & ";GET2 " & integer'image(dlen) & ";" & image(MyRank) & "; ended at ; " & real'image(rt(now))));
442	report l.all;
443
444	writeline (f, l) ;
445	-- synthesis translate_on
446	end if;
447
448	when WinCompleted =>
449	if ct=0 then
450	-- synthesis translate_off
451	write (l,string'("Dlen ;" & integer'image(dlen) & ";Compl1 " & integer'image(dlen) & ";" & image(MyRank) & "; started at ; " & real'image(rt(now))));
452	report l.all;
453	writeline (f, l) ;
454	-- synthesis translate_on
455	end if;
456	pMPI_Win_Complete(ct,Libr,sram,MyWin );
457	adresse:=to_integer(unsigned(sram.O.addr_wr));
458	adresse_rd:=to_integer(unsigned(sram.O.addr_rd));
459
460	if ct=0 then
461	RunState<=WinWait;
462	-- synthesis translate_off
463	write (l,string'("Dlen ;" & integer'image(dlen) & ";Compl2 " & integer'image(dlen) & ";" & image(MyRank) & "; ended at ; " & real'image(rt(now))));
464	report l.all;
465	writeline (f, l) ;
466	-- synthesis translate_on
467
468	end if;
469	when WinWait =>
470	if ct=0 then
471	-- synthesis translate_off
472	write (l,string'("Dlen ;" & integer'image(dlen) & ";WAIT1 " & integer'image(dlen) & ";" & image(MyRank) & "; started at ; " & real'image(rt(now))));
473	report l.all;
474	writeline (f, l) ;
475	-- synthesis translate_on
476	end if;
477	pMPI_Win_wait(ct,Libr,sram,MyWin );
478	adresse:=to_integer(unsigned(sram.O.addr_wr));
479	adresse_rd:=to_integer(unsigned(sram.O.addr_rd));
480
481	if ct=0 then
482	if unsigned(Myrank)>1 then
483	RunState<=Finalize;
484	else
485	RunState<=MpiSpawn;
486	end if;
487	-- synthesis translate_off
488	write (l,string'("Dlen ;" & integer'image(dlen) & ";WAIT2 " & integer'image(dlen) & ";" & image(MyRank) & "; ended at ; " & real'image(rt(now))));
489	report l.all;
490	writeline (f, l) ;
491	-- synthesis translate_on
492
493	end if;
494
495	when MpiSpawn =>
496	if ct=0 then
497	-- synthesis translate_off
498	write (l,string'("Dlen ;" & integer'image(dlen) & ";Spawn1 " & integer'image(dlen) & ";" & image(MyRank) & "; started at ; " & real'image(rt(now))));
499	report l.all;
500	writeline (f, l) ;
501	-- synthesis translate_on
502	end if;
503	--(NextCtx : inout natural;signal Interf:inout Core_io;signal SysRam :inout typ_dpram;
504
505	maxprocs:=2;
506	pMPI_Comm_Spawn(ct,Libr,sram,command,argv,maxprocs,info,root,comm,intercomm,array_of_errcodes);
507	adresse:=to_integer(unsigned(sram.O.addr_wr));
508	adresse_rd:=to_integer(unsigned(sram.O.addr_rd));
509
510	if ct=0 then
511	if unsigned(Myrank)=0 and spawn='0' then
512	MyGroup.Grp<=x"000C";
513	spawn:='1';
514	Runstate<=WinPost;
515	else
516	RunState<=Finalize;
517	end if;
518	-- synthesis translate_off
519	write (l,string'("Dlen ;" & integer'image(dlen) & ";Spawn2 " & integer'image(dlen) & ";" & image(MyRank) & "; ended at ; " & real'image(rt(now))));
520	report l.all;
521	writeline (f, l) ;
522	-- synthesis translate_on
523
524	end if;
525	when finalize =>
526	if ct=0 then
527	-- synthesis translate_off
528	write (l,string'("Dlen ;" & integer'image(dlen) & ";FINALIZE1 " & integer'image(dlen) & ";" & image(MyRank) & "; started at ; " & real'image(rt(now))));
529	report l.all;
530	writeline (f, l) ;
531	-- synthesis translate_on
532	end if;
533	sram.O.we<='0';
534	sram.O.ena<='0';
535	sram.O.enb<='0';
536	if ct=0 then
537	RunState<=start;
538	-- synthesis translate_off
539	write (l,string'("Dlen ;" & integer'image(dlen) & ";FINALIZE2 " & integer'image(dlen) & ";" & image(MyRank) & "; ended at ; " & real'image(rt(now))));
540	report l.all;
541	writeline (f, l) ;
542	file_close(f);
543	-- synthesis translate_on
544	end if;
545
546	when st_timeout =>
547
548	sram.O.we<='0';
549	sram.O.ena<='0';
550	sram.O.enb<='0';
551
552	RunState<=start;
553	end case;
554	ct_state<=ct; --pour débogage
555	end if;
556	end if;
557
558	end process pPutGet;
559
560	end Behavioral;
561

Note: See TracBrowser for help on using the repository browser.

Context Navigation

source: PROJECT_CORE_MPI/MPI_HCL/TRUNK/HT_process.vhd

Download in other formats: