[114] | 1 | ---------------------------------------------------------------------------------- |
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| 2 | -- Company: |
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| 3 | -- Engineer: GAMOM Roland Christian |
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| 4 | -- |
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| 5 | -- Create Date: 17:38:35 04/20/2013 |
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| 6 | -- Design Name: |
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| 7 | -- Module Name: Hold_FSM - Behavioral |
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| 8 | -- Project Name: |
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| 9 | -- Target Devices: |
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| 10 | -- Tool versions: |
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| 11 | -- Description: |
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| 12 | -- |
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| 13 | -- Dependencies: |
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| 14 | -- |
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| 15 | -- Revision: |
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| 16 | -- Revision 0.01 - File Created |
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| 17 | -- Additional Comments: |
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| 18 | -- |
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| 19 | ---------------------------------------------------------------------------------- |
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| 20 | library IEEE; |
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| 21 | use IEEE.STD_LOGIC_1164.ALL; |
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| 22 | |
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| 23 | -- Uncomment the following library declaration if using |
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| 24 | -- arithmetic functions with Signed or Unsigned values |
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| 25 | --use IEEE.NUMERIC_STD.ALL; |
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| 26 | |
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| 27 | -- Uncomment the following library declaration if instantiating |
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| 28 | -- any Xilinx primitives in this code. |
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| 29 | --library UNISIM; |
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| 30 | --use UNISIM.VComponents.all; |
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| 31 | |
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| 32 | entity Hold_FSM is |
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| 33 | Port ( Hold_Req : in STD_LOGIC; |
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| 34 | ram_busy : in STD_LOGIC; |
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| 35 | Clk : in STD_LOGIC; |
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| 36 | Reset : in STD_LOGIC; |
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| 37 | Ramsel : out STD_LOGIC; |
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| 38 | Hold_Ack : out STD_LOGIC); |
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| 39 | end Hold_FSM; |
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| 40 | |
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| 41 | architecture Behavioral of Hold_FSM is |
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| 42 | type typ_Hld is (Ht_Lock,Core_Lock,Ht_free); |
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| 43 | signal Holdstate,Hold_st :typ_hld; |
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| 44 | signal Ram_sel :std_logic:='0'; |
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| 45 | signal front_Rbusy,front_hReq:std_logic:='0'; |
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| 46 | begin |
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| 47 | |
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| 48 | hold_sync:process (clk,reset) |
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| 49 | begin |
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| 50 | if rising_edge(clk) then |
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| 51 | |
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| 52 | |
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| 53 | end if; |
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| 54 | end process hold_sync; |
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| 55 | Ramsel_state:process(clk)--,HoldState,Hold_Req,ram_Busy,Front_HReq,Front_RBusy) |
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| 56 | |
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| 57 | begin |
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| 58 | |
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| 59 | if rising_edge(clk) then |
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| 60 | if reset='1' then |
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| 61 | HolDState<=Ht_free; |
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| 62 | else |
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| 63 | -- HolDState<=Hold_St; |
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| 64 | -- Hold_St<=HoldState; |
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| 65 | case HoldState is |
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| 66 | when Ht_free => |
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| 67 | if Hold_Req='1' and ram_busy='0' then |
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| 68 | HolDState <=Core_lock; |
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| 69 | elsif Hold_Req='0' and ram_busy='1' then |
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| 70 | HoldState <=HT_lock; |
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| 71 | elsif Hold_Req='1' and ram_busy='1' then |
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| 72 | HoldState <=HT_lock; |
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| 73 | else |
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| 74 | HoldState <=HT_free; |
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| 75 | end if; |
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| 76 | when Ht_lock => |
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| 77 | if Hold_Req='0' and ram_busy='0' then |
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| 78 | HoldState <=HT_free; |
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| 79 | elsif Hold_Req='1' and Ram_busy='0' then |
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| 80 | HoldState <=Core_lock; |
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| 81 | else |
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| 82 | HoldState <=HT_lock; |
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| 83 | end if; |
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| 84 | |
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| 85 | When Core_lock => |
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| 86 | If Hold_Req='0' and Ram_busy='0' then |
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| 87 | HoldState <=HT_free; |
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| 88 | elsif Hold_Req='0' and Ram_busy='1' then |
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| 89 | HoldState <=HT_lock; |
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| 90 | else |
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| 91 | HoldState <=Core_lock; |
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| 92 | end if; |
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| 93 | end case ; |
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| 94 | end if; |
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| 95 | end if; |
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| 96 | |
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| 97 | end process; |
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| 98 | |
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| 99 | Ramsel_val:process(HoldState,Hold_Req,Ram_Busy) |
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| 100 | |
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| 101 | begin |
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| 102 | case HoldState is |
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| 103 | when Ht_free => |
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| 104 | ram_sel<='0'; |
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| 105 | Hold_Ack<='0'; |
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| 106 | when Ht_Lock => |
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| 107 | ram_sel<='0'; |
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| 108 | Hold_Ack<='0'; |
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| 109 | when Core_lock => |
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| 110 | Ram_sel <='1'; |
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| 111 | Hold_Ack<='1'; |
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| 112 | end case; |
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| 113 | if Hold_Req= not(front_HReq) then |
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| 114 | front_HReq<= not front_HReq; |
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| 115 | end if; |
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| 116 | |
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| 117 | if Ram_busy= not (front_RBusy) then |
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| 118 | front_RBusy<= not front_RBusy; |
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| 119 | end if; |
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| 120 | end process ramsel_val; |
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| 121 | Ramsel<=Ram_sel; |
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| 122 | --======================================================================= |
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| 123 | end Behavioral; |
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| 124 | |
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