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[104] | 1 | --------------------------------------------------------------------------------- |
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| 2 | -- Company: |
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| 3 | -- Engineer: |
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| 4 | -- |
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| 5 | -- Create Date: 15:11:13 01/16/2014 |
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| 6 | -- Design Name: |
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| 7 | -- Module Name: IP_Timer - Behavioral |
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| 8 | -- Project Name: |
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| 9 | -- Target Devices: |
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| 10 | -- Tool versions: |
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| 11 | -- Description: |
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| 12 | -- |
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| 13 | -- Dependencies: |
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| 14 | -- |
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| 15 | -- Revision: |
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| 16 | -- Revision 0.01 - File Created |
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| 17 | -- Additional Comments: |
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| 18 | -- |
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| 19 | ---------------------------------------------------------------------------------- |
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| 20 | |
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| 21 | library ieee; |
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| 22 | use ieee.std_logic_1164.all; |
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| 23 | use ieee.std_logic_unsigned.all; |
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| 24 | -- Uncomment the following library declaration if using |
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| 25 | -- arithmetic functions with Signed or Unsigned values |
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| 26 | use IEEE.NUMERIC_STD.ALL; |
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| 27 | |
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| 28 | -- Uncomment the following library declaration if instantiating |
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| 29 | -- any Xilinx primitives in this code. |
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| 30 | --library UNISIM; |
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| 31 | --use UNISIM.VComponents.all; |
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| 32 | |
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| 33 | entity IP_Timer is |
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| 34 | |
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| 35 | port (clk,reset,upDn,load,start:in std_logic; |
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| 36 | loadval :in std_logic_vector(31 downto 0); |
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| 37 | outval : out std_logic_vector(31 downto 0); |
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| 38 | zero : out std_logic); |
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| 39 | |
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| 40 | end IP_Timer; |
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| 41 | |
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| 42 | architecture Behavioral of IP_Timer is |
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| 43 | signal count: std_logic_vector(31 downto 0); |
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| 44 | signal z:std_logic:='1'; |
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| 45 | begin |
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| 46 | process (clk) |
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| 47 | begin |
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| 48 | if clk='1' and clk'event then |
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| 49 | if reset='1' then |
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| 50 | count <= (others => '0'); |
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| 51 | z<='1'; |
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| 52 | elsif start='1' then |
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| 53 | if load='1' then |
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| 54 | count <= loadval; |
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| 55 | else |
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| 56 | if UpDn='1' then |
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| 57 | count <= count + 1; |
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| 58 | else |
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| 59 | count <= count - 1; |
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| 60 | end if; |
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| 61 | end if; |
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| 62 | if count=0 then |
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| 63 | z<='1'; |
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| 64 | else |
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| 65 | z<='0'; |
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| 66 | end if; |
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| 67 | end if; |
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| 68 | end if; |
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| 69 | end process; |
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| 70 | OutVal<=count; |
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| 71 | zero<=z; |
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| 72 | end Behavioral; |
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| 73 | |
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