[135] | 1 | ---------------------------------------------------------------------------------- |
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| 2 | -- Company: |
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| 3 | -- Engineer: |
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| 4 | -- |
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| 5 | -- Create Date: 17:58:09 04/07/2014 |
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| 6 | -- Design Name: |
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| 7 | -- Module Name: Def_Request - Behavioral |
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| 8 | -- Project Name: |
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| 9 | -- Target Devices: |
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| 10 | -- Tool versions: |
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| 11 | -- Description: |
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| 12 | -- |
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| 13 | -- Dependencies: |
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| 14 | -- |
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| 15 | -- Revision: |
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| 16 | -- Revision 0.01 - File Created |
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| 17 | -- Additional Comments: |
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| 18 | -- |
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| 19 | ---------------------------------------------------------------------------------- |
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| 20 | library IEEE; |
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| 21 | use IEEE.STD_LOGIC_1164.ALL; |
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| 22 | use IEEE.STD_LOGIC_ARITH.ALL; |
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| 23 | use IEEE.STD_LOGIC_UNSIGNED.ALL; |
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| 24 | -- Uncomment the following library declaration if using |
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| 25 | -- arithmetic functions with Signed or Unsigned values |
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| 26 | --use IEEE.NUMERIC_STD.ALL; |
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| 27 | |
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| 28 | -- Uncomment the following library declaration if instantiating |
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| 29 | -- any Xilinx primitives in this code. |
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| 30 | --library UNISIM; |
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| 31 | --use UNISIM.VComponents.all; |
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| 32 | |
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| 33 | entity Def_Request is |
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| 34 | generic (NB_IO :positive:=4); |
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| 35 | Port ( Req : in STD_LOGIC_VECTOR (NB_IO**2 downto 1); |
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| 36 | clk : in STD_LOGIC; |
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| 37 | reset : in STD_LOGIC; |
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| 38 | fifo_full : in STD_LOGIC_VECTOR (NB_IO downto 1); |
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| 39 | priority_rotation : in STD_LOGIC_VECTOR (NB_IO downto 1); |
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| 40 | grant : in STD_LOGIC_VECTOR (NB_IO**2 downto 1); |
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| 41 | request : out STD_LOGIC_VECTOR (NB_IO**2 downto 1)); |
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| 42 | end Def_Request; |
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| 43 | |
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| 44 | architecture Behavioral of Def_Request is |
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| 45 | constant NB_IO2 :positive:=NB_IO**2; -- le carré du nombre de ports d'E/S |
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| 46 | Signal Fifo_out_full : STD_LOGIC_VECTOR (NB_IO downto 1); |
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| 47 | signal grant_latch : std_logic_vector(NB_IO2 downto 1); |
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| 48 | signal priority_rotation_en : std_logic; |
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| 49 | signal req_grant,Grant_bak : std_logic_vector(NB_IO2 downto 1):=(others=>'0'); |
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| 50 | signal Mreq : std_logic_vector(NB_IO2 downto 1):=(others=>'1'); |
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| 51 | |
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| 52 | begin |
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| 53 | Req_grant<=(req and grant ); |
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| 54 | priority_rotation_en <= '1' when unsigned(priority_rotation) = 2**NB_IO-1 else '0'; |
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| 55 | request<=req and mreq; |
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| 56 | --latch qui memorise le signal grant pendant la transmission |
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| 57 | grant_latch_process : process(clk) |
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| 58 | begin |
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| 59 | if rising_edge(clk) then |
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| 60 | if reset = '1' then |
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| 61 | grant_latch <= (others => '0'); |
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| 62 | Fifo_out_full<=(others => '0'); |
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| 63 | elsif priority_rotation_en = '1' or unsigned(req_grant)=0 then |
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| 64 | grant_latch <= Grant; |
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| 65 | Fifo_out_full<=fifo_full; |
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| 66 | else |
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| 67 | grant_latch <= Grant; |
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| 68 | Fifo_out_full<=fifo_full; |
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| 69 | end if; |
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| 70 | end if; |
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| 71 | |
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| 72 | end process; |
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| 73 | def_mreq: process(grant_latch,fifo_full) |
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| 74 | |
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| 75 | variable t:std_logic_vector(NB_IO2 downto 1):=(others=>'0'); |
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| 76 | begin |
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| 77 | |
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| 78 | for i in 0 to NB_IO2-1 loop |
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| 79 | t(i+1):='0'; |
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| 80 | --sur le front montant de fifo_full sauver l'état Grant courant |
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| 81 | if fifo_full(i mod NB_IO+1)='1' and fifo_out_full(i mod NB_IO+1)='0' then |
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| 82 | Grant_bak(i+1)<= grant_latch(i+1); |
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| 83 | elsif fifo_full(i mod NB_IO+1)='0' and fifo_out_full(i mod NB_IO+1)='0' then |
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| 84 | Grant_bak(i+1)<='0'; |
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| 85 | end if; |
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| 86 | for j in 0 to NB_IO-1 loop |
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| 87 | t(i+1):=t(i+1) or grant_latch(j*NB_IO+1+i mod NB_IO) or fifo_out_full(i mod NB_IO+1); |
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| 88 | |
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| 89 | end loop; |
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| 90 | mreq(i+1)<=not(t(i+1) ) or grant_latch(i+1)or grant_bak(i+1); |
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| 91 | end loop; |
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| 92 | end process; |
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| 93 | |
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| 94 | end Behavioral; |
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| 95 | |
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