[101] | 1 | ---------------------------------------------------------------------------------- |
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| 2 | -- Company: |
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| 3 | -- Engineer: KIEGAING EMMANUEL/GAMOM |
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| 4 | -- |
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| 5 | -- Create Date: 19:51:54 04/19/2011 |
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| 6 | -- Design Name: |
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| 7 | -- Module Name: FIFO_64 - Behavioral |
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| 8 | -- Project Name: |
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| 9 | -- Target Devices: |
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| 10 | -- Tool versions: |
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| 11 | -- Description: |
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| 12 | --FIFO 64 Octets utisé pour les modules d'entrée |
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| 13 | -- ce fifo est de type fwft first word falls throught ce qui |
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| 14 | -- signifie que l'on a toujours la donnée au sommet de la pile en |
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| 15 | -- sortie du fifo. |
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| 16 | -- Dependencies: RAM_64.vhd |
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| 17 | -- |
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| 18 | -- Revision: 30-07-2012 |
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| 19 | -- Revision 0.01 - File Created |
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| 20 | -- Additional Comments: |
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| 21 | -- le signal counter_en a été supprimé |
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| 22 | ---------------------------------------------------------------------------------- |
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| 23 | library IEEE; |
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| 24 | |
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| 25 | use IEEE.STD_LOGIC_1164.ALL; |
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| 26 | use IEEE.STD_LOGIC_ARITH.ALL; |
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| 27 | use IEEE.STD_LOGIC_UNSIGNED.ALL; |
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| 28 | --Library NocLib; |
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| 29 | --use NocLib.CoreTypes.all; |
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| 30 | use work.CoreTypes.all; |
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| 31 | ---- Uncomment the following library declaration if instantiating |
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| 32 | ---- any Xilinx primitives in this code. |
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| 33 | library UNISIM; |
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| 34 | use UNISIM.VComponents.all; |
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| 35 | |
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| 36 | entity FIFO_256_FWFT is |
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| 37 | Port ( clk : in STD_LOGIC; |
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| 38 | din : in STD_LOGIC_VECTOR (Word-1 downto 0); |
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| 39 | rd_en : in STD_LOGIC; |
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| 40 | srst : in STD_LOGIC; |
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| 41 | wr_en : in STD_LOGIC; |
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| 42 | dout : out STD_LOGIC_VECTOR (Word-1 downto 0); |
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| 43 | empty : out STD_LOGIC; |
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| 44 | full : out STD_LOGIC); |
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| 45 | end FIFO_256_FWFT; |
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| 46 | |
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| 47 | architecture Behavioral of FIFO_256_FWFT is |
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| 48 | -- declaration de la ram 256 octets |
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| 49 | COMPONENT RAM_256 |
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| 50 | PORT( |
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| 51 | clka : IN std_logic; |
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| 52 | clkb : IN std_logic; |
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| 53 | wea : IN std_logic; |
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| 54 | ena : IN std_logic; |
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| 55 | enb : IN std_logic; |
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| 56 | addra : IN std_logic_vector(Word-1 downto 0); |
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| 57 | addrb : IN std_logic_vector(Word-1 downto 0); |
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| 58 | dia : IN std_logic_vector(Word-1 downto 0); |
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| 59 | dob : OUT std_logic_vector(Word-1 downto 0) |
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| 60 | ); |
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| 61 | END COMPONENT; |
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| 62 | |
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| 63 | constant MPROOF : positive:=2; --cette constante définit la profondeur des fifos |
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| 64 | type fsm_states is (state0, state1, state2, state3);-- definition du type etat pour le codage des etats des fsm |
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| 65 | signal fwft_fsm_state,next_fwft_state : fsm_states; |
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| 66 | attribute RAM_STYLE : string; |
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| 67 | |
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| 68 | type ram_type is array (2**(MPROOF+word)-1 downto 0) of std_logic_vector (Word-1 downto 0); |
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| 69 | signal RAM: ram_type; |
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| 70 | attribute RAM_STYLE of RAM: signal is "BLOCK"; |
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| 71 | -- declaration des signeaux des compteurs |
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| 72 | signal push_address_counter: std_logic_vector(MPROOF+Word-1 downto 0); |
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| 73 | signal pop_address_counter : std_logic_vector(MPROOF+Word-1 downto 0); |
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| 74 | signal fifo_counter : std_logic_vector(MPROOF+Word-1 downto 0); |
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| 75 | --autre signaux |
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| 76 | signal empty_signal: std_logic:='1'; |
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| 77 | signal rd_ready,rd_ready_i : std_logic:='0'; |
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| 78 | signal full_signal : std_logic; |
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| 79 | signal near_full :std_logic; |
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| 80 | signal wr_en_signal : std_logic;--_vector(0 downto 0); |
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| 81 | signal rd_en_signal : std_logic; |
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| 82 | signal clk_signal : std_logic; |
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| 83 | signal dob_signal : std_logic_vector(Word-1 downto 0); |
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| 84 | signal dout_signal : std_logic_vector(Word-1 downto 0); |
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| 85 | signal doa_signal : std_logic_vector(Word-1 downto 0); |
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| 86 | signal counter_en : std_logic; |
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| 87 | |
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| 88 | begin |
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| 89 | |
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| 90 | -- ram instantiation de la bloc ram 256 octets du FIFO |
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| 91 | --fifo_RAM_256: RAM_256 PORT MAP( |
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| 92 | -- clka => clk_signal, |
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| 93 | -- clkb => clk_signal, |
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| 94 | -- wea => wr_en_signal, |
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| 95 | -- ena => '1', |
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| 96 | -- enb => '1', |
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| 97 | -- addra => push_address_counter, |
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| 98 | -- addrb => pop_address_counter, |
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| 99 | -- dia => din, |
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| 100 | -- dob => dob_signal |
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| 101 | -- --dob => doa_signal |
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| 102 | -- ); |
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| 103 | |
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| 104 | -- circuiterie des signaux de validation et d'etat du fifo |
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| 105 | wr_en_signal <= wr_en and (not full_signal); -- la donnée est ignorée si le fifo est plein |
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| 106 | rd_en_signal <= rd_en and (not empty_signal);-- pas de lecture si le fifo est vide |
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| 107 | full_signal <= '1' when unsigned(fifo_counter) = 2**(MProof+word)-1 else |
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| 108 | '0'; |
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| 109 | near_full <= '1' when unsigned(fifo_counter) >= 2**(MProof+word)-5 else |
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| 110 | '0'; |
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| 111 | --empty_signal <= '1' when fifo_counter = "000000" else |
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| 112 | -- '0'; |
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| 113 | empty_signal <= '1' when (rd_ready='0') else -- or (All_zeros(fifo_counter) = '0') else |
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| 114 | '0'; |
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| 115 | clk_signal <= clk; |
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| 116 | full <= near_full; |
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| 117 | empty <= empty_signal ; |
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| 118 | |
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| 119 | -- sortie du fifo fwft |
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| 120 | dout <= dout_signal; |
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| 121 | -- le processus synchrone de la MAE |
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| 122 | fwft_fsm_sync : process(clk_signal) |
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| 123 | begin |
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| 124 | if rising_edge(clk_signal) then |
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| 125 | if srst = '1' then |
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| 126 | |
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| 127 | fwft_fsm_state <= state0; |
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| 128 | rd_ready<='0'; |
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| 129 | else |
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| 130 | fwft_fsm_state<= next_fwft_state; |
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| 131 | rd_ready<=rd_ready_i; |
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| 132 | end if; |
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| 133 | |
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| 134 | end if; |
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| 135 | end process; |
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| 136 | -- le processus des transistion |
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| 137 | fwft_fsm_nsl : process(rd_ready,fwft_fsm_state,fifo_counter,rd_en_signal,wr_en_signal) |
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| 138 | begin |
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| 139 | --Fifo_counter=0 -->state0, |
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| 140 | --Fifo_counter=1 -->state1, |
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| 141 | --Fifo_counter>1 -->state2, |
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| 142 | rd_ready_i<=rd_ready; |
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| 143 | next_fwft_state<=fwft_fsm_state; |
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| 144 | case fwft_fsm_state is |
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| 145 | when state0 => if wr_en_signal = '1' then --tampon vide seule l'écriture est possible |
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| 146 | next_fwft_state <= state1; |
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| 147 | end if; |
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| 148 | rd_ready_i<='0'; |
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| 149 | --une seule donnée dans le fifo |
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| 150 | when state1 => rd_ready_i<='1'; |
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| 151 | if rd_en_signal = '1' and wr_en_signal='1' then |
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| 152 | |
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| 153 | next_fwft_state <= state1; |
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| 154 | elsif rd_en_signal = '1' and wr_en_signal='0' then |
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| 155 | next_fwft_state <= state0; |
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| 156 | rd_ready_i<='0'; |
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| 157 | elsif rd_en_signal = '0' and wr_en_signal='1' then |
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| 158 | next_fwft_state <= state2; |
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| 159 | else |
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| 160 | next_fwft_state <= state1; |
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| 161 | end if; |
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| 162 | --plus d'une donnée dans le fifo |
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| 163 | when state2 => rd_ready_i<='1'; |
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| 164 | if unsigned(fifo_counter) > 1 then |
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| 165 | next_fwft_state <= state2; |
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| 166 | elsif unsigned(fifo_counter)=1 and rd_en_signal = '1' and wr_en_signal = '0' then |
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| 167 | next_fwft_state <= state0; |
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| 168 | rd_ready_i<='0'; |
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| 169 | elsif unsigned(fifo_counter) = 1 and not(rd_en_signal='1' and wr_en_signal='0') then |
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| 170 | next_fwft_state <= state1; |
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| 171 | elsif unsigned(fifo_counter) = 0 then |
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| 172 | next_fwft_state <= state0; |
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| 173 | rd_ready_i<='0'; |
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| 174 | else |
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| 175 | next_fwft_state <= state2; |
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| 176 | end if; |
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| 177 | |
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| 178 | when state3 => rd_ready_i<='1'; |
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| 179 | if rd_en_signal = '1' then --écriture seule dans le tampon |
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| 180 | next_fwft_state <= state0; |
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| 181 | rd_ready_i<='0'; |
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| 182 | elsif wr_en_signal='1' then |
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| 183 | next_fwft_state <= state2; |
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| 184 | end if; |
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| 185 | |
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| 186 | -- when others => fwft_fsm_state <= state0; |
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| 187 | |
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| 188 | |
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| 189 | end case; |
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| 190 | |
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| 191 | end process; |
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| 192 | -- actions associées à la fsm |
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| 193 | -- mux qui oriente les sortie doa et dob vers out |
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| 194 | with fwft_fsm_state select |
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| 195 | dout_signal <= dob_signal when state0, |
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| 196 | doa_signal when state1, --la sortie est la donnée en entrée |
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| 197 | dob_signal when state2, -- la sortie vient de la RAM |
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| 198 | dob_signal when state3, |
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| 199 | doa_signal when others; |
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| 200 | -- counter_en |
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| 201 | with fwft_fsm_state select |
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| 202 | counter_en <= '0' when state0, |
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| 203 | '1' when state1, |
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| 204 | '1' when state2, |
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| 205 | '1' when state3, |
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| 206 | '0' when others; |
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| 207 | |
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| 208 | --with fwft_fsm_state select |
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| 209 | -- rd_ready <= '0' when state0, |
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| 210 | -- '1' when state1, |
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| 211 | -- '1' when state2, |
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| 212 | -- '1' when state3, |
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| 213 | -- '0' when others; |
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| 214 | doa_latch_process : process(clk_signal) |
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| 215 | begin |
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| 216 | if rising_edge(clk_signal) then |
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| 217 | if wr_en_signal ='1' then |
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| 218 | doa_signal <= din; |
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| 219 | end if; |
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| 220 | end if; |
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| 221 | end process; |
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| 222 | |
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| 223 | -- processus de comptage des adresses d'empilement |
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| 224 | push_process : process(clk_signal) |
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| 225 | begin |
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| 226 | if rising_edge(clk_signal) then |
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| 227 | if srst = '1' then |
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| 228 | push_address_counter <= (others =>'0'); |
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| 229 | elsif wr_en_signal ='1' then |
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| 230 | RAM(conv_integer(push_address_counter)) <=din; |
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| 231 | push_address_counter <= push_address_counter +1; |
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| 232 | end if; |
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| 233 | if rd_en_signal='1' then |
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| 234 | dob_signal<=RAM(conv_integer(pop_address_counter+1)); |
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| 235 | else |
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| 236 | dob_signal<=RAM(conv_integer(pop_address_counter)); |
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| 237 | end if; |
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| 238 | end if; |
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| 239 | end process; |
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| 240 | |
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| 241 | -- processus de comptage des adresses depilement du fifo |
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| 242 | pop_process : process(clk_signal) |
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| 243 | begin |
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| 244 | if rising_edge(clk_signal) then |
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| 245 | if srst = '1' then |
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| 246 | pop_address_counter <= (others =>'0'); --pour avoir un décalage entre la valeur lue et celle qui est écrite |
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| 247 | elsif rd_en_signal ='1' then |
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| 248 | pop_address_counter <= pop_address_counter+1; |
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| 249 | end if; |
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| 250 | |
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| 251 | end if; |
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| 252 | end process; |
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| 253 | |
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| 254 | -- processus de comptage des octets dans le fifo |
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| 255 | fifo_counter_process : process(clk_signal) |
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| 256 | variable count : std_logic_vector(MPROOF+word-1 downto 0):= (others=>'0'); |
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| 257 | begin |
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| 258 | if rising_edge(clk_signal) then |
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| 259 | if srst = '1' then |
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| 260 | fifo_counter <= (others =>'0'); |
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| 261 | count:=(others =>'0'); |
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| 262 | else |
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| 263 | if wr_en_signal ='1' and rd_en_signal ='0' then |
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| 264 | --fifo_counter <= fifo_counter +1; |
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| 265 | count:=count+1; |
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| 266 | end if; |
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| 267 | if rd_en_signal ='1' and wr_en_signal ='0' and counter_en='1' then |
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| 268 | --fifo_counter <= fifo_counter - 1; |
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| 269 | count:=count-1; |
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| 270 | end if; |
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| 271 | fifo_counter<=count; |
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| 272 | end if; |
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| 273 | end if; |
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| 274 | end process; |
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| 275 | |
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| 276 | end Behavioral; |
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| 277 | |
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