[101] | 1 | |
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| 2 | ---------------------------------------------------------------------------------- |
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| 3 | -- Company: |
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| 4 | -- Engineer: |
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| 5 | -- |
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| 6 | -- Create Date: 09:29:48 04/18/2011 |
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| 7 | -- Design Name: |
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| 8 | -- Module Name: OUTPUT_PORT_MODULE - Behavioral_description |
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| 9 | -- Project Name: |
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| 10 | -- Target Devices: |
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| 11 | -- Tool versions: |
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| 12 | -- Description: |
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| 13 | -- cette version du module de sortie se limite à une instance du fifo ordinaire |
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| 14 | -- les données son emise en sortie à chaque cycle d'horloge |
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| 15 | -- Dependencies: |
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| 16 | -- |
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| 17 | -- Revision: 07-08-2013 |
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| 18 | -- Revision 0.01 - File Created |
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| 19 | -- Additional Comments: Ajout d'un délai pour ignorer les paquets qui sont là depuis |
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| 20 | -- longtemps |
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| 21 | -- |
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| 22 | ---------------------------------------------------------------------------------- |
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| 23 | library IEEE; |
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| 24 | use IEEE.STD_LOGIC_1164.ALL; |
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| 25 | --use IEEE.STD_LOGIC_ARITH.ALL; |
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| 26 | --use IEEE.STD_LOGIC_UNSIGNED.ALL; |
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| 27 | USE ieee.numeric_std.ALL; |
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| 28 | Library NocLib; |
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| 29 | use NocLib.CoreTypes.all; |
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| 30 | ---- Uncomment the following library declaration if instantiating |
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| 31 | ---- any Xilinx primitives in this code. |
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| 32 | --library UNISIM; |
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| 33 | --use UNISIM.VComponents.all; |
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| 34 | |
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| 35 | entity OUTPUT_PORT_MODULE is |
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| 36 | Port ( data_in : in STD_LOGIC_VECTOR (Word-1 downto 0); |
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| 37 | reset : in STD_LOGIC; |
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| 38 | clk : in STD_LOGIC; |
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| 39 | wr_en : in STD_LOGIC; |
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| 40 | data_out : out STD_LOGIC_VECTOR (Word-1 downto 0); |
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| 41 | fifo_full : out std_logic; |
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| 42 | data_avalaible : out std_logic; |
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| 43 | rd_out_en : in STD_LOGIC); |
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| 44 | end OUTPUT_PORT_MODULE; |
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| 45 | |
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| 46 | architecture Behavioral_description of OUTPUT_PORT_MODULE is |
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| 47 | -- declaration du FIFO 64 octets |
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| 48 | component FIFO_256_FWFT |
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| 49 | port ( |
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| 50 | clk: IN std_logic; |
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| 51 | din: IN std_logic_VECTOR(Word-1 downto 0); |
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| 52 | rd_en: IN std_logic; |
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| 53 | srst: IN std_logic; |
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| 54 | wr_en: IN std_logic; |
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| 55 | dout: out std_logic_VECTOR(Word-1 downto 0); |
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| 56 | empty: OUT std_logic; |
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| 57 | full: OUT std_logic); |
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| 58 | end component; |
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| 59 | --definition du type etat pour les fsm |
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| 60 | type typ_outfsm is (Idle,waiting,dropping,reading); |
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| 61 | type typ_receiv is (r_wait,r_head,r_len,r_glen,r_data,r_pulse,r_end); |
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| 62 | |
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| 63 | signal EtRec : typ_receiv; |
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| 64 | signal Et_out_fsm : typ_outfsm; |
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| 65 | signal fifo_empty : std_logic; |
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| 66 | signal sw : std_logic:='0'; -- permet de positionner le mux sur les signaux internes |
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| 67 | signal tlimit : natural:=0; --permet de compter les impulsions de temps |
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| 68 | signal n : natural:=0; --utiliser pour la mae du tampon de sortie |
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| 69 | signal rcv_start : std_logic; --début de la réception |
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| 70 | signal rcv_ack : std_logic; -- acquittement de la réception |
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| 71 | signal rcv_comp : std_logic; -- fin de la réception |
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| 72 | signal spop,pop,rd_en,dat_avail : std_logic:='0'; |
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| 73 | signal mem,fifo_out : std_logic_vector(Word-1 downto 0); --variable tampon sans intérêt réel |
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| 74 | begin |
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| 75 | -- instantiation du FIFO_64 |
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| 76 | OUTPUT_PORT_FIFO : FIFO_256_FWFT |
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| 77 | port map ( |
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| 78 | clk => clk, |
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| 79 | din => data_in, |
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| 80 | rd_en => rd_en, |
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| 81 | srst => reset, |
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| 82 | wr_en => wr_en, |
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| 83 | dout => fifo_out, |
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| 84 | empty => fifo_empty, |
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| 85 | full => fifo_full); |
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| 86 | |
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| 87 | |
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| 88 | outport_proc : process(clk,reset,fifo_empty) |
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| 89 | begin |
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| 90 | if rising_edge(clk) then |
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| 91 | if reset='1' then |
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| 92 | n<=0; |
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| 93 | Et_out_fsm<=Idle; |
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| 94 | else |
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| 95 | case(Et_out_fsm) is |
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| 96 | |
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| 97 | when Idle => --idle |
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| 98 | if fifo_empty = '0' then |
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| 99 | Et_Out_fsm<=waiting; |
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| 100 | end if; |
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| 101 | tlimit<=0; |
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| 102 | sw<='0'; |
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| 103 | when reading => |
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| 104 | if rd_out_en='0' then |
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| 105 | Et_out_fsm<=Idle; |
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| 106 | end if; |
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| 107 | sw<='0'; |
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| 108 | when waiting => --counting |
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| 109 | if rd_out_en='1' then |
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| 110 | Et_out_fsm<=reading; |
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| 111 | elsif tlimit=5000 then |
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| 112 | Et_out_fsm<=dropping; |
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| 113 | tlimit<=0; |
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| 114 | else |
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| 115 | tlimit<=tlimit+1; |
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| 116 | end if; |
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| 117 | sw<='0'; |
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| 118 | when dropping => --dropping packet |
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| 119 | if n=0 then |
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| 120 | rcv_start<='1'; |
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| 121 | n<=1; |
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| 122 | sw<='1'; |
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| 123 | elsif n=1 then |
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| 124 | if rcv_comp='1' then |
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| 125 | rcv_ack<='1'; |
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| 126 | rcv_start<='0'; |
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| 127 | n<=2; |
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| 128 | end if; |
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| 129 | sw<='1'; |
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| 130 | elsif n=2 then |
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| 131 | sw<='0'; |
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| 132 | Et_out_fsm<=Idle; |
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| 133 | report "Attention Paquet perdu !à Output_Port_Module"; |
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| 134 | n<=0; |
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| 135 | end if; |
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| 136 | |
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| 137 | end case; |
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| 138 | end if; |
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| 139 | end if; |
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| 140 | end process outport_proc; |
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| 141 | data_out<=fifo_out; |
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| 142 | mux_proc : process (sw,rd_out_en,pop,fifo_empty) |
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| 143 | begin |
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| 144 | if sw='1' then --mode drop |
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| 145 | rd_en<=pop; |
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| 146 | data_avalaible <='0'; --plus de données dans le tampon ! |
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| 147 | else |
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| 148 | rd_en<=rd_out_en; |
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| 149 | data_avalaible <= not fifo_empty; |
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| 150 | end if; |
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| 151 | end process mux_proc; |
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| 152 | proc_receiv : process (clk,reset) |
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| 153 | variable dlen,i: natural range 0 to 255 :=0; |
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| 154 | |
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| 155 | begin |
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| 156 | if reset='1' then |
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| 157 | etrec<=r_wait; |
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| 158 | |
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| 159 | else |
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| 160 | if rising_edge(clk) then -- le process s'exécute sur chaque front |
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| 161 | -- montant de l'horloge |
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| 162 | case etrec is |
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| 163 | when r_wait => |
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| 164 | |
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| 165 | i:=0; |
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| 166 | if fifo_empty='0' and rcv_start='1' then |
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| 167 | |
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| 168 | etrec<=r_head; |
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| 169 | mem<=fifo_out; |
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| 170 | |
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| 171 | end if; |
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| 172 | when r_head => |
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| 173 | mem<=fifo_out; --l'en-tête |
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| 174 | |
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| 175 | etrec<=r_len; |
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| 176 | when r_len => |
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| 177 | dlen:=to_integer(unsigned(fifo_out)); |
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| 178 | mem<=fifo_out; -- la longueur |
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| 179 | |
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| 180 | if dlen>2 then |
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| 181 | etrec<=r_data; |
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| 182 | else |
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| 183 | etrec<=r_end; |
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| 184 | end if; |
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| 185 | i:=1; |
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| 186 | |
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| 187 | when r_data => |
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| 188 | if fifo_empty='0' then |
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| 189 | if i<dlen-2 then |
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| 190 | i:=i+1; |
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| 191 | mem<=fifo_out; |
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| 192 | |
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| 193 | |
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| 194 | else |
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| 195 | etrec<=r_pulse; |
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| 196 | |
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| 197 | mem<=fifo_out; |
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| 198 | end if; |
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| 199 | -- time out à prévoir ici |
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| 200 | end if; |
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| 201 | when r_pulse => |
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| 202 | etrec<=r_end; |
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| 203 | |
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| 204 | when r_end => |
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| 205 | if rcv_ack='1' then |
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| 206 | etrec<=r_wait; |
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| 207 | end if; |
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| 208 | |
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| 209 | when others => |
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| 210 | |
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| 211 | |
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| 212 | etrec<=r_wait; |
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| 213 | end case; |
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| 214 | end if; |
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| 215 | end if; |
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| 216 | end process; |
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| 217 | |
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| 218 | pop<=spop; |
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| 219 | |
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| 220 | rec_value : process (etrec) |
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| 221 | begin |
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| 222 | case etrec is |
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| 223 | when r_wait => |
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| 224 | spop<='0'; |
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| 225 | rcv_comp<='0'; |
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| 226 | when r_head => |
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| 227 | |
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| 228 | spop<='1'; |
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| 229 | rcv_comp<='0'; |
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| 230 | |
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| 231 | when r_len => |
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| 232 | spop<='1'; |
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| 233 | when r_data => |
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| 234 | spop<='1'; |
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| 235 | when r_pulse => |
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| 236 | spop<='0'; |
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| 237 | rcv_comp<='1'; |
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| 238 | when r_end => |
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| 239 | spop<='0'; |
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| 240 | rcv_comp<='1'; |
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| 241 | when others => |
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| 242 | spop<='0'; |
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| 243 | rcv_comp<='0'; |
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| 244 | end case; |
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| 245 | end process; |
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| 246 | |
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| 247 | end Behavioral_description; |
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| 248 | |
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