source: PROJECT_CORE_MPI/MPI_HCL/TRUNK/NOC/SCHEDULER2_2.VHD

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-- Company: 
-- Engineer: KIEGAING EMMANUEL GEL EN 5
-- 
-- Create Date:    03:56:34 05/06/2011 
-- Design Name: 
-- Module Name:    Sheduler - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: Module de l'ordonnanceur du switch crossbar
-- l'algorithme utilisée est le DPA (diagonal propagation arbiter)
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
--use Work.Sheduler_package.all;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity Scheduler2_2 is
    Port ( Request : in  STD_LOGIC_VECTOR (4 downto 1);
                   Fifo_full : in STD_LOGIC_VECTOR (2 downto 1);
           clk : in  STD_LOGIC;
           reset : in  STD_LOGIC;
            priority_rotation : in  STD_LOGIC_VECTOR (2 downto 1);
           port_grant : out  STD_LOGIC_VECTOR (4 downto 1));
end Scheduler2_2;

architecture Behavioral of Scheduler2_2 is
--Declaration du types
--tableau de signaux de connexion des cellules arbitres
TYPE C_Bar_Signal_Array IS ARRAY(3 downto 1) of STD_LOGIC_VECTOR(2 downto 1);
-- declaration du composant cellule d'arbitrage
Component Arbiter 
  PORT (P, Fifo_full,Request, West,North : in  STD_LOGIC;
        Grant,East,South : out  STD_LOGIC );
End Component;--Signaux de connexion des cellues
SIGNAL south_2_north :  C_Bar_Signal_Array; -- connexion south north 
SIGNAL east_2_west   :  C_Bar_Signal_Array; -- connexion east west 
SIGNAL Signal_mask      : C_Bar_Signal_Array;-- connexion des masques de priorité
SIGNAL Signal_grant     : C_Bar_Signal_Array;-- connexion des signaux de validation
SIGNAL Signal_priority  : STD_LOGIC_VECTOR (3 DOWNTO 1);--signal pour la connection des vecteur de priorité
SIGNAL High         : std_logic;--niveau pour les cellules des extremités nord et ouest 
 signal grant_latch : std_logic_vector(4 downto 1); 
 signal priority_rotation_en : std_logic; 
 signal Grant ,req_grant :  std_logic_vector(4 downto 1);
 begin

--validation de la rotation de priorité lorsque aucun port n'emet 
 req_grant<=(request and grant_latch);
 priority_rotation_en <= '1' when unsigned(req_grant) = 0 or unsigned(priority_rotation) = 3 else       '0'; 
--latch servant qui memorise le signal grant pendant a transmission 
grant_latch_process : process(clk)
 begin 
  if rising_edge(clk) then 
   if reset = '1' then 
                grant_latch <= (others => '0'); 
         elsif priority_rotation_en = '1' then 
           grant_latch <= Grant; 
   end if; 
   end if; 
 end process; 
 port_grant <= grant_latch; 
 Grant(1)  <= Signal_grant(1)(1) or Signal_grant(3)(1); --  Grant(1,1)
Grant(2)  <= Signal_grant(2)(2) ;                      --  Grant(1,2)
Grant(3)  <= Signal_grant(2)(1) ;                      --  Grant(2,1)
Grant(4)  <= Signal_grant(1)(2) or Signal_grant(3)(2); --  Grant(2,2)
High <= '1';

----instantiations des cellules arbitres et interconnection

-------------------------- Diagonale n° 1 


Arbiter_1_1 : Arbiter

PORT MAP (Request => Request(1), North => High, West => High, P => Signal_priority(3), Fifo_full => Fifo_full(1),  
South => south_2_north(1)(1), East => east_2_west(1)(1) , Grant => Signal_grant(1)(1)); 

Arbiter_1_2 : Arbiter

PORT MAP (Request => Request(4), North => High, West => High, P => Signal_priority(3), Fifo_full => Fifo_full(2),  
South => south_2_north(1)(2), East => east_2_west(1)(2) , Grant => Signal_grant(1)(2)); 

-------------------------- Diagonale n° 2 


Arbiter_2_1 : Arbiter

PORT MAP (Request => Request(3), North => south_2_north(1)(1), West => east_2_west(1)(2), P => Signal_priority(2), Fifo_full => Fifo_full(1),  
South => south_2_north(2)(1), East => east_2_west(2)(1) , Grant => Signal_grant(2)(1)); 

Arbiter_2_2 : Arbiter

PORT MAP (Request => Request(2), North => south_2_north(1)(2), West => east_2_west(1)(1), P => Signal_priority(2), Fifo_full => Fifo_full(2),  
South => south_2_north(2)(2), East => east_2_west(2)(2) , Grant => Signal_grant(2)(2)); 

-------------------------- Diagonale n° 3 


Arbiter_3_1 : Arbiter

PORT MAP (Request => Request(1), North => south_2_north(2)(1), West => east_2_west(2)(2), P => Signal_priority(1), Fifo_full => Fifo_full(1),  
South => south_2_north(3)(1), East => east_2_west(3)(1) , Grant => Signal_grant(3)(1)); 

Arbiter_3_2 : Arbiter

PORT MAP (Request => Request(4), North => south_2_north(2)(2), West => east_2_west(2)(1), P => Signal_priority(1), Fifo_full => Fifo_full(2),  
South => south_2_north(3)(2), East => east_2_west(3)(2) , Grant => Signal_grant(3)(2)); 


--processus permettant de roter la priorité des diagonales à chaque front d'horloge
 -- rotation round robin
         round_robin : process(clk)
        begin
                if rising_edge(clk) then
                 if reset ='1' then
                    Signal_priority <= "110";
                  elsif priority_rotation_en = '1' then 
                    case Signal_priority is
                       when "110" => Signal_priority <= "011";
                       when "011" => Signal_priority <= "110";
                       when others    => Signal_priority <= "110";
                  end case;
                 end if;
             end if;
         end process;

end Behavioral;