[101] | 1 | --------------------------------------------------------------------------------- |
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| 2 | -- Company: |
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| 3 | -- Engineer: KIEGAING EMMANUEL GEL EN 5 |
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| 4 | -- |
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| 5 | -- Create Date: 03:56:34 05/06/2011 |
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| 6 | -- Design Name: |
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| 7 | -- Module Name: Sheduler - Behavioral |
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| 8 | -- Project Name: |
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| 9 | -- Target Devices: |
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| 10 | -- Tool versions: |
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| 11 | -- Description: Module de l'ordonnanceur du switch crossbar |
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| 12 | -- l'algorithme utilisée est le DPA (diagonal propagation arbiter) |
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| 13 | -- |
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| 14 | -- Dependencies: |
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| 15 | -- |
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| 16 | -- Revision: |
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| 17 | -- Revision 0.01 - File Created |
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| 18 | -- Additional Comments: |
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| 19 | -- |
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| 20 | ---------------------------------------------------------------------------------- |
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| 21 | library IEEE; |
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| 22 | use IEEE.STD_LOGIC_1164.ALL; |
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| 23 | use IEEE.STD_LOGIC_ARITH.ALL; |
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| 24 | use IEEE.STD_LOGIC_UNSIGNED.ALL; |
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| 25 | --use Work.Sheduler_package.all; |
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| 26 | |
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| 27 | ---- Uncomment the following library declaration if instantiating |
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| 28 | ---- any Xilinx primitives in this code. |
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| 29 | --library UNISIM; |
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| 30 | --use UNISIM.VComponents.all; |
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| 31 | entity Scheduler4_4 is |
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| 32 | Port ( Req : in STD_LOGIC_VECTOR (16 downto 1); |
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| 33 | Fifo_full : in STD_LOGIC_VECTOR (4 downto 1); |
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| 34 | clk : in STD_LOGIC; |
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| 35 | reset : in STD_LOGIC; |
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| 36 | priority_rotation : in STD_LOGIC_VECTOR (4 downto 1); |
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| 37 | port_grant : out STD_LOGIC_VECTOR (16 downto 1)); |
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| 38 | end Scheduler4_4; |
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| 39 | |
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| 40 | architecture Behavioral of Scheduler4_4 is |
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| 41 | --déclaration de constantes |
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| 42 | Constant NB_IO : positive:=4; --le nombre de ports d'entrée/sortie |
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| 43 | --Declaration du types |
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| 44 | --tableau de signaux de connexion des cellules arbitres |
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| 45 | TYPE C_Bar_Signal_Array IS ARRAY(7 downto 1) of STD_LOGIC_VECTOR(NB_IO downto 1); |
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| 46 | -- declaration du composant cellule d'arbitrage |
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| 47 | Component Arbiter |
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| 48 | PORT (P, Fifo_full,Request, West,North : in STD_LOGIC; |
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| 49 | Grant,East,South : out STD_LOGIC ); |
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| 50 | End Component;--Signaux de connexion des cellues |
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| 51 | |
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| 52 | constant NB_IO2 :positive:=NB_IO**2; -- le carré du nombre de ports d'E/S |
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| 53 | |
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| 54 | SIGNAL south_2_north : C_Bar_Signal_Array; -- connexion south north |
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| 55 | SIGNAL east_2_west : C_Bar_Signal_Array; -- connexion east west |
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| 56 | SIGNAL Signal_mask : C_Bar_Signal_Array;-- connexion des masques de priorité |
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| 57 | SIGNAL Signal_grant : C_Bar_Signal_Array;-- connexion des signaux de validation |
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| 58 | SIGNAL Signal_priority : STD_LOGIC_VECTOR (7 DOWNTO 1);--signal pour la connection des vecteur de priorité |
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| 59 | SIGNAL High : std_logic;--niveau pour les cellules des extremités nord et ouest |
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| 60 | Signal Fifo_out_full : STD_LOGIC_VECTOR (NB_IO downto 1); |
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| 61 | signal grant_latch : std_logic_vector(NB_IO2 downto 1); |
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| 62 | signal priority_rotation_en : std_logic; |
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| 63 | signal Grant,request,req_grant,Grant_bak : std_logic_vector(NB_IO2 downto 1):=(others=>'0'); |
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| 64 | signal Mreq : std_logic_vector(NB_IO2 downto 1):=(others=>'1'); |
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| 65 | |
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| 66 | begin |
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| 67 | |
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| 68 | --validation de la rotation de priorité lorsque aucun port n'emet |
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| 69 | req_grant<=(req and grant ); |
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| 70 | priority_rotation_en <= '1' when unsigned(priority_rotation) = 2**NB_IO-1 else '0'; |
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| 71 | request<=req and mreq; |
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| 72 | --latch qui memorise le signal grant pendant la transmission |
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| 73 | grant_latch_process : process(clk) |
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| 74 | begin |
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| 75 | if rising_edge(clk) then |
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| 76 | if reset = '1' then |
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| 77 | grant_latch <= (others => '0'); |
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| 78 | Fifo_out_full<=(others => '0'); |
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| 79 | elsif priority_rotation_en = '1' or unsigned(req_grant)=0 then |
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| 80 | grant_latch <= Grant; |
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| 81 | Fifo_out_full<=fifo_full; |
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| 82 | else |
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| 83 | grant_latch <= Grant; |
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| 84 | Fifo_out_full<=fifo_full; |
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| 85 | end if; |
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| 86 | end if; |
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| 87 | |
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| 88 | end process; |
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| 89 | def_mreq: process(grant_latch,fifo_full) |
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| 90 | |
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| 91 | variable t:std_logic_vector(NB_IO2 downto 1):=(others=>'0'); |
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| 92 | begin |
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| 93 | |
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| 94 | for i in 0 to NB_IO2-1 loop |
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| 95 | t(i+1):='0'; |
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| 96 | --sur le front montant de fifo_full sauver l'état Grant courant |
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| 97 | if fifo_full(i mod NB_IO+1)='1' and fifo_out_full(i mod NB_IO+1)='0' then |
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| 98 | Grant_bak(i+1)<= grant_latch(i+1); |
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| 99 | elsif fifo_full(i mod NB_IO+1)='0' and fifo_out_full(i mod NB_IO+1)='0' then |
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| 100 | Grant_bak(i+1)<='0'; |
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| 101 | end if; |
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| 102 | for j in 0 to NB_IO-1 loop |
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| 103 | t(i+1):=t(i+1) or grant_latch(j*NB_IO+1+i mod NB_IO) or fifo_out_full(i mod NB_IO+1); |
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| 104 | |
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| 105 | end loop; |
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| 106 | mreq(i+1)<=not(t(i+1) ) or grant_latch(i+1)or grant_bak(i+1); |
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| 107 | end loop; |
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| 108 | end process; |
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| 109 | port_grant <= grant; |
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| 110 | Grant(1) <= Signal_grant(1)(1) or Signal_grant(5)(1); -- Grant(1,1) |
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| 111 | Grant(2) <= Signal_grant(2)(2) or Signal_grant(6)(2); -- Grant(1,2) |
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| 112 | Grant(3) <= Signal_grant(3)(3) or Signal_grant(7)(3); -- Grant(1,3) |
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| 113 | Grant(4) <= Signal_grant(4)(4) ; -- Grant(1,4) |
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| 114 | Grant(5) <= Signal_grant(2)(1) or Signal_grant(6)(1); -- Grant(2,1) |
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| 115 | Grant(6) <= Signal_grant(3)(2) or Signal_grant(7)(2); -- Grant(2,2) |
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| 116 | Grant(7) <= Signal_grant(4)(3) ; -- Grant(2,3) |
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| 117 | Grant(8) <= Signal_grant(1)(4) or Signal_grant(5)(4); -- Grant(2,4) |
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| 118 | Grant(9) <= Signal_grant(3)(1) or Signal_grant(7)(1); -- Grant(3,1) |
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| 119 | Grant(10) <= Signal_grant(4)(2) ; -- Grant(3,2) |
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| 120 | Grant(11) <= Signal_grant(1)(3) or Signal_grant(5)(3); -- Grant(3,3) |
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| 121 | Grant(12) <= Signal_grant(2)(4) or Signal_grant(6)(4); -- Grant(3,4) |
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| 122 | Grant(13) <= Signal_grant(4)(1) ; -- Grant(4,1) |
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| 123 | Grant(14) <= Signal_grant(1)(2) or Signal_grant(5)(2); -- Grant(4,2) |
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| 124 | Grant(15) <= Signal_grant(2)(3) or Signal_grant(6)(3); -- Grant(4,3) |
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| 125 | Grant(16) <= Signal_grant(3)(4) or Signal_grant(7)(4); -- Grant(4,4) |
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| 126 | High <= '1'; |
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| 127 | |
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| 128 | ----instantiations des cellules arbitres et interconnection |
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| 129 | |
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| 130 | -------------------------- Diagonale n° 1 |
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| 131 | |
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| 132 | |
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| 133 | Arbiter_1_1 : Arbiter |
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| 134 | |
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| 135 | PORT MAP (Request => Request(1), North => High, West => High, P => Signal_priority(7), Fifo_full => Fifo_full(1), |
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| 136 | South => south_2_north(1)(1), East => east_2_west(1)(1) , Grant => Signal_grant(1)(1)); |
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| 137 | |
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| 138 | Arbiter_1_2 : Arbiter |
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| 139 | |
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| 140 | PORT MAP (Request => Request(14), North => High, West => High, P => Signal_priority(7), Fifo_full => Fifo_full(2), |
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| 141 | South => south_2_north(1)(2), East => east_2_west(1)(2) , Grant => Signal_grant(1)(2)); |
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| 142 | |
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| 143 | Arbiter_1_3 : Arbiter |
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| 144 | |
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| 145 | PORT MAP (Request => Request(11), North => High, West => High, P => Signal_priority(7), Fifo_full => Fifo_full(3), |
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| 146 | South => south_2_north(1)(3), East => east_2_west(1)(3) , Grant => Signal_grant(1)(3)); |
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| 147 | |
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| 148 | Arbiter_1_4 : Arbiter |
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| 149 | |
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| 150 | PORT MAP (Request => Request(8), North => High, West => High, P => Signal_priority(7), Fifo_full => Fifo_full(4), |
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| 151 | South => south_2_north(1)(4), East => east_2_west(1)(4) , Grant => Signal_grant(1)(4)); |
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| 152 | |
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| 153 | -------------------------- Diagonale n° 2 |
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| 154 | |
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| 155 | |
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| 156 | Arbiter_2_1 : Arbiter |
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| 157 | |
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| 158 | PORT MAP (Request => Request(5), North => south_2_north(1)(1), West => east_2_west(1)(4), P => Signal_priority(6), Fifo_full => Fifo_full(1), |
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| 159 | South => south_2_north(2)(1), East => east_2_west(2)(1) , Grant => Signal_grant(2)(1)); |
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| 160 | |
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| 161 | Arbiter_2_2 : Arbiter |
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| 162 | |
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| 163 | PORT MAP (Request => Request(2), North => south_2_north(1)(2), West => east_2_west(1)(1), P => Signal_priority(6), Fifo_full => Fifo_full(2), |
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| 164 | South => south_2_north(2)(2), East => east_2_west(2)(2) , Grant => Signal_grant(2)(2)); |
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| 165 | |
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| 166 | Arbiter_2_3 : Arbiter |
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| 167 | |
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| 168 | PORT MAP (Request => Request(15), North => south_2_north(1)(3), West => east_2_west(1)(2), P => Signal_priority(6), Fifo_full => Fifo_full(3), |
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| 169 | South => south_2_north(2)(3), East => east_2_west(2)(3) , Grant => Signal_grant(2)(3)); |
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| 170 | |
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| 171 | Arbiter_2_4 : Arbiter |
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| 172 | |
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| 173 | PORT MAP (Request => Request(12), North => south_2_north(1)(4), West => east_2_west(1)(3), P => Signal_priority(6), Fifo_full => Fifo_full(4), |
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| 174 | South => south_2_north(2)(4), East => east_2_west(2)(4) , Grant => Signal_grant(2)(4)); |
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| 175 | |
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| 176 | -------------------------- Diagonale n° 3 |
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| 177 | |
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| 178 | |
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| 179 | Arbiter_3_1 : Arbiter |
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| 180 | |
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| 181 | PORT MAP (Request => Request(9), North => south_2_north(2)(1), West => east_2_west(2)(4), P => Signal_priority(5), Fifo_full => Fifo_full(1), |
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| 182 | South => south_2_north(3)(1), East => east_2_west(3)(1) , Grant => Signal_grant(3)(1)); |
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| 183 | |
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| 184 | Arbiter_3_2 : Arbiter |
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| 185 | |
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| 186 | PORT MAP (Request => Request(6), North => south_2_north(2)(2), West => east_2_west(2)(1), P => Signal_priority(5), Fifo_full => Fifo_full(2), |
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| 187 | South => south_2_north(3)(2), East => east_2_west(3)(2) , Grant => Signal_grant(3)(2)); |
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| 188 | |
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| 189 | Arbiter_3_3 : Arbiter |
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| 190 | |
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| 191 | PORT MAP (Request => Request(3), North => south_2_north(2)(3), West => east_2_west(2)(2), P => Signal_priority(5), Fifo_full => Fifo_full(3), |
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| 192 | South => south_2_north(3)(3), East => east_2_west(3)(3) , Grant => Signal_grant(3)(3)); |
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| 193 | |
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| 194 | Arbiter_3_4 : Arbiter |
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| 195 | |
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| 196 | PORT MAP (Request => Request(16), North => south_2_north(2)(4), West => east_2_west(2)(3), P => Signal_priority(5), Fifo_full => Fifo_full(4), |
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| 197 | South => south_2_north(3)(4), East => east_2_west(3)(4) , Grant => Signal_grant(3)(4)); |
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| 198 | |
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| 199 | -------------------------- Diagonale n° 4 |
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| 200 | |
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| 201 | |
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| 202 | Arbiter_4_1 : Arbiter |
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| 203 | |
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| 204 | PORT MAP (Request => Request(13), North => south_2_north(3)(1), West => east_2_west(3)(4), P => Signal_priority(4), Fifo_full => Fifo_full(1), |
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| 205 | South => south_2_north(4)(1), East => east_2_west(4)(1) , Grant => Signal_grant(4)(1)); |
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| 206 | |
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| 207 | Arbiter_4_2 : Arbiter |
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| 208 | |
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| 209 | PORT MAP (Request => Request(10), North => south_2_north(3)(2), West => east_2_west(3)(1), P => Signal_priority(4), Fifo_full => Fifo_full(2), |
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| 210 | South => south_2_north(4)(2), East => east_2_west(4)(2) , Grant => Signal_grant(4)(2)); |
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| 211 | |
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| 212 | Arbiter_4_3 : Arbiter |
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| 213 | |
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| 214 | PORT MAP (Request => Request(7), North => south_2_north(3)(3), West => east_2_west(3)(2), P => Signal_priority(4), Fifo_full => Fifo_full(3), |
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| 215 | South => south_2_north(4)(3), East => east_2_west(4)(3) , Grant => Signal_grant(4)(3)); |
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| 216 | |
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| 217 | Arbiter_4_4 : Arbiter |
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| 218 | |
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| 219 | PORT MAP (Request => Request(4), North => south_2_north(3)(4), West => east_2_west(3)(3), P => Signal_priority(4), Fifo_full => Fifo_full(4), |
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| 220 | South => south_2_north(4)(4), East => east_2_west(4)(4) , Grant => Signal_grant(4)(4)); |
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| 221 | |
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| 222 | -------------------------- Diagonale n° 5 |
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| 223 | |
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| 224 | |
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| 225 | Arbiter_5_1 : Arbiter |
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| 226 | |
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| 227 | PORT MAP (Request => Request(1), North => south_2_north(4)(1), West => east_2_west(4)(4), P => Signal_priority(3), Fifo_full => Fifo_full(1), |
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| 228 | South => south_2_north(5)(1), East => east_2_west(5)(1) , Grant => Signal_grant(5)(1)); |
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| 229 | |
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| 230 | Arbiter_5_2 : Arbiter |
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| 231 | |
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| 232 | PORT MAP (Request => Request(14), North => south_2_north(4)(2), West => east_2_west(4)(1), P => Signal_priority(3), Fifo_full => Fifo_full(2), |
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| 233 | South => south_2_north(5)(2), East => east_2_west(5)(2) , Grant => Signal_grant(5)(2)); |
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| 234 | |
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| 235 | Arbiter_5_3 : Arbiter |
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| 236 | |
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| 237 | PORT MAP (Request => Request(11), North => south_2_north(4)(3), West => east_2_west(4)(2), P => Signal_priority(3), Fifo_full => Fifo_full(3), |
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| 238 | South => south_2_north(5)(3), East => east_2_west(5)(3) , Grant => Signal_grant(5)(3)); |
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| 239 | |
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| 240 | Arbiter_5_4 : Arbiter |
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| 241 | |
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| 242 | PORT MAP (Request => Request(8), North => south_2_north(4)(4), West => east_2_west(4)(3), P => Signal_priority(3), Fifo_full => Fifo_full(4), |
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| 243 | South => south_2_north(5)(4), East => east_2_west(5)(4) , Grant => Signal_grant(5)(4)); |
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| 244 | |
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| 245 | -------------------------- Diagonale n° 6 |
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| 246 | |
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| 247 | |
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| 248 | Arbiter_6_1 : Arbiter |
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| 249 | |
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| 250 | PORT MAP (Request => Request(5), North => south_2_north(5)(1), West => east_2_west(5)(4), P => Signal_priority(2), Fifo_full => Fifo_full(1), |
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| 251 | South => south_2_north(6)(1), East => east_2_west(6)(1) , Grant => Signal_grant(6)(1)); |
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| 252 | |
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| 253 | Arbiter_6_2 : Arbiter |
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| 254 | |
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| 255 | PORT MAP (Request => Request(2), North => south_2_north(5)(2), West => east_2_west(5)(1), P => Signal_priority(2), Fifo_full => Fifo_full(2), |
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| 256 | South => south_2_north(6)(2), East => east_2_west(6)(2) , Grant => Signal_grant(6)(2)); |
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| 257 | |
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| 258 | Arbiter_6_3 : Arbiter |
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| 259 | |
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| 260 | PORT MAP (Request => Request(15), North => south_2_north(5)(3), West => east_2_west(5)(2), P => Signal_priority(2), Fifo_full => Fifo_full(3), |
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| 261 | South => south_2_north(6)(3), East => east_2_west(6)(3) , Grant => Signal_grant(6)(3)); |
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| 262 | |
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| 263 | Arbiter_6_4 : Arbiter |
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| 264 | |
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| 265 | PORT MAP (Request => Request(12), North => south_2_north(5)(4), West => east_2_west(5)(3), P => Signal_priority(2), Fifo_full => Fifo_full(4), |
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| 266 | South => south_2_north(6)(4), East => east_2_west(6)(4) , Grant => Signal_grant(6)(4)); |
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| 267 | |
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| 268 | -------------------------- Diagonale n° 7 |
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| 269 | |
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| 270 | |
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| 271 | Arbiter_7_1 : Arbiter |
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| 272 | |
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| 273 | PORT MAP (Request => Request(9), North => south_2_north(6)(1), West => east_2_west(6)(4), P => Signal_priority(1), Fifo_full => Fifo_full(1), |
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| 274 | South => south_2_north(7)(1), East => east_2_west(7)(1) , Grant => Signal_grant(7)(1)); |
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| 275 | |
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| 276 | Arbiter_7_2 : Arbiter |
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| 277 | |
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| 278 | PORT MAP (Request => Request(6), North => south_2_north(6)(2), West => east_2_west(6)(1), P => Signal_priority(1), Fifo_full => Fifo_full(2), |
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| 279 | South => south_2_north(7)(2), East => east_2_west(7)(2) , Grant => Signal_grant(7)(2)); |
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| 280 | |
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| 281 | Arbiter_7_3 : Arbiter |
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| 282 | |
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| 283 | PORT MAP (Request => Request(3), North => south_2_north(6)(3), West => east_2_west(6)(2), P => Signal_priority(1), Fifo_full => Fifo_full(3), |
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| 284 | South => south_2_north(7)(3), East => east_2_west(7)(3) , Grant => Signal_grant(7)(3)); |
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| 285 | |
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| 286 | Arbiter_7_4 : Arbiter |
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| 287 | |
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| 288 | PORT MAP (Request => Request(16), North => south_2_north(6)(4), West => east_2_west(6)(3), P => Signal_priority(1), Fifo_full => Fifo_full(4), |
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| 289 | South => south_2_north(7)(4), East => east_2_west(7)(4) , Grant => Signal_grant(7)(4)); |
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| 290 | |
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| 291 | |
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| 292 | --processus permettant de roter la priorité des diagonales à chaque front d'horloge |
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| 293 | -- rotation round robin |
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| 294 | round_robin : process(clk) |
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| 295 | begin |
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| 296 | if rising_edge(clk) then |
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| 297 | if reset ='1' then |
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| 298 | Signal_priority <= "1111000"; |
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| 299 | elsif priority_rotation_en = '1' then |
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| 300 | case Signal_priority is |
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| 301 | when "1111000" => Signal_priority <= "0111100"; |
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| 302 | when "0111100" => Signal_priority <= "0011110"; |
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| 303 | when "0011110" => Signal_priority <= "0001111"; |
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| 304 | when "0001111" => Signal_priority <= "1111000"; |
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| 305 | when others => Signal_priority <= "1111000"; |
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| 306 | end case; |
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| 307 | end if; |
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| 308 | end if; |
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| 309 | end process; |
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| 310 | |
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| 311 | end Behavioral; |
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| 312 | |
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