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SWITCH_GEN.vhd @ 101

Last change on this file since 101 was 101, checked in by rolagamo, 10 years ago

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1	----------------------------------------------------------------------------------
2	-- Company: ENSET 2011
3	-- Engineer: GAMOM NGOUNOU
4	--
5	-- Create Date: 03:40:47 11/19/2011
6	-- Design Name:
7	-- Module Name: SWITCH_GEN - Behavioral
8	-- Project Name:
9	-- Target Devices:
10	-- Tool versions:
11	-- Description:
12	-- fichier principal du switch générique; en fonction du parametre generique le
13	-- les directive de generation conditionnelle permettent de ne générer et synthétiser uniquement la logique
14	-- nécessaire à l'implémentation du switch de la dimension voulue
15	-- Dependencies:
16	--
17	-- Revision:
18	-- Revision 0.01 - File Created
19	-- Additional Comments:
20	--
21	----------------------------------------------------------------------------------
22	library IEEE;
23	use IEEE.STD_LOGIC_1164.ALL;
24	use IEEE.STD_LOGIC_ARITH.ALL;
25	use IEEE.STD_LOGIC_UNSIGNED.ALL;
26	use work.Coretypes.all ;
27	---- Uncomment the following library declaration if instantiating
28	---- any Xilinx primitives in this code.
29	--library UNISIM;
30	--use UNISIM.VComponents.all;
31
32	entity SWITCH_GEN is
33	--type portio is array(positive range) of std_logic_vector (7 downto 0);
34	generic(number_of_ports : positive := 8);
35	port(
36	-- ports d'entree
37	Port_in : in typ_portIO(1 to number_of_ports) ;
38
39
40	-- port de sortie
41	Port_out : out typ_portIO(1 to number_of_ports);
42
43	-- signaux de controle
44	data_in_en : in std_logic_vector(number_of_ports downto 1);
45	cmd_in_en : in std_logic_vector(number_of_ports downto 1);
46	data_out_en : in std_logic_vector(number_of_ports downto 1);
47	fifo_in_full : out std_logic_vector(number_of_ports downto 1);
48	fifo_in_empty : out std_logic_vector(number_of_ports downto 1);
49	data_available : out std_logic_vector(number_of_ports downto 1);
50	clk : in STD_LOGIC;
51	reset : in STD_LOGIC);
52	end SWITCH_GEN;
53
54	architecture Behavioral of SWITCH_GEN is
55	-- declaration des modules du switch generique
56	-- le module de gestion des ports d'entrée
57
58	COMPONENT INPUT_PORT_MODULE
59	generic(number_of_ports : positive := 8;
60	Port_num: natural);
61	Port ( data_in : in STD_LOGIC_VECTOR (7 downto 0);
62	data_in_en : in STD_LOGIC;
63	cmd_in_en : in STD_LOGIC;
64	reset : in STD_LOGIC;
65	clk : in STD_LOGIC;
66	request : out STD_LOGIC_VECTOR (number_of_ports downto 1);
67	grant : in STD_LOGIC_VECTOR (number_of_ports downto 1);
68	fifo_full : out STD_LOGIC;
69	fifo_empty : out STD_LOGIC;
70	priority_rotation : out std_logic;
71	data_out : out STD_LOGIC_VECTOR (7 downto 0);
72	data_out_pulse : out std_logic);
73	END COMPONENT;
74
75	-- le module des ports de sortie
76
77	COMPONENT OUTPUT_PORT_MODULE
78	PORT(
79	data_in : IN std_logic_vector(7 downto 0);
80	reset : IN std_logic;
81	clk : IN std_logic;
82	wr_en : IN std_logic;
83	rd_out_en : IN std_logic;
84	data_out : OUT std_logic_vector(7 downto 0);
85	fifo_full : OUT std_logic;
86	data_avalaible : OUT std_logic
87	);
88	END COMPONENT;
89
90	-- le module du crossbar
91	COMPONENT Crossbar
92	generic
93	(
94	number_of_crossbar_ports: positive := 4
95	);
96	Port (
97	clk : in STD_LOGIC;
98	reset : in STD_LOGIC;
99	Port1_in : in STD_LOGIC_VECTOR (7 downto 0);
100	Port2_in : in STD_LOGIC_VECTOR (7 downto 0);
101	Port3_in : in STD_LOGIC_VECTOR (7 downto 0);
102	Port4_in : in STD_LOGIC_VECTOR (7 downto 0);
103	Port5_in : in STD_LOGIC_VECTOR (7 downto 0);
104	Port6_in : in STD_LOGIC_VECTOR (7 downto 0);
105	Port7_in : in STD_LOGIC_VECTOR (7 downto 0);
106	Port8_in : in STD_LOGIC_VECTOR (7 downto 0);
107	Port9_in : in STD_LOGIC_VECTOR (7 downto 0);
108	Port10_in : in STD_LOGIC_VECTOR (7 downto 0);
109	Port11_in : in STD_LOGIC_VECTOR (7 downto 0);
110	Port12_in : in STD_LOGIC_VECTOR (7 downto 0);
111	Port13_in : in STD_LOGIC_VECTOR (7 downto 0);
112	Port14_in : in STD_LOGIC_VECTOR (7 downto 0);
113	Port15_in : in STD_LOGIC_VECTOR (7 downto 0);
114	Port16_in : in STD_LOGIC_VECTOR (7 downto 0);
115
116	--Port_pulse_in : in std_logic_vector(1 to number_of_ports);
117	Port1_pulse_in : in std_logic;
118	Port2_pulse_in : in std_logic;
119	Port3_pulse_in : in std_logic;
120	Port4_pulse_in : in std_logic;
121	Port5_pulse_in : in std_logic;
122	Port6_pulse_in : in std_logic;
123	Port7_pulse_in : in std_logic;
124	Port8_pulse_in : in std_logic;
125	Port9_pulse_in : in std_logic;
126	Port10_pulse_in : in std_logic;
127	Port11_pulse_in : in std_logic;
128	Port12_pulse_in : in std_logic;
129	Port13_pulse_in : in std_logic;
130	Port14_pulse_in : in std_logic;
131	Port15_pulse_in : in std_logic;
132	Port16_pulse_in : in std_logic;
133
134	--Port_pulse_out : in std_logic_vector(1 to number_of_ports);
135	Port1_pulse_out : out std_logic;
136	Port2_pulse_out : out std_logic;
137	Port3_pulse_out : out std_logic;
138	Port4_pulse_out : out std_logic;
139	Port5_pulse_out : out std_logic;
140	Port6_pulse_out : out std_logic;
141	Port7_pulse_out : out std_logic;
142	Port8_pulse_out : out std_logic;
143	Port9_pulse_out : out std_logic;
144	Port10_pulse_out : out std_logic;
145	Port11_pulse_out : out std_logic;
146	Port12_pulse_out : out std_logic;
147	Port13_pulse_out : out std_logic;
148	Port14_pulse_out : out std_logic;
149	Port15_pulse_out : out std_logic;
150	Port16_pulse_out : out std_logic;
151
152	--Port_out : out Typ_PortIO(1 to number_of_crossbar_ports);
153	Port1_out : out STD_LOGIC_VECTOR (7 downto 0);
154	Port2_out : out STD_LOGIC_VECTOR (7 downto 0);
155	Port3_out : out STD_LOGIC_VECTOR (7 downto 0);
156	Port4_out : out STD_LOGIC_VECTOR (7 downto 0);
157	Port5_out : out STD_LOGIC_VECTOR (7 downto 0);
158	Port6_out : out STD_LOGIC_VECTOR (7 downto 0);
159	Port7_out : out STD_LOGIC_VECTOR (7 downto 0);
160	Port8_out : out STD_LOGIC_VECTOR (7 downto 0);
161	Port9_out : out STD_LOGIC_VECTOR (7 downto 0);
162	Port10_out : out STD_LOGIC_VECTOR (7 downto 0);
163	Port11_out : out STD_LOGIC_VECTOR (7 downto 0);
164	Port12_out : out STD_LOGIC_VECTOR (7 downto 0);
165	Port13_out : out STD_LOGIC_VECTOR (7 downto 0);
166	Port14_out : out STD_LOGIC_VECTOR (7 downto 0);
167	Port15_out : out STD_LOGIC_VECTOR (7 downto 0);
168	Port16_out : out STD_LOGIC_VECTOR (7 downto 0);
169
170	Ctrl : in STD_LOGIC_VECTOR (number_of_crossbar_ports*number_of_crossbar_ports downto 1)
171	);
172	END COMPONENT;
173
174	-- déclaration du scheduler
175	COMPONENT Scheduler
176	generic(number_of_ports : positive := 4);
177	Port ( Request : in STD_LOGIC_VECTOR (number_of_ports*number_of_ports downto 1);
178	Fifo_full : in STD_LOGIC_VECTOR (number_of_ports downto 1);
179	clk : in STD_LOGIC;
180	reset : in STD_LOGIC;
181	priority_rotation : in STD_LOGIC_VECTOR (number_of_ports downto 1);
182	port_grant : out STD_LOGIC_VECTOR (number_of_ports*number_of_ports downto 1));
183	END COMPONENT;
184
185	--declaration des signaux de connection entre les modules du switch
186
187	Signal Request_signal : STD_LOGIC_VECTOR(number_of_ports*number_of_ports downto 1);
188	Signal grant_signal : STD_LOGIC_VECTOR(number_of_ports*number_of_ports downto 1);
189	Signal priority_rotation_signal : STD_LOGIC_VECTOR(number_of_ports downto 1);
190	signal fifo_out_full_signal : std_logic_vector(number_of_ports downto 1);
191
192	signal crossbar_in_port : Typ_PortIO(1 to number_of_ports);
193
194
195
196	signal crossbar_out_port : Typ_PortIO(1 to number_of_ports);
197
198
199	signal crossbar_in_pulse : std_logic_vector(number_of_ports downto 1);
200
201
202	signal crossbar_out_pulse : std_logic_vector(number_of_ports downto 1);
203
204
205
206	begin
207	-- intstanciation et connexion des modules du switch en fonction du nombre de ports
208	-- le circuit genere depend du parametre generique nombre de ports
209	-- switch 2 ports
210	switch2x2 : if number_of_ports = 2 generate
211
212	PORT1_INPUT_PORT_MODULE: INPUT_PORT_MODULE
213	GENERIC MAP(number_of_ports =>2,Port_num=>1)
214	PORT MAP(
215	data_in => Port_in(1),
216	data_in_en => data_in_en(1),
217	cmd_in_en => cmd_in_en(1),
218	reset => reset,
219	clk =>clk,
220	grant(1) => grant_signal(1),
221	grant(2) => grant_signal(2),
222	fifo_full =>fifo_in_full(1),
223	priority_rotation => priority_rotation_signal(1),
224	fifo_empty => fifo_in_empty(1),
225	data_out =>crossbar_in_port(1),
226	data_out_pulse =>crossbar_in_pulse(1),
227	request(1) =>request_signal(1),
228	request(2) =>request_signal(2)
229	);
230
231	PORT2_INPUT_PORT_MODULE: INPUT_PORT_MODULE
232	GENERIC MAP(number_of_ports =>2,Port_num=>2)
233	PORT MAP(
234	data_in => Port_in(2),
235	data_in_en => data_in_en(2),
236	cmd_in_en => cmd_in_en(2),
237	reset => reset,
238	clk =>clk,
239	grant(1) => grant_signal(3),
240	grant(2) => grant_signal(4),
241	fifo_full =>fifo_in_full(2),
242	priority_rotation => priority_rotation_signal(2),
243	fifo_empty => fifo_in_empty(2),
244	data_out =>crossbar_in_port(2),
245	data_out_pulse =>crossbar_in_pulse(2),
246	request(1) =>request_signal(3),
247	request(2) =>request_signal(4)
248	);
249
250	end generate switch2x2;
251
252
253	-- switch 3 ports
254	switch3x3 : if number_of_ports = 3 generate
255
256	PORT1_INPUT_PORT_MODULE: INPUT_PORT_MODULE
257	GENERIC MAP(number_of_ports =>3,Port_num=>1)
258	PORT MAP(
259	data_in => Port_in(1),
260	data_in_en => data_in_en(1),
261	cmd_in_en => cmd_in_en(1),
262	reset => reset,
263	clk =>clk,
264	grant(1) => grant_signal(1),
265	grant(2) => grant_signal(2),
266	grant(3) => grant_signal(3),
267	fifo_full =>fifo_in_full(1),
268	priority_rotation => priority_rotation_signal(1),
269	fifo_empty => fifo_in_empty(1),
270	data_out =>crossbar_in_port(1),
271	data_out_pulse =>crossbar_in_pulse(1),
272	request(1) =>request_signal(1),
273	request(2) =>request_signal(2),
274	request(3) =>request_signal(3)
275	);
276
277	PORT2_INPUT_PORT_MODULE: INPUT_PORT_MODULE
278	GENERIC MAP(number_of_ports =>3,Port_num=>2)
279	PORT MAP(
280	data_in => Port_in(2),
281	data_in_en => data_in_en(2),
282	cmd_in_en => cmd_in_en(2),
283	reset => reset,
284	clk =>clk,
285	grant(4) => grant_signal(4),
286	grant(5) => grant_signal(5),
287	grant(6) => grant_signal(6),
288	fifo_full =>fifo_in_full(2),
289	priority_rotation => priority_rotation_signal(2),
290	fifo_empty => fifo_in_empty(2),
291	data_out =>crossbar_in_port(2),
292	data_out_pulse =>crossbar_in_pulse(2),
293	request(4) =>request_signal(4),
294	request(5) =>request_signal(5),
295	request(6) =>request_signal(6)
296	);
297
298	PORT3_INPUT_PORT_MODULE: INPUT_PORT_MODULE
299	GENERIC MAP(number_of_ports =>3,Port_num=>3)
300	PORT MAP(
301	data_in => Port_in(3),
302	data_in_en => data_in_en(3),
303	cmd_in_en => cmd_in_en(3),
304	reset => reset,
305	clk =>clk,
306	grant(7) => grant_signal(7),
307	grant(8) => grant_signal(8),
308	grant(9) => grant_signal(9),
309	fifo_full =>fifo_in_full(3),
310	priority_rotation => priority_rotation_signal(3),
311	fifo_empty => fifo_in_empty(3),
312	data_out =>crossbar_in_port(3),
313	data_out_pulse =>crossbar_in_pulse(3),
314	request(7) =>request_signal(7),
315	request(8) =>request_signal(8),
316	request(9) =>request_signal(9)
317	);
318
319	end generate switch3x3;
320
321
322	-- switch 4 à 7 ports
323	switch4x4_7x7 : if number_of_ports >= 4 and number_of_ports <=7 generate
324
325	switch_4x4_7x7:for i in 1 to number_of_ports generate
326
327	constant j: natural:=number_of_ports*(i-1);
328	begin
329	--j=number_of_ports*(i-1);
330	PORTx4_INPUT_PORT_MODULE: INPUT_PORT_MODULE
331	GENERIC MAP(number_of_ports =>number_of_ports,Port_num=>i)
332	PORT MAP(
333	data_in => Port_in(i),
334	data_in_en => data_in_en(i),
335	cmd_in_en => cmd_in_en(i),
336	reset => reset,
337	clk =>clk,
338	grant =>grant_signal(j+NUMBER_OF_PORTS downto j+1),
339
340	fifo_full =>fifo_in_full(i),
341	priority_rotation => priority_rotation_signal(i),
342	fifo_empty => fifo_in_empty(i),
343	data_out =>crossbar_in_port(i),
344	data_out_pulse =>crossbar_in_pulse(i),
345	request =>request_signal(j+NUMBER_OF_PORTS downto j+1)
346
347	);
348	end generate switch_4x4_7x7;
349	end generate switch4x4_7x7;
350
351
352	---- switch 5 ports
353	--switch5x5 : if number_of_ports = 5 generate
354	--
355	--PORT1_INPUT_PORT_MODULE: INPUT_PORT_MODULE
356	--GENERIC MAP(number_of_ports =>5)
357	--PORT MAP(
358	-- data_in => Port_in(1),
359	-- data_in_en => data_in_en(1),
360	-- reset => reset,
361	-- clk =>clk,
362	-- grant(1) => grant_signal(1),
363	-- grant(2) => grant_signal(2),
364	-- grant(3) => grant_signal(3),
365	-- grant(4) => grant_signal(4),
366	-- grant(5) => grant_signal(5),
367	-- fifo_full =>fifo_in_full(1),
368	-- priority_rotation => priority_rotation_signal(1),
369	-- fifo_empty => fifo_in_empty(1),
370	-- data_out =>crossbar_in_port(1),
371	-- data_out_pulse =>crossbar_in_pulse(1),
372	-- request(1) =>request_signal(1),
373	-- request(2) =>request_signal(2),
374	-- request(3) =>request_signal(3),
375	-- request(4) =>request_signal(4),
376	-- request(5) =>request_signal(5)
377	--);
378	--
379	--PORT2_INPUT_PORT_MODULE: INPUT_PORT_MODULE
380	--GENERIC MAP(number_of_ports =>5)
381	--PORT MAP(
382	-- data_in => Port_in(2),
383	-- data_in_en => data_in_en(2),
384	-- reset => reset,
385	-- clk =>clk,
386	-- grant(1) => grant_signal(6),
387	-- grant(2) => grant_signal(7),
388	-- grant(3) => grant_signal(8),
389	-- grant(4) => grant_signal(9),
390	-- grant(5) => grant_signal(10),
391	-- fifo_full =>fifo_in_full(2),
392	-- priority_rotation => priority_rotation_signal(2),
393	-- fifo_empty => fifo_in_empty(2),
394	-- data_out =>crossbar_in_port(2),
395	-- data_out_pulse =>crossbar_in_pulse(2),
396	-- request(6) =>request_signal(6),
397	-- request(7) =>request_signal(7),
398	-- request(8) =>request_signal(8),
399	-- request(9) =>request_signal(9),
400	-- request(10) =>request_signal(10)
401	--);
402	--
403	--PORT3_INPUT_PORT_MODULE: INPUT_PORT_MODULE
404	--GENERIC MAP(number_of_ports =>5)
405	--PORT MAP(
406	-- data_in => Port_in(3),
407	-- data_in_en => data_in_en(3),
408	-- reset => reset,
409	-- clk =>clk,
410	-- grant(11) => grant_signal(11),
411	-- grant(12) => grant_signal(12),
412	-- grant(13) => grant_signal(13),
413	-- grant(14) => grant_signal(14),
414	-- grant(15) => grant_signal(15),
415	-- fifo_full =>fifo_in_full(3),
416	-- priority_rotation => priority_rotation_signal(3),
417	-- fifo_empty => fifo_in_empty(3),
418	-- data_out =>crossbar_in_port(3),
419	-- data_out_pulse =>crossbar_in_pulse(3),
420	-- request(11) =>request_signal(11),
421	-- request(12) =>request_signal(12),
422	-- request(13) =>request_signal(13),
423	-- request(14) =>request_signal(14),
424	-- request(15) =>request_signal(15)
425	--);
426	--
427	--PORT4_INPUT_PORT_MODULE: INPUT_PORT_MODULE
428	--GENERIC MAP(number_of_ports =>5)
429	--PORT MAP(
430	-- data_in => Port_in(4),
431	-- data_in_en => data_in_en(4),
432	-- reset => reset,
433	-- clk =>clk,
434	-- grant(16) => grant_signal(16),
435	-- grant(17) => grant_signal(17),
436	-- grant(18) => grant_signal(18),
437	-- grant(19) => grant_signal(19),
438	-- grant(20) => grant_signal(20),
439	-- fifo_full =>fifo_in_full(4),
440	-- priority_rotation => priority_rotation_signal(4),
441	-- fifo_empty => fifo_in_empty(4),
442	-- data_out =>crossbar_in_port(4),
443	-- data_out_pulse =>crossbar_in_pulse(4),
444	-- request(16) =>request_signal(16),
445	-- request(17) =>request_signal(17),
446	-- request(18) =>request_signal(18),
447	-- request(19) =>request_signal(19),
448	-- request(20) =>request_signal(20)
449	--);
450	--
451	--PORT5_INPUT_PORT_MODULE: INPUT_PORT_MODULE
452	--GENERIC MAP(number_of_ports =>5)
453	--PORT MAP(
454	-- data_in => Port_in(5),
455	-- data_in_en => data_in_en(5),
456	-- reset => reset,
457	-- clk =>clk,
458	-- grant(21) => grant_signal(21),
459	-- grant(22) => grant_signal(22),
460	-- grant(23) => grant_signal(23),
461	-- grant(24) => grant_signal(24),
462	-- grant(25) => grant_signal(25),
463	-- fifo_full =>fifo_in_full(5),
464	-- priority_rotation => priority_rotation_signal(5),
465	-- fifo_empty => fifo_in_empty(5),
466	-- data_out =>crossbar_in_port(5),
467	-- data_out_pulse =>crossbar_in_pulse(5),
468	-- request(21) =>request_signal(21),
469	-- request(22) =>request_signal(22),
470	-- request(23) =>request_signal(23),
471	-- request(24) =>request_signal(24),
472	-- request(25) =>request_signal(25)
473	--);
474	--
475	--end generate switch5x5;
476	--
477	--
478	---- switch 6 ports
479	--switch6x6 : if number_of_ports = 6 generate
480	--
481	--PORT1_INPUT_PORT_MODULE: INPUT_PORT_MODULE
482	--GENERIC MAP(number_of_ports =>6)
483	--PORT MAP(
484	-- data_in => Port_in(1),
485	-- data_in_en => data_in_en(1),
486	-- cmd_in_en => cmd_in_en(1),
487	-- reset => reset,
488	-- clk =>clk,
489	-- grant(1) => grant_signal(1),
490	-- grant(2) => grant_signal(2),
491	-- grant(3) => grant_signal(3),
492	-- grant(4) => grant_signal(4),
493	-- grant(5) => grant_signal(5),
494	-- grant(6) => grant_signal(6),
495	-- fifo_full =>fifo_in_full(1),
496	-- priority_rotation => priority_rotation_signal(1),
497	-- fifo_empty => fifo_in_empty(1),
498	-- data_out =>crossbar_in_port(1),
499	-- data_out_pulse =>crossbar_in_pulse(1),
500	-- request(1) =>request_signal(1),
501	-- request(2) =>request_signal(2),
502	-- request(3) =>request_signal(3),
503	-- request(4) =>request_signal(4),
504	-- request(5) =>request_signal(5),
505	-- request(6) =>request_signal(6)
506	--);
507	--
508	--PORT2_INPUT_PORT_MODULE: INPUT_PORT_MODULE
509	--GENERIC MAP(number_of_ports =>6)
510	--PORT MAP(
511	-- data_in => Port_in(2),
512	-- data_in_en => data_in_en(2),
513	-- reset => reset,
514	-- clk =>clk,
515	-- grant(1) => grant_signal(7),
516	-- grant(2) => grant_signal(8),
517	-- grant(3) => grant_signal(9),
518	-- grant(4) => grant_signal(10),
519	-- grant(5) => grant_signal(11),
520	-- grant(6) => grant_signal(12),
521	-- fifo_full =>fifo_in_full(2),
522	-- priority_rotation => priority_rotation_signal(2),
523	-- fifo_empty => fifo_in_empty(2),
524	-- data_out =>crossbar_in_port(2),
525	-- data_out_pulse =>crossbar_in_pulse(2),
526	-- request(1) =>request_signal(7),
527	-- request(2) =>request_signal(8),
528	-- request(3) =>request_signal(9),
529	-- request(4) =>request_signal(10),
530	-- request(5) =>request_signal(11),
531	-- request(6) =>request_signal(12)
532	--);
533	--
534	--PORT3_INPUT_PORT_MODULE: INPUT_PORT_MODULE
535	--GENERIC MAP(number_of_ports =>6)
536	--PORT MAP(
537	-- data_in => Port_in(3),
538	-- data_in_en => data_in_en(3),
539	-- reset => reset,
540	-- clk =>clk,
541	-- grant(13) => grant_signal(13),
542	-- grant(14) => grant_signal(14),
543	-- grant(15) => grant_signal(15),
544	-- grant(16) => grant_signal(16),
545	-- grant(17) => grant_signal(17),
546	-- grant(18) => grant_signal(18),
547	-- fifo_full =>fifo_in_full(3),
548	-- priority_rotation => priority_rotation_signal(3),
549	-- fifo_empty => fifo_in_empty(3),
550	-- data_out =>crossbar_in_port(3),
551	-- data_out_pulse =>crossbar_in_pulse(3),
552	-- request(13) =>request_signal(13),
553	-- request(14) =>request_signal(14),
554	-- request(15) =>request_signal(15),
555	-- request(16) =>request_signal(16),
556	-- request(17) =>request_signal(17),
557	-- request(18) =>request_signal(18)
558	--);
559	--
560	--PORT4_INPUT_PORT_MODULE: INPUT_PORT_MODULE
561	--GENERIC MAP(number_of_ports =>6)
562	--PORT MAP(
563	-- data_in => Port_in(4),
564	-- data_in_en => data_in_en(4),
565	-- cmd_in_en => cmd_in_en(4),
566	-- reset => reset,
567	-- clk =>clk,
568	-- grant(19) => grant_signal(19),
569	-- grant(20) => grant_signal(20),
570	-- grant(21) => grant_signal(21),
571	-- grant(22) => grant_signal(22),
572	-- grant(23) => grant_signal(23),
573	-- grant(24) => grant_signal(24),
574	-- fifo_full =>fifo_in_full(4),
575	-- priority_rotation => priority_rotation_signal(4),
576	-- fifo_empty => fifo_in_empty(4),
577	-- data_out =>crossbar_in_port(4),
578	-- data_out_pulse =>crossbar_in_pulse(4),
579	-- request(19) =>request_signal(19),
580	-- request(20) =>request_signal(20),
581	-- request(21) =>request_signal(21),
582	-- request(22) =>request_signal(22),
583	-- request(23) =>request_signal(23),
584	-- request(24) =>request_signal(24)
585	--);
586	--
587	--PORT5_INPUT_PORT_MODULE: INPUT_PORT_MODULE
588	--GENERIC MAP(number_of_ports =>6)
589	--PORT MAP(
590	-- data_in => Port_in(5),
591	-- data_in_en => data_in_en(5),
592	-- cmd_in_en => cmd_in_en(5),
593	-- reset => reset,
594	-- clk =>clk,
595	-- grant(25) => grant_signal(25),
596	-- grant(26) => grant_signal(26),
597	-- grant(27) => grant_signal(27),
598	-- grant(28) => grant_signal(28),
599	-- grant(29) => grant_signal(29),
600	-- grant(30) => grant_signal(30),
601	-- fifo_full =>fifo_in_full(5),
602	-- priority_rotation => priority_rotation_signal(5),
603	-- fifo_empty => fifo_in_empty(5),
604	-- data_out =>crossbar_in_port(5),
605	-- data_out_pulse =>crossbar_in_pulse(5),
606	-- request(25) =>request_signal(25),
607	-- request(26) =>request_signal(26),
608	-- request(27) =>request_signal(27),
609	-- request(28) =>request_signal(28),
610	-- request(29) =>request_signal(29),
611	-- request(30) =>request_signal(30)
612	--);
613	--
614	--PORT6_INPUT_PORT_MODULE: INPUT_PORT_MODULE
615	--GENERIC MAP(number_of_ports =>6)
616	--PORT MAP(
617	-- data_in => Port_in(6),
618	-- data_in_en => data_in_en(6),
619	-- reset => reset,
620	-- clk =>clk,
621	-- grant(31) => grant_signal(31),
622	-- grant(32) => grant_signal(32),
623	-- grant(33) => grant_signal(33),
624	-- grant(34) => grant_signal(34),
625	-- grant(35) => grant_signal(35),
626	-- grant(36) => grant_signal(36),
627	-- fifo_full =>fifo_in_full(6),
628	-- priority_rotation => priority_rotation_signal(6),
629	-- fifo_empty => fifo_in_empty(6),
630	-- data_out =>crossbar_in_port(6),
631	-- data_out_pulse =>crossbar_in_pulse(6),
632	-- request(31) =>request_signal(31),
633	-- request(32) =>request_signal(32),
634	-- request(33) =>request_signal(33),
635	-- request(34) =>request_signal(34),
636	-- request(35) =>request_signal(35),
637	-- request(36) =>request_signal(36)
638	--);
639	--
640	--end generate switch6x6;
641	--
642	--
643	---- switch 7 ports
644	--switch7x7 : if number_of_ports = 7 generate
645	--
646	--PORT1_INPUT_PORT_MODULE: INPUT_PORT_MODULE
647	--GENERIC MAP(number_of_ports =>7)
648	--PORT MAP(
649	-- data_in => Port_in(1),
650	-- data_in_en => data_in_en(1),
651	-- cmd_in_en => cmd_in_en(1),
652	-- reset => reset,
653	-- clk =>clk,
654	-- grant(1) => grant_signal(1),
655	-- grant(2) => grant_signal(2),
656	-- grant(3) => grant_signal(3),
657	-- grant(4) => grant_signal(4),
658	-- grant(5) => grant_signal(5),
659	-- grant(6) => grant_signal(6),
660	-- grant(7) => grant_signal(7),
661	-- fifo_full =>fifo_in_full(1),
662	-- priority_rotation => priority_rotation_signal(1),
663	-- fifo_empty => fifo_in_empty(1),
664	-- data_out =>crossbar_in_port(1),
665	-- data_out_pulse =>crossbar_in_pulse(1),
666	-- request(1) =>request_signal(1),
667	-- request(2) =>request_signal(2),
668	-- request(3) =>request_signal(3),
669	-- request(4) =>request_signal(4),
670	-- request(5) =>request_signal(5),
671	-- request(6) =>request_signal(6),
672	-- request(7) =>request_signal(7)
673	--);
674	--
675	--PORT2_INPUT_PORT_MODULE: INPUT_PORT_MODULE
676	--GENERIC MAP(number_of_ports =>7)
677	--PORT MAP(
678	-- data_in => Port_in(2),
679	-- data_in_en => data_in_en(2),
680	-- reset => reset,
681	-- clk =>clk,
682	-- grant(1) => grant_signal(8),
683	-- grant(2) => grant_signal(9),
684	-- grant(3) => grant_signal(10),
685	-- grant(4) => grant_signal(11),
686	-- grant(5) => grant_signal(12),
687	-- grant(6) => grant_signal(13),
688	-- grant(7) => grant_signal(14),
689	-- fifo_full =>fifo_in_full(2),
690	-- priority_rotation => priority_rotation_signal(2),
691	-- fifo_empty => fifo_in_empty(2),
692	-- data_out =>crossbar_in_port(2),
693	-- data_out_pulse =>crossbar_in_pulse(2),
694	-- request(8) =>request_signal(8),
695	-- request(9) =>request_signal(9),
696	-- request(10) =>request_signal(10),
697	-- request(11) =>request_signal(11),
698	-- request(12) =>request_signal(12),
699	-- request(13) =>request_signal(13),
700	-- request(14) =>request_signal(14)
701	--);
702	--
703	--PORT3_INPUT_PORT_MODULE: INPUT_PORT_MODULE
704	--GENERIC MAP(number_of_ports =>7)
705	--PORT MAP(
706	-- data_in => Port_in(3),
707	-- data_in_en => data_in_en(3),
708	-- reset => reset,
709	-- clk =>clk,
710	-- grant(15) => grant_signal(15),
711	-- grant(16) => grant_signal(16),
712	-- grant(17) => grant_signal(17),
713	-- grant(18) => grant_signal(18),
714	-- grant(19) => grant_signal(19),
715	-- grant(20) => grant_signal(20),
716	-- grant(21) => grant_signal(21),
717	-- fifo_full =>fifo_in_full(3),
718	-- priority_rotation => priority_rotation_signal(3),
719	-- fifo_empty => fifo_in_empty(3),
720	-- data_out =>crossbar_in_port(3),
721	-- data_out_pulse =>crossbar_in_pulse(3),
722	-- request(15) =>request_signal(15),
723	-- request(16) =>request_signal(16),
724	-- request(17) =>request_signal(17),
725	-- request(18) =>request_signal(18),
726	-- request(19) =>request_signal(19),
727	-- request(20) =>request_signal(20),
728	-- request(21) =>request_signal(21)
729	--);
730	--
731	--PORT4_INPUT_PORT_MODULE: INPUT_PORT_MODULE
732	--GENERIC MAP(number_of_ports =>7)
733	--PORT MAP(
734	-- data_in => Port_in(4),
735	-- data_in_en => data_in_en(4),
736	-- reset => reset,
737	-- clk =>clk,
738	-- grant(22) => grant_signal(22),
739	-- grant(23) => grant_signal(23),
740	-- grant(24) => grant_signal(24),
741	-- grant(25) => grant_signal(25),
742	-- grant(26) => grant_signal(26),
743	-- grant(27) => grant_signal(27),
744	-- grant(28) => grant_signal(28),
745	-- fifo_full =>fifo_in_full(4),
746	-- priority_rotation => priority_rotation_signal(4),
747	-- fifo_empty => fifo_in_empty(4),
748	-- data_out =>crossbar_in_port(4),
749	-- data_out_pulse =>crossbar_in_pulse(4),
750	-- request(22) =>request_signal(22),
751	-- request(23) =>request_signal(23),
752	-- request(24) =>request_signal(24),
753	-- request(25) =>request_signal(25),
754	-- request(26) =>request_signal(26),
755	-- request(27) =>request_signal(27),
756	-- request(28) =>request_signal(28)
757	--);
758	--
759	--PORT5_INPUT_PORT_MODULE: INPUT_PORT_MODULE
760	--GENERIC MAP(number_of_ports =>7)
761	--PORT MAP(
762	-- data_in => Port_in(5),
763	-- data_in_en => data_in_en(5),
764	-- reset => reset,
765	-- clk =>clk,
766	-- grant(29) => grant_signal(29),
767	-- grant(30) => grant_signal(30),
768	-- grant(31) => grant_signal(31),
769	-- grant(32) => grant_signal(32),
770	-- grant(33) => grant_signal(33),
771	-- grant(34) => grant_signal(34),
772	-- grant(35) => grant_signal(35),
773	-- fifo_full =>fifo_in_full(5),
774	-- priority_rotation => priority_rotation_signal(5),
775	-- fifo_empty => fifo_in_empty(5),
776	-- data_out =>crossbar_in_port(5),
777	-- data_out_pulse =>crossbar_in_pulse(5),
778	-- request(29) =>request_signal(29),
779	-- request(30) =>request_signal(30),
780	-- request(31) =>request_signal(31),
781	-- request(32) =>request_signal(32),
782	-- request(33) =>request_signal(33),
783	-- request(34) =>request_signal(34),
784	-- request(35) =>request_signal(35)
785	--);
786	--
787	--PORT6_INPUT_PORT_MODULE: INPUT_PORT_MODULE
788	--GENERIC MAP(number_of_ports =>7)
789	--PORT MAP(
790	-- data_in => Port_in(6),
791	-- data_in_en => data_in_en(6),
792	-- reset => reset,
793	-- clk =>clk,
794	-- grant(36) => grant_signal(36),
795	-- grant(37) => grant_signal(37),
796	-- grant(38) => grant_signal(38),
797	-- grant(39) => grant_signal(39),
798	-- grant(40) => grant_signal(40),
799	-- grant(41) => grant_signal(41),
800	-- grant(42) => grant_signal(42),
801	-- fifo_full =>fifo_in_full(6),
802	-- priority_rotation => priority_rotation_signal(6),
803	-- fifo_empty => fifo_in_empty(6),
804	-- data_out =>crossbar_in_port(6),
805	-- data_out_pulse =>crossbar_in_pulse(6),
806	-- request(36) =>request_signal(36),
807	-- request(37) =>request_signal(37),
808	-- request(38) =>request_signal(38),
809	-- request(39) =>request_signal(39),
810	-- request(40) =>request_signal(40),
811	-- request(41) =>request_signal(41),
812	-- request(42) =>request_signal(42)
813	--);
814	--
815	--PORT7_INPUT_PORT_MODULE: INPUT_PORT_MODULE
816	--GENERIC MAP(number_of_ports =>7)
817	--PORT MAP(
818	-- data_in => Port_in(7),
819	-- data_in_en => data_in_en(7),
820	-- reset => reset,
821	-- clk =>clk,
822	-- grant(43) => grant_signal(43),
823	-- grant(44) => grant_signal(44),
824	-- grant(45) => grant_signal(45),
825	-- grant(46) => grant_signal(46),
826	-- grant(47) => grant_signal(47),
827	-- grant(48) => grant_signal(48),
828	-- grant(49) => grant_signal(49),
829	-- fifo_full =>fifo_in_full(7),
830	-- priority_rotation => priority_rotation_signal(7),
831	-- fifo_empty => fifo_in_empty(7),
832	-- data_out =>crossbar_in_port(8),
833	-- data_out_pulse =>crossbar_in_pulse(7),
834	-- request(43) =>request_signal(43),
835	-- request(44) =>request_signal(44),
836	-- request(45) =>request_signal(45),
837	-- request(46) =>request_signal(46),
838	-- request(47) =>request_signal(47),
839	-- request(48) =>request_signal(48),
840	-- request(49) =>request_signal(49)
841	--);
842	--
843	--end generate switch7x7;
844
845
846	-- switch 8 ports
847	switch8x8 : if number_of_ports = 8 generate
848	switch_8x8:for i in 1 to number_of_ports generate
849	constant j: natural:=number_of_ports*(i-1);
850	begin
851	--j<=number_of_ports*(i-1);
852	PORTx8_INPUT_PORT_MODULE: INPUT_PORT_MODULE
853	GENERIC MAP(number_of_ports =>8,Port_num=>i)
854	PORT MAP(
855	data_in => Port_in(i),
856	data_in_en => data_in_en(i),
857	cmd_in_en => cmd_in_en(i),
858	reset => reset,
859	clk =>clk,
860	grant =>grant_signal(j+NUMBER_OF_PORTS downto j+1),
861	fifo_full =>fifo_in_full(i),
862	priority_rotation => priority_rotation_signal(i),
863	fifo_empty => fifo_in_empty(i),
864	data_out =>crossbar_in_port(i),
865	data_out_pulse =>crossbar_in_pulse(i),
866
867	request =>request_signal(j+NUMBER_OF_PORTS downto j+1)
868	);
869	end generate switch_8x8;
870	end generate switch8x8;
871
872	-- switch 9 ports
873	switch9x9_to_15 : if (number_of_ports >= 9)and (number_of_ports <= 15) generate
874
875	switch_9x9_to_15:for i in 1 to number_of_ports generate
876
877	constant j: natural:=number_of_ports*(i-1);
878	begin
879
880	PORTx9_INPUT_PORT_MODULE: INPUT_PORT_MODULE
881	GENERIC MAP(number_of_ports =>NUMBER_OF_PORTS,Port_num=>i)
882	PORT MAP(
883	data_in => Port_in(i),
884	data_in_en => data_in_en(i),
885	cmd_in_en => cmd_in_en(i),
886	reset => reset,
887	clk =>clk,
888	grant => grant_signal(j+NUMBER_OF_PORTS downto j+1),
889	fifo_full =>fifo_in_full(i),
890	priority_rotation => priority_rotation_signal(i),
891	fifo_empty => fifo_in_empty(i),
892	data_out =>crossbar_in_port(i),
893	data_out_pulse =>crossbar_in_pulse(i),
894
895	request =>request_signal(j+NUMBER_OF_PORTS downto j+1)
896	);
897	end generate switch_9x9_to_15;
898	end generate switch9x9_to_15;
899
900
901
902	-- switch 10 ports
903	--switch10x10 : if number_of_ports = 10 generate
904	--
905	--PORT1_INPUT_PORT_MODULE: INPUT_PORT_MODULE
906	--GENERIC MAP(number_of_ports =>10)
907	--PORT MAP(
908	-- data_in => Port_in(1),
909	-- data_in_en => data_in_en(1),
910	-- reset => reset,
911	-- clk =>clk,
912	-- grant(1) => grant_signal(1),
913	-- grant(2) => grant_signal(2),
914	-- grant(3) => grant_signal(3),
915	-- grant(4) => grant_signal(4),
916	-- grant(5) => grant_signal(5),
917	-- grant(6) => grant_signal(6),
918	-- grant(7) => grant_signal(7),
919	-- grant(8) => grant_signal(8),
920	-- grant(9) => grant_signal(9),
921	-- grant(10) => grant_signal(10),
922	-- fifo_full =>fifo_in_full(1),
923	-- priority_rotation => priority_rotation_signal(1),
924	-- fifo_empty => fifo_in_empty(1),
925	-- data_out =>crossbar_in_port(1),
926	-- data_out_pulse =>crossbar_in_pulse(1),
927	-- request(1) =>request_signal(1),
928	-- request(2) =>request_signal(2),
929	-- request(3) =>request_signal(3),
930	-- request(4) =>request_signal(4),
931	-- request(5) =>request_signal(5),
932	-- request(6) =>request_signal(6),
933	-- request(7) =>request_signal(7),
934	-- request(8) =>request_signal(8),
935	-- request(9) =>request_signal(9),
936	-- request(10) =>request_signal(10)
937	--);
938	--
939	--PORT2_INPUT_PORT_MODULE: INPUT_PORT_MODULE
940	--GENERIC MAP(number_of_ports =>10)
941	--PORT MAP(
942	-- data_in => Port_in(2),
943	-- data_in_en => data_in_en(2),
944	-- reset => reset,
945	-- clk =>clk,
946	-- grant(1) => grant_signal(11),
947	-- grant(2) => grant_signal(12),
948	-- grant(3) => grant_signal(13),
949	-- grant(4) => grant_signal(14),
950	-- grant(5) => grant_signal(15),
951	-- grant(6) => grant_signal(16),
952	-- grant(7) => grant_signal(17),
953	-- grant(8) => grant_signal(18),
954	-- grant(9) => grant_signal(19),
955	-- grant(10) => grant_signal(20),
956	-- fifo_full =>fifo_in_full(2),
957	-- priority_rotation => priority_rotation_signal(2),
958	-- fifo_empty => fifo_in_empty(2),
959	-- data_out =>crossbar_in_port(2),
960	-- data_out_pulse =>crossbar_in_pulse(2),
961	-- request(1) =>request_signal(11),
962	-- request(2) =>request_signal(12),
963	-- request(3) =>request_signal(13),
964	-- request(4) =>request_signal(14),
965	-- request(5) =>request_signal(15),
966	-- request(6) =>request_signal(16),
967	-- request(7) =>request_signal(17),
968	-- request(8) =>request_signal(18),
969	-- request(9) =>request_signal(19),
970	-- request(10) =>request_signal(20)
971	--);
972	--
973	--PORT3_INPUT_PORT_MODULE: INPUT_PORT_MODULE
974	--GENERIC MAP(number_of_ports =>10)
975	--PORT MAP(
976	-- data_in => Port_in(3),
977	-- data_in_en => data_in_en(3),
978	-- reset => reset,
979	-- clk =>clk,
980	-- grant(1) => grant_signal(21),
981	-- grant(2) => grant_signal(22),
982	-- grant(3) => grant_signal(23),
983	-- grant(4) => grant_signal(24),
984	-- grant(5) => grant_signal(25),
985	-- grant(6) => grant_signal(26),
986	-- grant(7) => grant_signal(27),
987	-- grant(8) => grant_signal(28),
988	-- grant(9) => grant_signal(29),
989	-- grant(10) => grant_signal(30),
990	-- fifo_full =>fifo_in_full(3),
991	-- priority_rotation => priority_rotation_signal(3),
992	-- fifo_empty => fifo_in_empty(3),
993	-- data_out =>crossbar_in_port(3),
994	-- data_out_pulse =>crossbar_in_pulse(3),
995	-- request(1) =>request_signal(21),
996	-- request(2) =>request_signal(22),
997	-- request(3) =>request_signal(23),
998	-- request(4) =>request_signal(24),
999	-- request(5) =>request_signal(25),
1000	-- request(6) =>request_signal(26),
1001	-- request(7) =>request_signal(27),
1002	-- request(8) =>request_signal(28),
1003	-- request(9) =>request_signal(29),
1004	-- request(10) =>request_signal(30)
1005	--);
1006	--
1007	--PORT4_INPUT_PORT_MODULE: INPUT_PORT_MODULE
1008	--GENERIC MAP(number_of_ports =>10)
1009	--PORT MAP(
1010	-- data_in => Port_in(4),
1011	-- data_in_en => data_in_en(4),
1012	-- reset => reset,
1013	-- clk =>clk,
1014	-- grant(1) => grant_signal(31),
1015	-- grant(2) => grant_signal(32),
1016	-- grant(3) => grant_signal(33),
1017	-- grant(4) => grant_signal(34),
1018	-- grant(5) => grant_signal(35),
1019	-- grant(6) => grant_signal(36),
1020	-- grant(7) => grant_signal(37),
1021	-- grant(8) => grant_signal(38),
1022	-- grant(9) => grant_signal(39),
1023	-- grant(10) => grant_signal(40),
1024	-- fifo_full =>fifo_in_full(4),
1025	-- priority_rotation => priority_rotation_signal(4),
1026	-- fifo_empty => fifo_in_empty(4),
1027	-- data_out =>crossbar_in_port(4),
1028	-- data_out_pulse =>crossbar_in_pulse(4),
1029	-- request(1) =>request_signal(31),
1030	-- request(2) =>request_signal(32),
1031	-- request(3) =>request_signal(33),
1032	-- request(4) =>request_signal(34),
1033	-- request(5) =>request_signal(35),
1034	-- request(6) =>request_signal(36),
1035	-- request(7) =>request_signal(37),
1036	-- request(8) =>request_signal(38),
1037	-- request(9) =>request_signal(39),
1038	-- request(10) =>request_signal(40)
1039	--);
1040	--
1041	--PORT5_INPUT_PORT_MODULE: INPUT_PORT_MODULE
1042	--GENERIC MAP(number_of_ports =>10)
1043	--PORT MAP(
1044	-- data_in => Port_in(5),
1045	-- data_in_en => data_in_en(5),
1046	-- reset => reset,
1047	-- clk =>clk,
1048	-- grant(1) => grant_signal(41),
1049	-- grant(2) => grant_signal(42),
1050	-- grant(3) => grant_signal(43),
1051	-- grant(4) => grant_signal(44),
1052	-- grant(5) => grant_signal(45),
1053	-- grant(6) => grant_signal(46),
1054	-- grant(7) => grant_signal(47),
1055	-- grant(8) => grant_signal(48),
1056	-- grant(9) => grant_signal(49),
1057	-- grant(10) => grant_signal(50),
1058	-- fifo_full =>fifo_in_full(5),
1059	-- priority_rotation => priority_rotation_signal(5),
1060	-- fifo_empty => fifo_in_empty(5),
1061	-- data_out =>crossbar_in_port(5),
1062	-- data_out_pulse =>crossbar_in_pulse(5),
1063	-- request(1) =>request_signal(41),
1064	-- request(2) =>request_signal(42),
1065	-- request(3) =>request_signal(43),
1066	-- request(4) =>request_signal(44),
1067	-- request(5) =>request_signal(45),
1068	-- request(6) =>request_signal(46),
1069	-- request(7) =>request_signal(47),
1070	-- request(8) =>request_signal(48),
1071	-- request(9) =>request_signal(49),
1072	-- request(10) =>request_signal(50)
1073	--);
1074	--
1075	--PORT6_INPUT_PORT_MODULE: INPUT_PORT_MODULE
1076	--GENERIC MAP(number_of_ports =>10)
1077	--PORT MAP(
1078	-- data_in => Port_in(6),
1079	-- data_in_en => data_in_en(6),
1080	-- reset => reset,
1081	-- clk =>clk,
1082	-- grant(1) => grant_signal(51),
1083	-- grant(2) => grant_signal(52),
1084	-- grant(3) => grant_signal(53),
1085	-- grant(4) => grant_signal(54),
1086	-- grant(5) => grant_signal(55),
1087	-- grant(6) => grant_signal(56),
1088	-- grant(7) => grant_signal(57),
1089	-- grant(8) => grant_signal(58),
1090	-- grant(9) => grant_signal(59),
1091	-- grant(10) => grant_signal(60),
1092	-- fifo_full =>fifo_in_full(6),
1093	-- priority_rotation => priority_rotation_signal(6),
1094	-- fifo_empty => fifo_in_empty(6),
1095	-- data_out =>crossbar_in_port(6),
1096	-- data_out_pulse =>crossbar_in_pulse(6),
1097	-- request(1) =>request_signal(51),
1098	-- request(2) =>request_signal(52),
1099	-- request(3) =>request_signal(53),
1100	-- request(4) =>request_signal(54),
1101	-- request(5) =>request_signal(55),
1102	-- request(6) =>request_signal(56),
1103	-- request(7) =>request_signal(57),
1104	-- request(8) =>request_signal(58),
1105	-- request(9) =>request_signal(59),
1106	-- request(10) =>request_signal(60)
1107	--);
1108	--
1109	--PORT7_INPUT_PORT_MODULE: INPUT_PORT_MODULE
1110	--GENERIC MAP(number_of_ports =>10)
1111	--PORT MAP(
1112	-- data_in => Port_in(7),
1113	-- data_in_en => data_in_en(7),
1114	-- reset => reset,
1115	-- clk =>clk,
1116	-- grant(1) => grant_signal(61),
1117	-- grant(2) => grant_signal(62),
1118	-- grant(3) => grant_signal(63),
1119	-- grant(4) => grant_signal(64),
1120	-- grant(5) => grant_signal(65),
1121	-- grant(6) => grant_signal(66),
1122	-- grant(7) => grant_signal(67),
1123	-- grant(8) => grant_signal(68),
1124	-- grant(9) => grant_signal(69),
1125	-- grant(10) => grant_signal(70),
1126	-- fifo_full =>fifo_in_full(7),
1127	-- priority_rotation => priority_rotation_signal(7),
1128	-- fifo_empty => fifo_in_empty(7),
1129	-- data_out =>crossbar_in_port(7),
1130	-- data_out_pulse =>crossbar_in_pulse(7),
1131	-- request(1) =>request_signal(61),
1132	-- request(2) =>request_signal(62),
1133	-- request(3) =>request_signal(63),
1134	-- request(4) =>request_signal(64),
1135	-- request(5) =>request_signal(65),
1136	-- request(6) =>request_signal(66),
1137	-- request(7) =>request_signal(67),
1138	-- request(8) =>request_signal(68),
1139	-- request(9) =>request_signal(69),
1140	-- request(10) =>request_signal(70)
1141	--);
1142	--
1143	--PORT8_INPUT_PORT_MODULE: INPUT_PORT_MODULE
1144	--GENERIC MAP(number_of_ports =>10)
1145	--PORT MAP(
1146	-- data_in => Port_in(8),
1147	-- data_in_en => data_in_en(8),
1148	-- reset => reset,
1149	-- clk =>clk,
1150	-- grant(1) => grant_signal(71),
1151	-- grant(2) => grant_signal(72),
1152	-- grant(3) => grant_signal(73),
1153	-- grant(4) => grant_signal(74),
1154	-- grant(5) => grant_signal(75),
1155	-- grant(6) => grant_signal(76),
1156	-- grant(7) => grant_signal(77),
1157	-- grant(8) => grant_signal(78),
1158	-- grant(9) => grant_signal(79),
1159	-- grant(10) => grant_signal(80),
1160	-- fifo_full =>fifo_in_full(8),
1161	-- priority_rotation => priority_rotation_signal(8),
1162	-- fifo_empty => fifo_in_empty(8),
1163	-- data_out =>crossbar_in_port(8),
1164	-- data_out_pulse =>crossbar_in_pulse(8),
1165	-- request(1) =>request_signal(71),
1166	-- request(2) =>request_signal(72),
1167	-- request(3) =>request_signal(73),
1168	-- request(4) =>request_signal(74),
1169	-- request(5) =>request_signal(75),
1170	-- request(6) =>request_signal(76),
1171	-- request(7) =>request_signal(77),
1172	-- request(8) =>request_signal(78),
1173	-- request(9) =>request_signal(79),
1174	-- request(10) =>request_signal(80)
1175	--);
1176	--
1177	--PORT9_INPUT_PORT_MODULE: INPUT_PORT_MODULE
1178	--GENERIC MAP(number_of_ports =>10)
1179	--PORT MAP(
1180	-- data_in => Port_in(9),
1181	-- data_in_en => data_in_en(9),
1182	-- reset => reset,
1183	-- clk =>clk,
1184	-- grant(1) => grant_signal(81),
1185	-- grant(2) => grant_signal(82),
1186	-- grant(3) => grant_signal(83),
1187	-- grant(4) => grant_signal(84),
1188	-- grant(5) => grant_signal(85),
1189	-- grant(6) => grant_signal(86),
1190	-- grant(7) => grant_signal(87),
1191	-- grant(8) => grant_signal(88),
1192	-- grant(9) => grant_signal(89),
1193	-- grant(10) => grant_signal(90),
1194	-- fifo_full =>fifo_in_full(9),
1195	-- priority_rotation => priority_rotation_signal(9),
1196	-- fifo_empty => fifo_in_empty(9),
1197	-- data_out =>crossbar_in_port(9),
1198	-- data_out_pulse =>crossbar_in_pulse(9),
1199	-- request(1) =>request_signal(81),
1200	-- request(2) =>request_signal(82),
1201	-- request(3) =>request_signal(83),
1202	-- request(4) =>request_signal(84),
1203	-- request(5) =>request_signal(85),
1204	-- request(6) =>request_signal(86),
1205	-- request(7) =>request_signal(87),
1206	-- request(8) =>request_signal(88),
1207	-- request(9) =>request_signal(89),
1208	-- request(10) =>request_signal(90)
1209	--);
1210	--
1211	--PORT10_INPUT_PORT_MODULE: INPUT_PORT_MODULE
1212	--GENERIC MAP(number_of_ports =>10)
1213	--PORT MAP(
1214	-- data_in => Port_in(10),
1215	-- data_in_en => data_in_en(10),
1216	-- reset => reset,
1217	-- clk =>clk,
1218	-- grant(1) => grant_signal(91),
1219	-- grant(2) => grant_signal(92),
1220	-- grant(3) => grant_signal(93),
1221	-- grant(4) => grant_signal(94),
1222	-- grant(5) => grant_signal(95),
1223	-- grant(6) => grant_signal(96),
1224	-- grant(7) => grant_signal(97),
1225	-- grant(8) => grant_signal(98),
1226	-- grant(9) => grant_signal(99),
1227	-- grant(10) => grant_signal(100),
1228	-- fifo_full =>fifo_in_full(10),
1229	-- priority_rotation => priority_rotation_signal(10),
1230	-- fifo_empty => fifo_in_empty(10),
1231	-- data_out =>crossbar_in_port(10),
1232	-- data_out_pulse =>crossbar_in_pulse(10),
1233	-- request(1) =>request_signal(91),
1234	-- request(2) =>request_signal(92),
1235	-- request(3) =>request_signal(93),
1236	-- request(4) =>request_signal(94),
1237	-- request(5) =>request_signal(95),
1238	-- request(6) =>request_signal(96),
1239	-- request(7) =>request_signal(97),
1240	-- request(8) =>request_signal(98),
1241	-- request(9) =>request_signal(99),
1242	-- request(10) =>request_signal(100)
1243	--);
1244	--
1245	--end generate switch10x10;
1246	--
1247	--
1248	---- switch 11 ports
1249	--switch11x11 : if number_of_ports = 11 generate
1250	--
1251	--PORT1_INPUT_PORT_MODULE: INPUT_PORT_MODULE
1252	--GENERIC MAP(number_of_ports =>11)
1253	--PORT MAP(
1254	-- data_in => Port_in(1),
1255	-- data_in_en => data_in_en(1),
1256	-- reset => reset,
1257	-- clk =>clk,
1258	-- grant(1) => grant_signal(1),
1259	-- grant(2) => grant_signal(2),
1260	-- grant(3) => grant_signal(3),
1261	-- grant(4) => grant_signal(4),
1262	-- grant(5) => grant_signal(5),
1263	-- grant(6) => grant_signal(6),
1264	-- grant(7) => grant_signal(7),
1265	-- grant(8) => grant_signal(8),
1266	-- grant(9) => grant_signal(9),
1267	-- grant(10) => grant_signal(10),
1268	-- grant(11) => grant_signal(11),
1269	-- fifo_full =>fifo_in_full(1),
1270	-- priority_rotation => priority_rotation_signal(1),
1271	-- fifo_empty => fifo_in_empty(1),
1272	-- data_out =>crossbar_in_port(1),
1273	-- data_out_pulse =>crossbar_in_pulse(1),
1274	-- request(1) =>request_signal(1),
1275	-- request(2) =>request_signal(2),
1276	-- request(3) =>request_signal(3),
1277	-- request(4) =>request_signal(4),
1278	-- request(5) =>request_signal(5),
1279	-- request(6) =>request_signal(6),
1280	-- request(7) =>request_signal(7),
1281	-- request(8) =>request_signal(8),
1282	-- request(9) =>request_signal(9),
1283	-- request(10) =>request_signal(10),
1284	-- request(11) =>request_signal(11)
1285	--);
1286	--
1287	--PORT2_INPUT_PORT_MODULE: INPUT_PORT_MODULE
1288	--GENERIC MAP(number_of_ports =>11)
1289	--PORT MAP(
1290	-- data_in => Port_in(2),
1291	-- data_in_en => data_in_en(2),
1292	-- reset => reset,
1293	-- clk =>clk,
1294	-- grant(1) => grant_signal(12),
1295	-- grant(02) => grant_signal(13),
1296	-- grant(03) => grant_signal(14),
1297	-- grant(04) => grant_signal(15),
1298	-- grant(05) => grant_signal(16),
1299	-- grant(06) => grant_signal(17),
1300	-- grant(07) => grant_signal(18),
1301	-- grant(08) => grant_signal(19),
1302	-- grant(09) => grant_signal(20),
1303	-- grant(10) => grant_signal(21),
1304	-- grant(11) => grant_signal(22),
1305	-- fifo_full =>fifo_in_full(2),
1306	-- priority_rotation => priority_rotation_signal(2),
1307	-- fifo_empty => fifo_in_empty(2),
1308	-- data_out =>crossbar_in_port(2),
1309	-- data_out_pulse =>crossbar_in_pulse(2),
1310	-- request(01) =>request_signal(12),
1311	-- request(02) =>request_signal(13),
1312	-- request(03) =>request_signal(14),
1313	-- request(04) =>request_signal(15),
1314	-- request(05) =>request_signal(16),
1315	-- request(06) =>request_signal(17),
1316	-- request(07) =>request_signal(18),
1317	-- request(08) =>request_signal(19),
1318	-- request(09) =>request_signal(20),
1319	-- request(10) =>request_signal(21),
1320	-- request(11) =>request_signal(22)
1321	--);
1322	--
1323	--PORT3_INPUT_PORT_MODULE: INPUT_PORT_MODULE
1324	--GENERIC MAP(number_of_ports =>11)
1325	--PORT MAP(
1326	-- data_in => Port_in(3),
1327	-- data_in_en => data_in_en(3),
1328	-- reset => reset,
1329	-- clk =>clk,
1330	-- grant(01) => grant_signal(23),
1331	-- grant(02) => grant_signal(24),
1332	-- grant(03) => grant_signal(25),
1333	-- grant(04) => grant_signal(26),
1334	-- grant(05) => grant_signal(27),
1335	-- grant(06) => grant_signal(28),
1336	-- grant(07) => grant_signal(29),
1337	-- grant(08) => grant_signal(30),
1338	-- grant(09) => grant_signal(31),
1339	-- grant(10) => grant_signal(32),
1340	-- grant(11) => grant_signal(33),
1341	-- fifo_full =>fifo_in_full(3),
1342	-- priority_rotation => priority_rotation_signal(3),
1343	-- fifo_empty => fifo_in_empty(3),
1344	-- data_out =>crossbar_in_port(3),
1345	-- data_out_pulse =>crossbar_in_pulse(3),
1346	-- request(01) =>request_signal(23),
1347	-- request(02) =>request_signal(24),
1348	-- request(03) =>request_signal(25),
1349	-- request(04) =>request_signal(26),
1350	-- request(05) =>request_signal(27),
1351	-- request(06) =>request_signal(28),
1352	-- request(07) =>request_signal(29),
1353	-- request(08) =>request_signal(30),
1354	-- request(09) =>request_signal(31),
1355	-- request(10) =>request_signal(32),
1356	-- request(11) =>request_signal(33)
1357	--);
1358	--
1359	--PORT4_INPUT_PORT_MODULE: INPUT_PORT_MODULE
1360	--GENERIC MAP(number_of_ports =>11)
1361	--PORT MAP(
1362	-- data_in => Port_in(4),
1363	-- data_in_en => data_in_en(4),
1364	-- reset => reset,
1365	-- clk =>clk,
1366	-- grant(01) => grant_signal(34),
1367	-- grant(02) => grant_signal(35),
1368	-- grant(03) => grant_signal(36),
1369	-- grant(04) => grant_signal(37),
1370	-- grant(05) => grant_signal(38),
1371	-- grant(06) => grant_signal(39),
1372	-- grant(07) => grant_signal(40),
1373	-- grant(08) => grant_signal(41),
1374	-- grant(09) => grant_signal(42),
1375	-- grant(10) => grant_signal(43),
1376	-- grant(11) => grant_signal(44),
1377	-- fifo_full =>fifo_in_full(4),
1378	-- priority_rotation => priority_rotation_signal(4),
1379	-- fifo_empty => fifo_in_empty(4),
1380	-- data_out =>crossbar_in_port(4),
1381	-- data_out_pulse =>crossbar_in_pulse(4),
1382	-- request(01) =>request_signal(34),
1383	-- request(02) =>request_signal(35),
1384	-- request(03) =>request_signal(36),
1385	-- request(04) =>request_signal(37),
1386	-- request(05) =>request_signal(38),
1387	-- request(06) =>request_signal(39),
1388	-- request(07) =>request_signal(40),
1389	-- request(08) =>request_signal(41),
1390	-- request(09) =>request_signal(42),
1391	-- request(10) =>request_signal(43),
1392	-- request(11) =>request_signal(44)
1393	--);
1394	--
1395	--PORT5_INPUT_PORT_MODULE: INPUT_PORT_MODULE
1396	--GENERIC MAP(number_of_ports =>11)
1397	--PORT MAP(
1398	-- data_in => Port_in(5),
1399	-- data_in_en => data_in_en(5),
1400	-- reset => reset,
1401	-- clk =>clk,
1402	-- grant(45) => grant_signal(45),
1403	-- grant(46) => grant_signal(46),
1404	-- grant(47) => grant_signal(47),
1405	-- grant(48) => grant_signal(48),
1406	-- grant(49) => grant_signal(49),
1407	-- grant(50) => grant_signal(50),
1408	-- grant(51) => grant_signal(51),
1409	-- grant(52) => grant_signal(52),
1410	-- grant(53) => grant_signal(53),
1411	-- grant(54) => grant_signal(54),
1412	-- grant(55) => grant_signal(55),
1413	-- fifo_full =>fifo_in_full(5),
1414	-- priority_rotation => priority_rotation_signal(5),
1415	-- fifo_empty => fifo_in_empty(5),
1416	-- data_out =>crossbar_in_port(5),
1417	-- data_out_pulse =>crossbar_in_pulse(5),
1418	-- request(45) =>request_signal(45),
1419	-- request(46) =>request_signal(46),
1420	-- request(47) =>request_signal(47),
1421	-- request(48) =>request_signal(48),
1422	-- request(49) =>request_signal(49),
1423	-- request(50) =>request_signal(50),
1424	-- request(51) =>request_signal(51),
1425	-- request(52) =>request_signal(52),
1426	-- request(53) =>request_signal(53),
1427	-- request(54) =>request_signal(54),
1428	-- request(55) =>request_signal(55)
1429	--);
1430	--
1431	--PORT6_INPUT_PORT_MODULE: INPUT_PORT_MODULE
1432	--GENERIC MAP(number_of_ports =>11)
1433	--PORT MAP(
1434	-- data_in => Port_in(6),
1435	-- data_in_en => data_in_en(6),
1436	-- reset => reset,
1437	-- clk =>clk,
1438	-- grant(56) => grant_signal(56),
1439	-- grant(57) => grant_signal(57),
1440	-- grant(58) => grant_signal(58),
1441	-- grant(59) => grant_signal(59),
1442	-- grant(60) => grant_signal(60),
1443	-- grant(61) => grant_signal(61),
1444	-- grant(62) => grant_signal(62),
1445	-- grant(63) => grant_signal(63),
1446	-- grant(64) => grant_signal(64),
1447	-- grant(65) => grant_signal(65),
1448	-- grant(66) => grant_signal(66),
1449	-- fifo_full =>fifo_in_full(6),
1450	-- priority_rotation => priority_rotation_signal(6),
1451	-- fifo_empty => fifo_in_empty(6),
1452	-- data_out =>crossbar_in_port(6),
1453	-- data_out_pulse =>crossbar_in_pulse(6),
1454	-- request(56) =>request_signal(56),
1455	-- request(57) =>request_signal(57),
1456	-- request(58) =>request_signal(58),
1457	-- request(59) =>request_signal(59),
1458	-- request(60) =>request_signal(60),
1459	-- request(61) =>request_signal(61),
1460	-- request(62) =>request_signal(62),
1461	-- request(63) =>request_signal(63),
1462	-- request(64) =>request_signal(64),
1463	-- request(65) =>request_signal(65),
1464	-- request(66) =>request_signal(66)
1465	--);
1466	--
1467	--PORT7_INPUT_PORT_MODULE: INPUT_PORT_MODULE
1468	--GENERIC MAP(number_of_ports =>11)
1469	--PORT MAP(
1470	-- data_in => Port_in(7),
1471	-- data_in_en => data_in_en(7),
1472	-- reset => reset,
1473	-- clk =>clk,
1474	-- grant(67) => grant_signal(67),
1475	-- grant(68) => grant_signal(68),
1476	-- grant(69) => grant_signal(69),
1477	-- grant(70) => grant_signal(70),
1478	-- grant(71) => grant_signal(71),
1479	-- grant(72) => grant_signal(72),
1480	-- grant(73) => grant_signal(73),
1481	-- grant(74) => grant_signal(74),
1482	-- grant(75) => grant_signal(75),
1483	-- grant(76) => grant_signal(76),
1484	-- grant(77) => grant_signal(77),
1485	-- fifo_full =>fifo_in_full(7),
1486	-- priority_rotation => priority_rotation_signal(7),
1487	-- fifo_empty => fifo_in_empty(7),
1488	-- data_out =>crossbar_in_port(8),
1489	-- data_out_pulse =>crossbar_in_pulse(7),
1490	-- request(67) =>request_signal(67),
1491	-- request(68) =>request_signal(68),
1492	-- request(69) =>request_signal(69),
1493	-- request(70) =>request_signal(70),
1494	-- request(71) =>request_signal(71),
1495	-- request(72) =>request_signal(72),
1496	-- request(73) =>request_signal(73),
1497	-- request(74) =>request_signal(74),
1498	-- request(75) =>request_signal(75),
1499	-- request(76) =>request_signal(76),
1500	-- request(77) =>request_signal(77)
1501	--);
1502	--
1503	--PORT8_INPUT_PORT_MODULE: INPUT_PORT_MODULE
1504	--GENERIC MAP(number_of_ports =>11)
1505	--PORT MAP(
1506	-- data_in => Port_in(8),
1507	-- data_in_en => data_in_en(8),
1508	-- reset => reset,
1509	-- clk =>clk,
1510	-- grant(78) => grant_signal(78),
1511	-- grant(79) => grant_signal(79),
1512	-- grant(80) => grant_signal(80),
1513	-- grant(81) => grant_signal(81),
1514	-- grant(82) => grant_signal(82),
1515	-- grant(83) => grant_signal(83),
1516	-- grant(84) => grant_signal(84),
1517	-- grant(85) => grant_signal(85),
1518	-- grant(86) => grant_signal(86),
1519	-- grant(87) => grant_signal(87),
1520	-- grant(88) => grant_signal(88),
1521	-- fifo_full =>fifo_in_full(8),
1522	-- priority_rotation => priority_rotation_signal(8),
1523	-- fifo_empty => fifo_in_empty(8),
1524	-- data_out =>crossbar_in_port(8),
1525	-- data_out_pulse =>crossbar_in_pulse(8),
1526	-- request(78) =>request_signal(78),
1527	-- request(79) =>request_signal(79),
1528	-- request(80) =>request_signal(80),
1529	-- request(81) =>request_signal(81),
1530	-- request(82) =>request_signal(82),
1531	-- request(83) =>request_signal(83),
1532	-- request(84) =>request_signal(84),
1533	-- request(85) =>request_signal(85),
1534	-- request(86) =>request_signal(86),
1535	-- request(87) =>request_signal(87),
1536	-- request(88) =>request_signal(88)
1537	--);
1538	--
1539	--PORT9_INPUT_PORT_MODULE: INPUT_PORT_MODULE
1540	--GENERIC MAP(number_of_ports =>11)
1541	--PORT MAP(
1542	-- data_in => Port_in(9),
1543	-- data_in_en => data_in_en(9),
1544	-- reset => reset,
1545	-- clk =>clk,
1546	-- grant(89) => grant_signal(89),
1547	-- grant(90) => grant_signal(90),
1548	-- grant(91) => grant_signal(91),
1549	-- grant(92) => grant_signal(92),
1550	-- grant(93) => grant_signal(93),
1551	-- grant(94) => grant_signal(94),
1552	-- grant(95) => grant_signal(95),
1553	-- grant(96) => grant_signal(96),
1554	-- grant(97) => grant_signal(97),
1555	-- grant(98) => grant_signal(98),
1556	-- grant(99) => grant_signal(99),
1557	-- fifo_full =>fifo_in_full(9),
1558	-- priority_rotation => priority_rotation_signal(9),
1559	-- fifo_empty => fifo_in_empty(9),
1560	-- data_out =>crossbar_in_port(9),
1561	-- data_out_pulse =>crossbar_in_pulse(9),
1562	-- request(89) =>request_signal(89),
1563	-- request(90) =>request_signal(90),
1564	-- request(91) =>request_signal(91),
1565	-- request(92) =>request_signal(92),
1566	-- request(93) =>request_signal(93),
1567	-- request(94) =>request_signal(94),
1568	-- request(95) =>request_signal(95),
1569	-- request(96) =>request_signal(96),
1570	-- request(97) =>request_signal(97),
1571	-- request(98) =>request_signal(98),
1572	-- request(99) =>request_signal(99)
1573	--);
1574	--
1575	--PORT10_INPUT_PORT_MODULE: INPUT_PORT_MODULE
1576	--GENERIC MAP(number_of_ports =>11)
1577	--PORT MAP(
1578	-- data_in => Port_in(10),
1579	-- data_in_en => data_in_en(10),
1580	-- reset => reset,
1581	-- clk =>clk,
1582	-- grant(1) => grant_signal(100),
1583	-- grant(2) => grant_signal(101),
1584	-- grant(3) => grant_signal(102),
1585	-- grant(4) => grant_signal(103),
1586	-- grant(5) => grant_signal(104),
1587	-- grant(6) => grant_signal(105),
1588	-- grant(7) => grant_signal(106),
1589	-- grant(8) => grant_signal(107),
1590	-- grant(9) => grant_signal(108),
1591	-- grant(10) => grant_signal(109),
1592	-- grant(11) => grant_signal(110),
1593	-- fifo_full =>fifo_in_full(10),
1594	-- priority_rotation => priority_rotation_signal(10),
1595	-- fifo_empty => fifo_in_empty(10),
1596	-- data_out =>crossbar_in_port(10),
1597	-- data_out_pulse =>crossbar_in_pulse(10),
1598	-- request(1) =>request_signal(100),
1599	-- request(2) =>request_signal(101),
1600	-- request(3) =>request_signal(102),
1601	-- request(4) =>request_signal(103),
1602	-- request(5) =>request_signal(104),
1603	-- request(6) =>request_signal(105),
1604	-- request(7) =>request_signal(106),
1605	-- request(8) =>request_signal(107),
1606	-- request(9) =>request_signal(108),
1607	-- request(10) =>request_signal(109),
1608	-- request(11) =>request_signal(110)
1609	--);
1610	--
1611	--PORT11_INPUT_PORT_MODULE: INPUT_PORT_MODULE
1612	--GENERIC MAP(number_of_ports =>11)
1613	--PORT MAP(
1614	-- data_in => Port_in(11),
1615	-- data_in_en => data_in_en(11),
1616	-- reset => reset,
1617	-- clk =>clk,
1618	-- grant(1) => grant_signal(111),
1619	-- grant(2) => grant_signal(112),
1620	-- grant(3) => grant_signal(113),
1621	-- grant(4) => grant_signal(114),
1622	-- grant(5) => grant_signal(115),
1623	-- grant(6) => grant_signal(116),
1624	-- grant(7) => grant_signal(117),
1625	-- grant(8) => grant_signal(118),
1626	-- grant(9) => grant_signal(119),
1627	-- grant(10) => grant_signal(120),
1628	-- grant(11) => grant_signal(121),
1629	-- fifo_full =>fifo_in_full(11),
1630	-- priority_rotation => priority_rotation_signal(11),
1631	-- fifo_empty => fifo_in_empty(11),
1632	-- data_out =>crossbar_in_port(11),
1633	-- data_out_pulse =>crossbar_in_pulse(11),
1634	-- request(1) =>request_signal(111),
1635	-- request(2) =>request_signal(112),
1636	-- request(3) =>request_signal(113),
1637	-- request(4) =>request_signal(114),
1638	-- request(5) =>request_signal(115),
1639	-- request(6) =>request_signal(116),
1640	-- request(7) =>request_signal(117),
1641	-- request(8) =>request_signal(118),
1642	-- request(9) =>request_signal(119),
1643	-- request(10) =>request_signal(120),
1644	-- request(11) =>request_signal(121)
1645	--);
1646	--
1647	--end generate switch11x11;
1648	--
1649	--
1650	---- switch 12 ports
1651	--switch12x12 : if number_of_ports = 12 generate
1652	--
1653	--PORT1_INPUT_PORT_MODULE: INPUT_PORT_MODULE
1654	--GENERIC MAP(number_of_ports =>12)
1655	--PORT MAP(
1656	-- data_in => Port_in(1),
1657	-- data_in_en => data_in_en(1),
1658	-- reset => reset,
1659	-- clk =>clk,
1660	-- grant(1) => grant_signal(1),
1661	-- grant(2) => grant_signal(2),
1662	-- grant(3) => grant_signal(3),
1663	-- grant(4) => grant_signal(4),
1664	-- grant(5) => grant_signal(5),
1665	-- grant(6) => grant_signal(6),
1666	-- grant(7) => grant_signal(7),
1667	-- grant(8) => grant_signal(8),
1668	-- grant(9) => grant_signal(9),
1669	-- grant(10) => grant_signal(10),
1670	-- grant(11) => grant_signal(11),
1671	-- grant(12) => grant_signal(12),
1672	-- fifo_full =>fifo_in_full(1),
1673	-- priority_rotation => priority_rotation_signal(1),
1674	-- fifo_empty => fifo_in_empty(1),
1675	-- data_out =>crossbar_in_port(1),
1676	-- data_out_pulse =>crossbar_in_pulse(1),
1677	-- request(1) =>request_signal(1),
1678	-- request(2) =>request_signal(2),
1679	-- request(3) =>request_signal(3),
1680	-- request(4) =>request_signal(4),
1681	-- request(5) =>request_signal(5),
1682	-- request(6) =>request_signal(6),
1683	-- request(7) =>request_signal(7),
1684	-- request(8) =>request_signal(8),
1685	-- request(9) =>request_signal(9),
1686	-- request(10) =>request_signal(10),
1687	-- request(11) =>request_signal(11),
1688	-- request(12) =>request_signal(12)
1689	--);
1690	--
1691	--PORT2_INPUT_PORT_MODULE: INPUT_PORT_MODULE
1692	--GENERIC MAP(number_of_ports =>12)
1693	--PORT MAP(
1694	-- data_in => Port_in(2),
1695	-- data_in_en => data_in_en(2),
1696	-- reset => reset,
1697	-- clk =>clk,
1698	-- grant(13) => grant_signal(13),
1699	-- grant(14) => grant_signal(14),
1700	-- grant(15) => grant_signal(15),
1701	-- grant(16) => grant_signal(16),
1702	-- grant(17) => grant_signal(17),
1703	-- grant(18) => grant_signal(18),
1704	-- grant(19) => grant_signal(19),
1705	-- grant(20) => grant_signal(20),
1706	-- grant(21) => grant_signal(21),
1707	-- grant(22) => grant_signal(22),
1708	-- grant(23) => grant_signal(23),
1709	-- grant(24) => grant_signal(24),
1710	-- fifo_full =>fifo_in_full(2),
1711	-- priority_rotation => priority_rotation_signal(2),
1712	-- fifo_empty => fifo_in_empty(2),
1713	-- data_out =>crossbar_in_port(2),
1714	-- data_out_pulse =>crossbar_in_pulse(2),
1715	-- request(13) =>request_signal(13),
1716	-- request(14) =>request_signal(14),
1717	-- request(15) =>request_signal(15),
1718	-- request(16) =>request_signal(16),
1719	-- request(17) =>request_signal(17),
1720	-- request(18) =>request_signal(18),
1721	-- request(19) =>request_signal(19),
1722	-- request(20) =>request_signal(20),
1723	-- request(21) =>request_signal(21),
1724	-- request(22) =>request_signal(22),
1725	-- request(23) =>request_signal(23),
1726	-- request(24) =>request_signal(24)
1727	--);
1728	--
1729	--PORT3_INPUT_PORT_MODULE: INPUT_PORT_MODULE
1730	--GENERIC MAP(number_of_ports =>12)
1731	--PORT MAP(
1732	-- data_in => Port_in(3),
1733	-- data_in_en => data_in_en(3),
1734	-- reset => reset,
1735	-- clk =>clk,
1736	-- grant(25) => grant_signal(25),
1737	-- grant(26) => grant_signal(26),
1738	-- grant(27) => grant_signal(27),
1739	-- grant(28) => grant_signal(28),
1740	-- grant(29) => grant_signal(29),
1741	-- grant(30) => grant_signal(30),
1742	-- grant(31) => grant_signal(31),
1743	-- grant(32) => grant_signal(32),
1744	-- grant(33) => grant_signal(33),
1745	-- grant(34) => grant_signal(34),
1746	-- grant(35) => grant_signal(35),
1747	-- grant(36) => grant_signal(36),
1748	-- fifo_full =>fifo_in_full(3),
1749	-- priority_rotation => priority_rotation_signal(3),
1750	-- fifo_empty => fifo_in_empty(3),
1751	-- data_out =>crossbar_in_port(3),
1752	-- data_out_pulse =>crossbar_in_pulse(3),
1753	-- request(25) =>request_signal(25),
1754	-- request(26) =>request_signal(26),
1755	-- request(27) =>request_signal(27),
1756	-- request(28) =>request_signal(28),
1757	-- request(29) =>request_signal(29),
1758	-- request(30) =>request_signal(30),
1759	-- request(31) =>request_signal(31),
1760	-- request(32) =>request_signal(32),
1761	-- request(33) =>request_signal(33),
1762	-- request(34) =>request_signal(34),
1763	-- request(35) =>request_signal(35),
1764	-- request(36) =>request_signal(36)
1765	--);
1766	--
1767	--PORT4_INPUT_PORT_MODULE: INPUT_PORT_MODULE
1768	--GENERIC MAP(number_of_ports =>12)
1769	--PORT MAP(
1770	-- data_in => Port_in(4),
1771	-- data_in_en => data_in_en(4),
1772	-- reset => reset,
1773	-- clk =>clk,
1774	-- grant(37) => grant_signal(37),
1775	-- grant(38) => grant_signal(38),
1776	-- grant(39) => grant_signal(39),
1777	-- grant(40) => grant_signal(40),
1778	-- grant(41) => grant_signal(41),
1779	-- grant(42) => grant_signal(42),
1780	-- grant(43) => grant_signal(43),
1781	-- grant(44) => grant_signal(44),
1782	-- grant(45) => grant_signal(45),
1783	-- grant(46) => grant_signal(46),
1784	-- grant(47) => grant_signal(47),
1785	-- grant(48) => grant_signal(48),
1786	-- fifo_full =>fifo_in_full(4),
1787	-- priority_rotation => priority_rotation_signal(4),
1788	-- fifo_empty => fifo_in_empty(4),
1789	-- data_out =>crossbar_in_port(4),
1790	-- data_out_pulse =>crossbar_in_pulse(4),
1791	-- request(37) =>request_signal(37),
1792	-- request(38) =>request_signal(38),
1793	-- request(39) =>request_signal(39),
1794	-- request(40) =>request_signal(40),
1795	-- request(41) =>request_signal(41),
1796	-- request(42) =>request_signal(42),
1797	-- request(43) =>request_signal(43),
1798	-- request(44) =>request_signal(44),
1799	-- request(45) =>request_signal(45),
1800	-- request(46) =>request_signal(46),
1801	-- request(47) =>request_signal(47),
1802	-- request(48) =>request_signal(48)
1803	--);
1804	--
1805	--PORT5_INPUT_PORT_MODULE: INPUT_PORT_MODULE
1806	--GENERIC MAP(number_of_ports =>12)
1807	--PORT MAP(
1808	-- data_in => Port_in(5),
1809	-- data_in_en => data_in_en(5),
1810	-- reset => reset,
1811	-- clk =>clk,
1812	-- grant(49) => grant_signal(49),
1813	-- grant(50) => grant_signal(50),
1814	-- grant(51) => grant_signal(51),
1815	-- grant(52) => grant_signal(52),
1816	-- grant(53) => grant_signal(53),
1817	-- grant(54) => grant_signal(54),
1818	-- grant(55) => grant_signal(55),
1819	-- grant(56) => grant_signal(56),
1820	-- grant(57) => grant_signal(57),
1821	-- grant(58) => grant_signal(58),
1822	-- grant(59) => grant_signal(59),
1823	-- grant(60) => grant_signal(60),
1824	-- fifo_full =>fifo_in_full(5),
1825	-- priority_rotation => priority_rotation_signal(5),
1826	-- fifo_empty => fifo_in_empty(5),
1827	-- data_out =>crossbar_in_port(5),
1828	-- data_out_pulse =>crossbar_in_pulse(5),
1829	-- request(49) =>request_signal(49),
1830	-- request(50) =>request_signal(50),
1831	-- request(51) =>request_signal(51),
1832	-- request(52) =>request_signal(52),
1833	-- request(53) =>request_signal(53),
1834	-- request(54) =>request_signal(54),
1835	-- request(55) =>request_signal(55),
1836	-- request(56) =>request_signal(56),
1837	-- request(57) =>request_signal(57),
1838	-- request(58) =>request_signal(58),
1839	-- request(59) =>request_signal(59),
1840	-- request(60) =>request_signal(60)
1841	--);
1842	--
1843	--PORT6_INPUT_PORT_MODULE: INPUT_PORT_MODULE
1844	--GENERIC MAP(number_of_ports =>12)
1845	--PORT MAP(
1846	-- data_in => Port_in(6),
1847	-- data_in_en => data_in_en(6),
1848	-- reset => reset,
1849	-- clk =>clk,
1850	-- grant(61) => grant_signal(61),
1851	-- grant(62) => grant_signal(62),
1852	-- grant(63) => grant_signal(63),
1853	-- grant(64) => grant_signal(64),
1854	-- grant(65) => grant_signal(65),
1855	-- grant(66) => grant_signal(66),
1856	-- grant(67) => grant_signal(67),
1857	-- grant(68) => grant_signal(68),
1858	-- grant(69) => grant_signal(69),
1859	-- grant(70) => grant_signal(70),
1860	-- grant(71) => grant_signal(71),
1861	-- grant(72) => grant_signal(72),
1862	-- fifo_full =>fifo_in_full(6),
1863	-- priority_rotation => priority_rotation_signal(6),
1864	-- fifo_empty => fifo_in_empty(6),
1865	-- data_out =>crossbar_in_port(6),
1866	-- data_out_pulse =>crossbar_in_pulse(6),
1867	-- request(61) =>request_signal(61),
1868	-- request(62) =>request_signal(62),
1869	-- request(63) =>request_signal(63),
1870	-- request(64) =>request_signal(64),
1871	-- request(65) =>request_signal(65),
1872	-- request(66) =>request_signal(66),
1873	-- request(67) =>request_signal(67),
1874	-- request(68) =>request_signal(68),
1875	-- request(69) =>request_signal(69),
1876	-- request(70) =>request_signal(70),
1877	-- request(71) =>request_signal(71),
1878	-- request(72) =>request_signal(72)
1879	--);
1880	--
1881	--PORT7_INPUT_PORT_MODULE: INPUT_PORT_MODULE
1882	--GENERIC MAP(number_of_ports =>12)
1883	--PORT MAP(
1884	-- data_in => Port_in(7),
1885	-- data_in_en => data_in_en(7),
1886	-- reset => reset,
1887	-- clk =>clk,
1888	-- grant(73) => grant_signal(73),
1889	-- grant(74) => grant_signal(74),
1890	-- grant(75) => grant_signal(75),
1891	-- grant(76) => grant_signal(76),
1892	-- grant(77) => grant_signal(77),
1893	-- grant(78) => grant_signal(78),
1894	-- grant(79) => grant_signal(79),
1895	-- grant(80) => grant_signal(80),
1896	-- grant(81) => grant_signal(81),
1897	-- grant(82) => grant_signal(82),
1898	-- grant(83) => grant_signal(83),
1899	-- grant(84) => grant_signal(84),
1900	-- fifo_full =>fifo_in_full(7),
1901	-- priority_rotation => priority_rotation_signal(7),
1902	-- fifo_empty => fifo_in_empty(7),
1903	-- data_out =>crossbar_in_port(7),
1904	-- data_out_pulse =>crossbar_in_pulse(7),
1905	-- request(73) =>request_signal(73),
1906	-- request(74) =>request_signal(74),
1907	-- request(75) =>request_signal(75),
1908	-- request(76) =>request_signal(76),
1909	-- request(77) =>request_signal(77),
1910	-- request(78) =>request_signal(78),
1911	-- request(79) =>request_signal(79),
1912	-- request(80) =>request_signal(80),
1913	-- request(81) =>request_signal(81),
1914	-- request(82) =>request_signal(82),
1915	-- request(83) =>request_signal(83),
1916	-- request(84) =>request_signal(84)
1917	--);
1918	--
1919	--PORT8_INPUT_PORT_MODULE: INPUT_PORT_MODULE
1920	--GENERIC MAP(number_of_ports =>12)
1921	--PORT MAP(
1922	-- data_in => Port_in(8),
1923	-- data_in_en => data_in_en(8),
1924	-- reset => reset,
1925	-- clk =>clk,
1926	-- grant(85) => grant_signal(85),
1927	-- grant(86) => grant_signal(86),
1928	-- grant(87) => grant_signal(87),
1929	-- grant(88) => grant_signal(88),
1930	-- grant(89) => grant_signal(89),
1931	-- grant(90) => grant_signal(90),
1932	-- grant(91) => grant_signal(91),
1933	-- grant(92) => grant_signal(92),
1934	-- grant(93) => grant_signal(93),
1935	-- grant(94) => grant_signal(94),
1936	-- grant(95) => grant_signal(95),
1937	-- grant(96) => grant_signal(96),
1938	-- fifo_full =>fifo_in_full(8),
1939	-- priority_rotation => priority_rotation_signal(8),
1940	-- fifo_empty => fifo_in_empty(8),
1941	-- data_out =>crossbar_in_port(8),
1942	-- data_out_pulse =>crossbar_in_pulse(8),
1943	-- request(85) =>request_signal(85),
1944	-- request(86) =>request_signal(86),
1945	-- request(87) =>request_signal(87),
1946	-- request(88) =>request_signal(88),
1947	-- request(89) =>request_signal(89),
1948	-- request(90) =>request_signal(90),
1949	-- request(91) =>request_signal(91),
1950	-- request(92) =>request_signal(92),
1951	-- request(93) =>request_signal(93),
1952	-- request(94) =>request_signal(94),
1953	-- request(95) =>request_signal(95),
1954	-- request(96) =>request_signal(96)
1955	--);
1956	--
1957	--PORT9_INPUT_PORT_MODULE: INPUT_PORT_MODULE
1958	--GENERIC MAP(number_of_ports =>12)
1959	--PORT MAP(
1960	-- data_in => Port_in(9),
1961	-- data_in_en => data_in_en(9),
1962	-- reset => reset,
1963	-- clk =>clk,
1964	-- grant(97) => grant_signal(97),
1965	-- grant(98) => grant_signal(98),
1966	-- grant(99) => grant_signal(99),
1967	-- grant(100) => grant_signal(100),
1968	-- grant(101) => grant_signal(101),
1969	-- grant(102) => grant_signal(102),
1970	-- grant(103) => grant_signal(103),
1971	-- grant(104) => grant_signal(104),
1972	-- grant(105) => grant_signal(105),
1973	-- grant(106) => grant_signal(106),
1974	-- grant(107) => grant_signal(107),
1975	-- grant(108) => grant_signal(108),
1976	-- fifo_full =>fifo_in_full(9),
1977	-- priority_rotation => priority_rotation_signal(9),
1978	-- fifo_empty => fifo_in_empty(9),
1979	-- data_out =>crossbar_in_port(9),
1980	-- data_out_pulse =>crossbar_in_pulse(9),
1981	-- request(97) =>request_signal(97),
1982	-- request(98) =>request_signal(98),
1983	-- request(99) =>request_signal(99),
1984	-- request(100) =>request_signal(100),
1985	-- request(101) =>request_signal(101),
1986	-- request(102) =>request_signal(102),
1987	-- request(103) =>request_signal(103),
1988	-- request(104) =>request_signal(104),
1989	-- request(105) =>request_signal(105),
1990	-- request(106) =>request_signal(106),
1991	-- request(107) =>request_signal(107),
1992	-- request(108) =>request_signal(108)
1993	--);
1994	--
1995	--PORT10_INPUT_PORT_MODULE: INPUT_PORT_MODULE
1996	--GENERIC MAP(number_of_ports =>12)
1997	--PORT MAP(
1998	-- data_in => Port_in(10),
1999	-- data_in_en => data_in_en(10),
2000	-- reset => reset,
2001	-- clk =>clk,
2002	-- grant(1) => grant_signal(109),
2003	-- grant(2) => grant_signal(110),
2004	-- grant(3) => grant_signal(111),
2005	-- grant(4) => grant_signal(112),
2006	-- grant(5) => grant_signal(113),
2007	-- grant(6) => grant_signal(114),
2008	-- grant(7) => grant_signal(115),
2009	-- grant(8) => grant_signal(116),
2010	-- grant(9) => grant_signal(117),
2011	-- grant(10) => grant_signal(118),
2012	-- grant(11) => grant_signal(119),
2013	-- grant(12) => grant_signal(120),
2014	-- fifo_full =>fifo_in_full(10),
2015	-- priority_rotation => priority_rotation_signal(10),
2016	-- fifo_empty => fifo_in_empty(10),
2017	-- data_out =>crossbar_in_port(10),
2018	-- data_out_pulse =>crossbar_in_pulse(10),
2019	-- request(109) =>request_signal(109),
2020	-- request(110) =>request_signal(110),
2021	-- request(111) =>request_signal(111),
2022	-- request(112) =>request_signal(112),
2023	-- request(113) =>request_signal(113),
2024	-- request(114) =>request_signal(114),
2025	-- request(115) =>request_signal(115),
2026	-- request(116) =>request_signal(116),
2027	-- request(117) =>request_signal(117),
2028	-- request(118) =>request_signal(118),
2029	-- request(119) =>request_signal(119),
2030	-- request(120) =>request_signal(120)
2031	--);
2032	--
2033	--PORT11_INPUT_PORT_MODULE: INPUT_PORT_MODULE
2034	--GENERIC MAP(number_of_ports =>12)
2035	--PORT MAP(
2036	-- data_in => Port_in(11),
2037	-- data_in_en => data_in_en(11),
2038	-- reset => reset,
2039	-- clk =>clk,
2040	-- grant(1) => grant_signal(121),
2041	-- grant(2) => grant_signal(122),
2042	-- grant(3) => grant_signal(123),
2043	-- grant(4) => grant_signal(124),
2044	-- grant(5) => grant_signal(125),
2045	-- grant(6) => grant_signal(126),
2046	-- grant(7) => grant_signal(127),
2047	-- grant(8) => grant_signal(128),
2048	-- grant(9) => grant_signal(129),
2049	-- grant(10) => grant_signal(130),
2050	-- grant(11) => grant_signal(131),
2051	-- grant(12) => grant_signal(132),
2052	-- fifo_full =>fifo_in_full(11),
2053	-- priority_rotation => priority_rotation_signal(11),
2054	-- fifo_empty => fifo_in_empty(11),
2055	-- data_out =>crossbar_in_port(11),
2056	-- data_out_pulse =>crossbar_in_pulse(11),
2057	-- request(121) =>request_signal(121),
2058	-- request(122) =>request_signal(122),
2059	-- request(123) =>request_signal(123),
2060	-- request(124) =>request_signal(124),
2061	-- request(125) =>request_signal(125),
2062	-- request(126) =>request_signal(126),
2063	-- request(127) =>request_signal(127),
2064	-- request(128) =>request_signal(128),
2065	-- request(129) =>request_signal(129),
2066	-- request(130) =>request_signal(130),
2067	-- request(131) =>request_signal(131),
2068	-- request(132) =>request_signal(132)
2069	--);
2070	--
2071	--PORT12_INPUT_PORT_MODULE: INPUT_PORT_MODULE
2072	--GENERIC MAP(number_of_ports =>12)
2073	--PORT MAP(
2074	-- data_in => Port_in(12),
2075	-- data_in_en => data_in_en(12),
2076	-- reset => reset,
2077	-- clk =>clk,
2078	-- grant(133) => grant_signal(133),
2079	-- grant(134) => grant_signal(134),
2080	-- grant(135) => grant_signal(135),
2081	-- grant(136) => grant_signal(136),
2082	-- grant(137) => grant_signal(137),
2083	-- grant(138) => grant_signal(138),
2084	-- grant(139) => grant_signal(139),
2085	-- grant(140) => grant_signal(140),
2086	-- grant(141) => grant_signal(141),
2087	-- grant(142) => grant_signal(142),
2088	-- grant(143) => grant_signal(143),
2089	-- grant(144) => grant_signal(144),
2090	-- fifo_full =>fifo_in_full(12),
2091	-- priority_rotation => priority_rotation_signal(12),
2092	-- fifo_empty => fifo_in_empty(12),
2093	-- data_out =>crossbar_in_port(12),
2094	-- data_out_pulse =>crossbar_in_pulse(12),
2095	-- request(133) =>request_signal(133),
2096	-- request(134) =>request_signal(134),
2097	-- request(135) =>request_signal(135),
2098	-- request(136) =>request_signal(136),
2099	-- request(137) =>request_signal(137),
2100	-- request(138) =>request_signal(138),
2101	-- request(139) =>request_signal(139),
2102	-- request(140) =>request_signal(140),
2103	-- request(141) =>request_signal(141),
2104	-- request(142) =>request_signal(142),
2105	-- request(143) =>request_signal(143),
2106	-- request(144) =>request_signal(144)
2107	--);
2108	--
2109	--end generate switch12x12;
2110	--
2111	--
2112	---- switch 13 ports
2113	--switch13x13 : if number_of_ports = 13 generate
2114	--
2115	--PORT1_INPUT_PORT_MODULE: INPUT_PORT_MODULE
2116	--GENERIC MAP(number_of_ports =>13)
2117	--PORT MAP(
2118	-- data_in => Port_in(1),
2119	-- data_in_en => data_in_en(1),
2120	-- reset => reset,
2121	-- clk =>clk,
2122	-- grant(1) => grant_signal(1),
2123	-- grant(2) => grant_signal(2),
2124	-- grant(3) => grant_signal(3),
2125	-- grant(4) => grant_signal(4),
2126	-- grant(5) => grant_signal(5),
2127	-- grant(6) => grant_signal(6),
2128	-- grant(7) => grant_signal(7),
2129	-- grant(8) => grant_signal(8),
2130	-- grant(9) => grant_signal(9),
2131	-- grant(10) => grant_signal(10),
2132	-- grant(11) => grant_signal(11),
2133	-- grant(12) => grant_signal(12),
2134	-- grant(13) => grant_signal(13),
2135	-- fifo_full =>fifo_in_full(1),
2136	-- priority_rotation => priority_rotation_signal(1),
2137	-- fifo_empty => fifo_in_empty(1),
2138	-- data_out =>crossbar_in_port(1),
2139	-- data_out_pulse =>crossbar_in_pulse(1),
2140	-- request(1) =>request_signal(1),
2141	-- request(2) =>request_signal(2),
2142	-- request(3) =>request_signal(3),
2143	-- request(4) =>request_signal(4),
2144	-- request(5) =>request_signal(5),
2145	-- request(6) =>request_signal(6),
2146	-- request(7) =>request_signal(7),
2147	-- request(8) =>request_signal(8),
2148	-- request(9) =>request_signal(9),
2149	-- request(10) =>request_signal(10),
2150	-- request(11) =>request_signal(11),
2151	-- request(12) =>request_signal(12),
2152	-- request(13) =>request_signal(13)
2153	--);
2154	--
2155	--PORT2_INPUT_PORT_MODULE: INPUT_PORT_MODULE
2156	--GENERIC MAP(number_of_ports =>13)
2157	--PORT MAP(
2158	-- data_in => Port_in(2),
2159	-- data_in_en => data_in_en(2),
2160	-- reset => reset,
2161	-- clk =>clk,
2162	-- grant(14) => grant_signal(14),
2163	-- grant(15) => grant_signal(15),
2164	-- grant(16) => grant_signal(16),
2165	-- grant(17) => grant_signal(17),
2166	-- grant(18) => grant_signal(18),
2167	-- grant(19) => grant_signal(19),
2168	-- grant(20) => grant_signal(20),
2169	-- grant(21) => grant_signal(21),
2170	-- grant(22) => grant_signal(22),
2171	-- grant(23) => grant_signal(23),
2172	-- grant(24) => grant_signal(24),
2173	-- grant(25) => grant_signal(25),
2174	-- grant(26) => grant_signal(26),
2175	-- fifo_full =>fifo_in_full(2),
2176	-- priority_rotation => priority_rotation_signal(2),
2177	-- fifo_empty => fifo_in_empty(2),
2178	-- data_out =>crossbar_in_port(2),
2179	-- data_out_pulse =>crossbar_in_pulse(2),
2180	-- request(14) =>request_signal(14),
2181	-- request(15) =>request_signal(15),
2182	-- request(16) =>request_signal(16),
2183	-- request(17) =>request_signal(17),
2184	-- request(18) =>request_signal(18),
2185	-- request(19) =>request_signal(19),
2186	-- request(20) =>request_signal(20),
2187	-- request(21) =>request_signal(21),
2188	-- request(22) =>request_signal(22),
2189	-- request(23) =>request_signal(23),
2190	-- request(24) =>request_signal(24),
2191	-- request(25) =>request_signal(25),
2192	-- request(26) =>request_signal(26)
2193	--);
2194
2195	--PORT3_INPUT_PORT_MODULE: INPUT_PORT_MODULE
2196	--GENERIC MAP(number_of_ports =>13)
2197	--PORT MAP(
2198	-- data_in => Port_in(3),
2199	-- data_in_en => data_in_en(3),
2200	-- reset => reset,
2201	-- clk =>clk,
2202	-- grant(27) => grant_signal(27),
2203	-- grant(28) => grant_signal(28),
2204	-- grant(29) => grant_signal(29),
2205	-- grant(30) => grant_signal(30),
2206	-- grant(31) => grant_signal(31),
2207	-- grant(32) => grant_signal(32),
2208	-- grant(33) => grant_signal(33),
2209	-- grant(34) => grant_signal(34),
2210	-- grant(35) => grant_signal(35),
2211	-- grant(36) => grant_signal(36),
2212	-- grant(37) => grant_signal(37),
2213	-- grant(38) => grant_signal(38),
2214	-- grant(39) => grant_signal(39),
2215	-- fifo_full =>fifo_in_full(3),
2216	-- priority_rotation => priority_rotation_signal(3),
2217	-- fifo_empty => fifo_in_empty(3),
2218	-- data_out =>crossbar_in_port(3),
2219	-- data_out_pulse =>crossbar_in_pulse(3),
2220	-- request(27) =>request_signal(27),
2221	-- request(28) =>request_signal(28),
2222	-- request(29) =>request_signal(29),
2223	-- request(30) =>request_signal(30),
2224	-- request(31) =>request_signal(31),
2225	-- request(32) =>request_signal(32),
2226	-- request(33) =>request_signal(33),
2227	-- request(34) =>request_signal(34),
2228	-- request(35) =>request_signal(35),
2229	-- request(36) =>request_signal(36),
2230	-- request(37) =>request_signal(37),
2231	-- request(38) =>request_signal(38),
2232	-- request(39) =>request_signal(39)
2233	--);
2234	--
2235	--PORT4_INPUT_PORT_MODULE: INPUT_PORT_MODULE
2236	--GENERIC MAP(number_of_ports =>13)
2237	--PORT MAP(
2238	-- data_in => Port_in(4),
2239	-- data_in_en => data_in_en(4),
2240	-- reset => reset,
2241	-- clk =>clk,
2242	-- grant(40) => grant_signal(40),
2243	-- grant(41) => grant_signal(41),
2244	-- grant(42) => grant_signal(42),
2245	-- grant(43) => grant_signal(43),
2246	-- grant(44) => grant_signal(44),
2247	-- grant(45) => grant_signal(45),
2248	-- grant(46) => grant_signal(46),
2249	-- grant(47) => grant_signal(47),
2250	-- grant(48) => grant_signal(48),
2251	-- grant(49) => grant_signal(49),
2252	-- grant(50) => grant_signal(50),
2253	-- grant(51) => grant_signal(51),
2254	-- grant(52) => grant_signal(52),
2255	-- fifo_full =>fifo_in_full(4),
2256	-- priority_rotation => priority_rotation_signal(4),
2257	-- fifo_empty => fifo_in_empty(4),
2258	-- data_out =>crossbar_in_port(4),
2259	-- data_out_pulse =>crossbar_in_pulse(4),
2260	-- request(40) =>request_signal(40),
2261	-- request(41) =>request_signal(41),
2262	-- request(42) =>request_signal(42),
2263	-- request(43) =>request_signal(43),
2264	-- request(44) =>request_signal(44),
2265	-- request(45) =>request_signal(45),
2266	-- request(46) =>request_signal(46),
2267	-- request(47) =>request_signal(47),
2268	-- request(48) =>request_signal(48),
2269	-- request(49) =>request_signal(49),
2270	-- request(50) =>request_signal(50),
2271	-- request(51) =>request_signal(51),
2272	-- request(52) =>request_signal(52)
2273	--);
2274	--
2275	--PORT5_INPUT_PORT_MODULE: INPUT_PORT_MODULE
2276	--GENERIC MAP(number_of_ports =>13)
2277	--PORT MAP(
2278	-- data_in => Port_in(5),
2279	-- data_in_en => data_in_en(5),
2280	-- reset => reset,
2281	-- clk =>clk,
2282	-- grant(53) => grant_signal(53),
2283	-- grant(54) => grant_signal(54),
2284	-- grant(55) => grant_signal(55),
2285	-- grant(56) => grant_signal(56),
2286	-- grant(57) => grant_signal(57),
2287	-- grant(58) => grant_signal(58),
2288	-- grant(59) => grant_signal(59),
2289	-- grant(60) => grant_signal(60),
2290	-- grant(61) => grant_signal(61),
2291	-- grant(62) => grant_signal(62),
2292	-- grant(63) => grant_signal(63),
2293	-- grant(64) => grant_signal(64),
2294	-- grant(65) => grant_signal(65),
2295	-- fifo_full =>fifo_in_full(5),
2296	-- priority_rotation => priority_rotation_signal(5),
2297	-- fifo_empty => fifo_in_empty(5),
2298	-- data_out =>crossbar_in_port(5),
2299	-- data_out_pulse =>crossbar_in_pulse(5),
2300	-- request(53) =>request_signal(53),
2301	-- request(54) =>request_signal(54),
2302	-- request(55) =>request_signal(55),
2303	-- request(56) =>request_signal(56),
2304	-- request(57) =>request_signal(57),
2305	-- request(58) =>request_signal(58),
2306	-- request(59) =>request_signal(59),
2307	-- request(60) =>request_signal(60),
2308	-- request(61) =>request_signal(61),
2309	-- request(62) =>request_signal(62),
2310	-- request(63) =>request_signal(63),
2311	-- request(64) =>request_signal(64),
2312	-- request(65) =>request_signal(65)
2313	--);
2314	--
2315	--PORT6_INPUT_PORT_MODULE: INPUT_PORT_MODULE
2316	--GENERIC MAP(number_of_ports =>13)
2317	--PORT MAP(
2318	-- data_in => Port_in(6),
2319	-- data_in_en => data_in_en(6),
2320	-- reset => reset,
2321	-- clk =>clk,
2322	-- grant(66) => grant_signal(66),
2323	-- grant(67) => grant_signal(67),
2324	-- grant(68) => grant_signal(68),
2325	-- grant(69) => grant_signal(69),
2326	-- grant(70) => grant_signal(70),
2327	-- grant(71) => grant_signal(71),
2328	-- grant(72) => grant_signal(72),
2329	-- grant(73) => grant_signal(73),
2330	-- grant(74) => grant_signal(74),
2331	-- grant(75) => grant_signal(75),
2332	-- grant(76) => grant_signal(76),
2333	-- grant(77) => grant_signal(77),
2334	-- grant(78) => grant_signal(78),
2335	-- fifo_full =>fifo_in_full(6),
2336	-- priority_rotation => priority_rotation_signal(6),
2337	-- fifo_empty => fifo_in_empty(6),
2338	-- data_out =>crossbar_in_port(6),
2339	-- data_out_pulse =>crossbar_in_pulse(6),
2340	-- request(66) =>request_signal(66),
2341	-- request(67) =>request_signal(67),
2342	-- request(68) =>request_signal(68),
2343	-- request(69) =>request_signal(69),
2344	-- request(70) =>request_signal(70),
2345	-- request(71) =>request_signal(71),
2346	-- request(72) =>request_signal(72),
2347	-- request(73) =>request_signal(73),
2348	-- request(74) =>request_signal(74),
2349	-- request(75) =>request_signal(75),
2350	-- request(76) =>request_signal(76),
2351	-- request(77) =>request_signal(77),
2352	-- request(78) =>request_signal(78)
2353	--);
2354	--
2355	--PORT7_INPUT_PORT_MODULE: INPUT_PORT_MODULE
2356	--GENERIC MAP(number_of_ports =>13)
2357	--PORT MAP(
2358	-- data_in => Port_in(7),
2359	-- data_in_en => data_in_en(7),
2360	-- reset => reset,
2361	-- clk =>clk,
2362	-- grant(79) => grant_signal(79),
2363	-- grant(80) => grant_signal(80),
2364	-- grant(81) => grant_signal(81),
2365	-- grant(82) => grant_signal(82),
2366	-- grant(83) => grant_signal(83),
2367	-- grant(84) => grant_signal(84),
2368	-- grant(85) => grant_signal(85),
2369	-- grant(86) => grant_signal(86),
2370	-- grant(87) => grant_signal(87),
2371	-- grant(88) => grant_signal(88),
2372	-- grant(89) => grant_signal(89),
2373	-- grant(90) => grant_signal(90),
2374	-- grant(91) => grant_signal(91),
2375	-- fifo_full =>fifo_in_full(7),
2376	-- priority_rotation => priority_rotation_signal(7),
2377	-- fifo_empty => fifo_in_empty(7),
2378	-- data_out =>crossbar_in_port(7),
2379	-- data_out_pulse =>crossbar_in_pulse(7),
2380	-- request(79) =>request_signal(79),
2381	-- request(80) =>request_signal(80),
2382	-- request(81) =>request_signal(81),
2383	-- request(82) =>request_signal(82),
2384	-- request(83) =>request_signal(83),
2385	-- request(84) =>request_signal(84),
2386	-- request(85) =>request_signal(85),
2387	-- request(86) =>request_signal(86),
2388	-- request(87) =>request_signal(87),
2389	-- request(88) =>request_signal(88),
2390	-- request(89) =>request_signal(89),
2391	-- request(90) =>request_signal(90),
2392	-- request(91) =>request_signal(91)
2393	--);
2394	--
2395	--PORT8_INPUT_PORT_MODULE: INPUT_PORT_MODULE
2396	--GENERIC MAP(number_of_ports =>13)
2397	--PORT MAP(
2398	-- data_in => Port_in(8),
2399	-- data_in_en => data_in_en(8),
2400	-- reset => reset,
2401	-- clk =>clk,
2402	-- grant(92) => grant_signal(92),
2403	-- grant(93) => grant_signal(93),
2404	-- grant(94) => grant_signal(94),
2405	-- grant(95) => grant_signal(95),
2406	-- grant(96) => grant_signal(96),
2407	-- grant(97) => grant_signal(97),
2408	-- grant(98) => grant_signal(98),
2409	-- grant(99) => grant_signal(99),
2410	-- grant(100) => grant_signal(100),
2411	-- grant(101) => grant_signal(101),
2412	-- grant(102) => grant_signal(102),
2413	-- grant(103) => grant_signal(103),
2414	-- grant(104) => grant_signal(104),
2415	-- fifo_full =>fifo_in_full(8),
2416	-- priority_rotation => priority_rotation_signal(8),
2417	-- fifo_empty => fifo_in_empty(8),
2418	-- data_out =>crossbar_in_port(8),
2419	-- data_out_pulse =>crossbar_in_pulse(8),
2420	-- request(92) =>request_signal(92),
2421	-- request(93) =>request_signal(93),
2422	-- request(94) =>request_signal(94),
2423	-- request(95) =>request_signal(95),
2424	-- request(96) =>request_signal(96),
2425	-- request(97) =>request_signal(97),
2426	-- request(98) =>request_signal(98),
2427	-- request(99) =>request_signal(99),
2428	-- request(100) =>request_signal(100),
2429	-- request(101) =>request_signal(101),
2430	-- request(102) =>request_signal(102),
2431	-- request(103) =>request_signal(103),
2432	-- request(104) =>request_signal(104)
2433	--);
2434	--
2435	--PORT9_INPUT_PORT_MODULE: INPUT_PORT_MODULE
2436	--GENERIC MAP(number_of_ports =>13)
2437	--PORT MAP(
2438	-- data_in => Port_in(9),
2439	-- data_in_en => data_in_en(9),
2440	-- reset => reset,
2441	-- clk =>clk,
2442	-- grant(1) => grant_signal(105),
2443	-- grant(2) => grant_signal(106),
2444	-- grant(3) => grant_signal(107),
2445	-- grant(4) => grant_signal(108),
2446	-- grant(5) => grant_signal(109),
2447	-- grant(6) => grant_signal(110),
2448	-- grant(7) => grant_signal(111),
2449	-- grant(8) => grant_signal(112),
2450	-- grant(9) => grant_signal(113),
2451	-- grant(10) => grant_signal(114),
2452	-- grant(11) => grant_signal(115),
2453	-- grant(12) => grant_signal(116),
2454	-- grant(13) => grant_signal(117),
2455	-- fifo_full =>fifo_in_full(9),
2456	-- priority_rotation => priority_rotation_signal(9),
2457	-- fifo_empty => fifo_in_empty(9),
2458	-- data_out =>crossbar_in_port(9),
2459	-- data_out_pulse =>crossbar_in_pulse(9),
2460	-- request(105) =>request_signal(105),
2461	-- request(106) =>request_signal(106),
2462	-- request(107) =>request_signal(107),
2463	-- request(108) =>request_signal(108),
2464	-- request(109) =>request_signal(109),
2465	-- request(110) =>request_signal(110),
2466	-- request(111) =>request_signal(111),
2467	-- request(112) =>request_signal(112),
2468	-- request(113) =>request_signal(113),
2469	-- request(114) =>request_signal(114),
2470	-- request(115) =>request_signal(115),
2471	-- request(116) =>request_signal(116),
2472	-- request(117) =>request_signal(117)
2473	--);
2474	--
2475	--PORT10_INPUT_PORT_MODULE: INPUT_PORT_MODULE
2476	--GENERIC MAP(number_of_ports =>13)
2477	--PORT MAP(
2478	-- data_in => Port_in(10),
2479	-- data_in_en => data_in_en(10),
2480	-- reset => reset,
2481	-- clk =>clk,
2482	-- grant(1) => grant_signal(118),
2483	-- grant(2) => grant_signal(119),
2484	-- grant(3) => grant_signal(120),
2485	-- grant(4) => grant_signal(121),
2486	-- grant(5) => grant_signal(122),
2487	-- grant(6) => grant_signal(123),
2488	-- grant(7) => grant_signal(124),
2489	-- grant(8) => grant_signal(125),
2490	-- grant(9) => grant_signal(126),
2491	-- grant(10) => grant_signal(127),
2492	-- grant(11) => grant_signal(128),
2493	-- grant(12) => grant_signal(129),
2494	-- grant(13) => grant_signal(130),
2495	-- fifo_full =>fifo_in_full(10),
2496	-- priority_rotation => priority_rotation_signal(10),
2497	-- fifo_empty => fifo_in_empty(10),
2498	-- data_out =>crossbar_in_port(10),
2499	-- data_out_pulse =>crossbar_in_pulse(10),
2500	-- request(1) =>request_signal(118),
2501	-- request(2) =>request_signal(119),
2502	-- request(3) =>request_signal(120),
2503	-- request(4) =>request_signal(121),
2504	-- request(5) =>request_signal(122),
2505	-- request(6) =>request_signal(123),
2506	-- request(7) =>request_signal(124),
2507	-- request(8) =>request_signal(125),
2508	-- request(9) =>request_signal(126),
2509	-- request(10) =>request_signal(127),
2510	-- request(11) =>request_signal(128),
2511	-- request(12) =>request_signal(129),
2512	-- request(13) =>request_signal(130)
2513	--);
2514	--
2515	--PORT11_INPUT_PORT_MODULE: INPUT_PORT_MODULE
2516	--GENERIC MAP(number_of_ports =>13)
2517	--PORT MAP(
2518	-- data_in => Port_in(11),
2519	-- data_in_en => data_in_en(11),
2520	-- reset => reset,
2521	-- clk =>clk,
2522	-- grant(1) => grant_signal(131),
2523	-- grant(2) => grant_signal(132),
2524	-- grant(3) => grant_signal(133),
2525	-- grant(4) => grant_signal(134),
2526	-- grant(5) => grant_signal(135),
2527	-- grant(6) => grant_signal(136),
2528	-- grant(7) => grant_signal(137),
2529	-- grant(8) => grant_signal(138),
2530	-- grant(9) => grant_signal(139),
2531	-- grant(10) => grant_signal(140),
2532	-- grant(11) => grant_signal(141),
2533	-- grant(12) => grant_signal(142),
2534	-- grant(13) => grant_signal(143),
2535	-- fifo_full =>fifo_in_full(11),
2536	-- priority_rotation => priority_rotation_signal(11),
2537	-- fifo_empty => fifo_in_empty(11),
2538	-- data_out =>crossbar_in_port(11),
2539	-- data_out_pulse =>crossbar_in_pulse(11),
2540	-- request(1) =>request_signal(131),
2541	-- request(2) =>request_signal(132),
2542	-- request(3) =>request_signal(133),
2543	-- request(4) =>request_signal(134),
2544	-- request(5) =>request_signal(135),
2545	-- request(6) =>request_signal(136),
2546	-- request(7) =>request_signal(137),
2547	-- request(8) =>request_signal(138),
2548	-- request(9) =>request_signal(139),
2549	-- request(10) =>request_signal(140),
2550	-- request(11) =>request_signal(141),
2551	-- request(12) =>request_signal(142),
2552	-- request(13) =>request_signal(143)
2553	--);
2554	--
2555	--PORT12_INPUT_PORT_MODULE: INPUT_PORT_MODULE
2556	--GENERIC MAP(number_of_ports =>13)
2557	--PORT MAP(
2558	-- data_in => Port_in(12),
2559	-- data_in_en => data_in_en(12),
2560	-- reset => reset,
2561	-- clk =>clk,
2562	-- grant(1) => grant_signal(144),
2563	-- grant(2) => grant_signal(145),
2564	-- grant(3) => grant_signal(146),
2565	-- grant(4) => grant_signal(147),
2566	-- grant(5) => grant_signal(148),
2567	-- grant(6) => grant_signal(149),
2568	-- grant(7) => grant_signal(150),
2569	-- grant(8) => grant_signal(151),
2570	-- grant(9) => grant_signal(152),
2571	-- grant(10) => grant_signal(153),
2572	-- grant(11) => grant_signal(154),
2573	-- grant(12) => grant_signal(155),
2574	-- grant(13) => grant_signal(156),
2575	-- fifo_full =>fifo_in_full(12),
2576	-- priority_rotation => priority_rotation_signal(12),
2577	-- fifo_empty => fifo_in_empty(12),
2578	-- data_out =>crossbar_in_port(12),
2579	-- data_out_pulse =>crossbar_in_pulse(12),
2580	-- request(1) =>request_signal(144),
2581	-- request(2) =>request_signal(145),
2582	-- request(3) =>request_signal(146),
2583	-- request(4) =>request_signal(147),
2584	-- request(5) =>request_signal(148),
2585	-- request(6) =>request_signal(149),
2586	-- request(7) =>request_signal(150),
2587	-- request(8) =>request_signal(151),
2588	-- request(9) =>request_signal(152),
2589	-- request(10) =>request_signal(153),
2590	-- request(11) =>request_signal(154),
2591	-- request(12) =>request_signal(155),
2592	-- request(13) =>request_signal(156)
2593	--);
2594	--
2595	--PORT13_INPUT_PORT_MODULE: INPUT_PORT_MODULE
2596	--GENERIC MAP(number_of_ports =>13)
2597	--PORT MAP(
2598	-- data_in => Port_in(13),
2599	-- data_in_en => data_in_en(13),
2600	-- reset => reset,
2601	-- clk =>clk,
2602	-- grant(1) => grant_signal(157),
2603	-- grant(2) => grant_signal(158),
2604	-- grant(3) => grant_signal(159),
2605	-- grant(4) => grant_signal(160),
2606	-- grant(5) => grant_signal(161),
2607	-- grant(6) => grant_signal(162),
2608	-- grant(7) => grant_signal(163),
2609	-- grant(8) => grant_signal(164),
2610	-- grant(9) => grant_signal(165),
2611	-- grant(10) => grant_signal(166),
2612	-- grant(11) => grant_signal(167),
2613	-- grant(12) => grant_signal(168),
2614	-- grant(13) => grant_signal(169),
2615	-- fifo_full =>fifo_in_full(13),
2616	-- priority_rotation => priority_rotation_signal(13),
2617	-- fifo_empty => fifo_in_empty(13),
2618	-- data_out =>crossbar_in_port(13),
2619	-- data_out_pulse =>crossbar_in_pulse(13),
2620	-- request(1) =>request_signal(157),
2621	-- request(2) =>request_signal(158),
2622	-- request(3) =>request_signal(159),
2623	-- request(4) =>request_signal(160),
2624	-- request(5) =>request_signal(161),
2625	-- request(6) =>request_signal(162),
2626	-- request(7) =>request_signal(163),
2627	-- request(8) =>request_signal(164),
2628	-- request(9) =>request_signal(165),
2629	-- request(10) =>request_signal(166),
2630	-- request(11) =>request_signal(167),
2631	-- request(12) =>request_signal(168),
2632	-- request(13) =>request_signal(169)
2633	--);
2634	--
2635	--end generate switch13x13;
2636	--
2637	--
2638	---- switch 14 ports
2639	--switch14x14 : if number_of_ports = 14 generate
2640	--
2641	--PORT1_INPUT_PORT_MODULE: INPUT_PORT_MODULE
2642	--GENERIC MAP(number_of_ports =>14)
2643	--PORT MAP(
2644	-- data_in => Port_in(1),
2645	-- data_in_en => data_in_en(1),
2646	-- reset => reset,
2647	-- clk =>clk,
2648	-- grant(1) => grant_signal(1),
2649	-- grant(2) => grant_signal(2),
2650	-- grant(3) => grant_signal(3),
2651	-- grant(4) => grant_signal(4),
2652	-- grant(5) => grant_signal(5),
2653	-- grant(6) => grant_signal(6),
2654	-- grant(7) => grant_signal(7),
2655	-- grant(8) => grant_signal(8),
2656	-- grant(9) => grant_signal(9),
2657	-- grant(10) => grant_signal(10),
2658	-- grant(11) => grant_signal(11),
2659	-- grant(12) => grant_signal(12),
2660	-- grant(13) => grant_signal(13),
2661	-- grant(14) => grant_signal(14),
2662	-- fifo_full =>fifo_in_full(1),
2663	-- priority_rotation => priority_rotation_signal(1),
2664	-- fifo_empty => fifo_in_empty(1),
2665	-- data_out =>crossbar_in_port(1),
2666	-- data_out_pulse =>crossbar_in_pulse(1),
2667	-- request(1) =>request_signal(1),
2668	-- request(2) =>request_signal(2),
2669	-- request(3) =>request_signal(3),
2670	-- request(4) =>request_signal(4),
2671	-- request(5) =>request_signal(5),
2672	-- request(6) =>request_signal(6),
2673	-- request(7) =>request_signal(7),
2674	-- request(8) =>request_signal(8),
2675	-- request(9) =>request_signal(9),
2676	-- request(10) =>request_signal(10),
2677	-- request(11) =>request_signal(11),
2678	-- request(12) =>request_signal(12),
2679	-- request(13) =>request_signal(13),
2680	-- request(14) =>request_signal(14)
2681	--);
2682	--
2683	--PORT2_INPUT_PORT_MODULE: INPUT_PORT_MODULE
2684	--GENERIC MAP(number_of_ports =>14)
2685	--PORT MAP(
2686	-- data_in => Port_in(2),
2687	-- data_in_en => data_in_en(2),
2688	-- reset => reset,
2689	-- clk =>clk,
2690	-- grant(1) => grant_signal(15),
2691	-- grant(2) => grant_signal(16),
2692	-- grant(3) => grant_signal(17),
2693	-- grant(4) => grant_signal(18),
2694	-- grant(5) => grant_signal(19),
2695	-- grant(6) => grant_signal(20),
2696	-- grant(7) => grant_signal(21),
2697	-- grant(8) => grant_signal(22),
2698	-- grant(9) => grant_signal(23),
2699	-- grant(10) => grant_signal(24),
2700	-- grant(11) => grant_signal(25),
2701	-- grant(12) => grant_signal(26),
2702	-- grant(13) => grant_signal(27),
2703	-- grant(14) => grant_signal(28),
2704	-- fifo_full =>fifo_in_full(2),
2705	-- priority_rotation => priority_rotation_signal(2),
2706	-- fifo_empty => fifo_in_empty(2),
2707	-- data_out =>crossbar_in_port(2),
2708	-- data_out_pulse =>crossbar_in_pulse(2),
2709	-- request(1) =>request_signal(15),
2710	-- request(2) =>request_signal(16),
2711	-- request(3) =>request_signal(17),
2712	-- request(4) =>request_signal(18),
2713	-- request(5) =>request_signal(19),
2714	-- request(6) =>request_signal(20),
2715	-- request(7) =>request_signal(21),
2716	-- request(8) =>request_signal(22),
2717	-- request(9) =>request_signal(23),
2718	-- request(10) =>request_signal(24),
2719	-- request(11) =>request_signal(25),
2720	-- request(12) =>request_signal(26),
2721	-- request(13) =>request_signal(27),
2722	-- request(14) =>request_signal(28)
2723	--);
2724	--
2725	--PORT3_INPUT_PORT_MODULE: INPUT_PORT_MODULE
2726	--GENERIC MAP(number_of_ports =>14)
2727	--PORT MAP(
2728	-- data_in => Port_in(3),
2729	-- data_in_en => data_in_en(3),
2730	-- reset => reset,
2731	-- clk =>clk,
2732	-- grant(1) => grant_signal(29),
2733	-- grant(2) => grant_signal(30),
2734	-- grant(3) => grant_signal(31),
2735	-- grant(4) => grant_signal(32),
2736	-- grant(5) => grant_signal(33),
2737	-- grant(6) => grant_signal(34),
2738	-- grant(7) => grant_signal(35),
2739	-- grant(8) => grant_signal(36),
2740	-- grant(9) => grant_signal(37),
2741	-- grant(10)=> grant_signal(38),
2742	-- grant(11) => grant_signal(39),
2743	-- grant(12) => grant_signal(40),
2744	-- grant(13) => grant_signal(41),
2745	-- grant(14) => grant_signal(42),
2746	-- fifo_full =>fifo_in_full(3),
2747	-- priority_rotation => priority_rotation_signal(3),
2748	-- fifo_empty => fifo_in_empty(3),
2749	-- data_out =>crossbar_in_port(3),
2750	-- data_out_pulse =>crossbar_in_pulse(3),
2751	-- request(01) =>request_signal(29),
2752	-- request(02) =>request_signal(30),
2753	-- request(03) =>request_signal(31),
2754	-- request(04) =>request_signal(32),
2755	-- request(05) =>request_signal(33),
2756	-- request(06) =>request_signal(34),
2757	-- request(07) =>request_signal(35),
2758	-- request(08) =>request_signal(36),
2759	-- request(09) =>request_signal(37),
2760	-- request(10) =>request_signal(38),
2761	-- request(11) =>request_signal(39),
2762	-- request(12) =>request_signal(40),
2763	-- request(13) =>request_signal(41),
2764	-- request(14) =>request_signal(42)
2765	--);
2766	--
2767	--PORT4_INPUT_PORT_MODULE: INPUT_PORT_MODULE
2768	--GENERIC MAP(number_of_ports =>14)
2769	--PORT MAP(
2770	-- data_in => Port_in(4),
2771	-- data_in_en => data_in_en(4),
2772	-- reset => reset,
2773	-- clk =>clk,
2774	-- grant(01) => grant_signal(43),
2775	-- grant(02) => grant_signal(44),
2776	-- grant(03) => grant_signal(45),
2777	-- grant(04) => grant_signal(46),
2778	-- grant(05) => grant_signal(47),
2779	-- grant(06) => grant_signal(48),
2780	-- grant(07) => grant_signal(49),
2781	-- grant(08) => grant_signal(50),
2782	-- grant(09) => grant_signal(51),
2783	-- grant(10) => grant_signal(52),
2784	-- grant(11) => grant_signal(53),
2785	-- grant(12) => grant_signal(54),
2786	-- grant(13) => grant_signal(55),
2787	-- grant(14) => grant_signal(56),
2788	-- fifo_full =>fifo_in_full(4),
2789	-- priority_rotation => priority_rotation_signal(4),
2790	-- fifo_empty => fifo_in_empty(4),
2791	-- data_out =>crossbar_in_port(4),
2792	-- data_out_pulse =>crossbar_in_pulse(4),
2793	-- request(01) =>request_signal(43),
2794	-- request(02) =>request_signal(44),
2795	-- request(03) =>request_signal(45),
2796	-- request(04) =>request_signal(46),
2797	-- request(05) =>request_signal(47),
2798	-- request(06) =>request_signal(48),
2799	-- request(07) =>request_signal(49),
2800	-- request(08) =>request_signal(50),
2801	-- request(09) =>request_signal(51),
2802	-- request(10) =>request_signal(52),
2803	-- request(11) =>request_signal(53),
2804	-- request(12) =>request_signal(54),
2805	-- request(13) =>request_signal(55),
2806	-- request(14) =>request_signal(56)
2807	--);
2808	--
2809	--PORT5_INPUT_PORT_MODULE: INPUT_PORT_MODULE
2810	--GENERIC MAP(number_of_ports =>14)
2811	--PORT MAP(
2812	-- data_in => Port_in(5),
2813	-- data_in_en => data_in_en(5),
2814	-- reset => reset,
2815	-- clk =>clk,
2816	-- grant(01) => grant_signal(57),
2817	-- grant(02) => grant_signal(58),
2818	-- grant(03) => grant_signal(59),
2819	-- grant(04) => grant_signal(60),
2820	-- grant(05) => grant_signal(61),
2821	-- grant(06) => grant_signal(62),
2822	-- grant(07) => grant_signal(63),
2823	-- grant(08) => grant_signal(64),
2824	-- grant(09) => grant_signal(65),
2825	-- grant(10) => grant_signal(66),
2826	-- grant(11) => grant_signal(67),
2827	-- grant(12) => grant_signal(68),
2828	-- grant(13) => grant_signal(69),
2829	-- grant(14) => grant_signal(70),
2830	-- fifo_full =>fifo_in_full(5),
2831	-- priority_rotation => priority_rotation_signal(5),
2832	-- fifo_empty => fifo_in_empty(5),
2833	-- data_out =>crossbar_in_port(5),
2834	-- data_out_pulse =>crossbar_in_pulse(5),
2835	-- request(01) =>request_signal(57),
2836	-- request(02) =>request_signal(58),
2837	-- request(03) =>request_signal(59),
2838	-- request(04) =>request_signal(60),
2839	-- request(05) =>request_signal(61),
2840	-- request(06) =>request_signal(62),
2841	-- request(07) =>request_signal(63),
2842	-- request(08) =>request_signal(64),
2843	-- request(09) =>request_signal(65),
2844	-- request(10) =>request_signal(66),
2845	-- request(11) =>request_signal(67),
2846	-- request(12) =>request_signal(68),
2847	-- request(13) =>request_signal(69),
2848	-- request(14) =>request_signal(70)
2849	--);
2850	--
2851	--PORT6_INPUT_PORT_MODULE: INPUT_PORT_MODULE
2852	--GENERIC MAP(number_of_ports =>14)
2853	--PORT MAP(
2854	-- data_in => Port_in(6),
2855	-- data_in_en => data_in_en(6),
2856	-- reset => reset,
2857	-- clk =>clk,
2858	-- grant(01) => grant_signal(71),
2859	-- grant(02) => grant_signal(72),
2860	-- grant(03) => grant_signal(73),
2861	-- grant(04) => grant_signal(74),
2862	-- grant(05) => grant_signal(75),
2863	-- grant(06) => grant_signal(76),
2864	-- grant(07) => grant_signal(77),
2865	-- grant(08) => grant_signal(78),
2866	-- grant(09) => grant_signal(79),
2867	-- grant(10) => grant_signal(80),
2868	-- grant(11) => grant_signal(81),
2869	-- grant(12) => grant_signal(82),
2870	-- grant(13) => grant_signal(83),
2871	-- grant(14) => grant_signal(84),
2872	-- fifo_full =>fifo_in_full(6),
2873	-- priority_rotation => priority_rotation_signal(6),
2874	-- fifo_empty => fifo_in_empty(6),
2875	-- data_out =>crossbar_in_port(6),
2876	-- data_out_pulse =>crossbar_in_pulse(6),
2877	-- request(01) =>request_signal(71),
2878	-- request(02) =>request_signal(72),
2879	-- request(03) =>request_signal(73),
2880	-- request(04) =>request_signal(74),
2881	-- request(05) =>request_signal(75),
2882	-- request(06) =>request_signal(76),
2883	-- request(07) =>request_signal(77),
2884	-- request(08) =>request_signal(78),
2885	-- request(09) =>request_signal(79),
2886	-- request(10) =>request_signal(80),
2887	-- request(11) =>request_signal(81),
2888	-- request(12) =>request_signal(82),
2889	-- request(13) =>request_signal(83),
2890	-- request(14) =>request_signal(84)
2891	--);
2892	--
2893	--PORT7_INPUT_PORT_MODULE: INPUT_PORT_MODULE
2894	--GENERIC MAP(number_of_ports =>14)
2895	--PORT MAP(
2896	-- data_in => Port_in(7),
2897	-- data_in_en => data_in_en(7),
2898	-- reset => reset,
2899	-- clk =>clk,
2900	-- grant(01) => grant_signal(85),
2901	-- grant(02) => grant_signal(86),
2902	-- grant(03) => grant_signal(87),
2903	-- grant(04) => grant_signal(88),
2904	-- grant(05) => grant_signal(89),
2905	-- grant(06) => grant_signal(90),
2906	-- grant(07) => grant_signal(91),
2907	-- grant(08) => grant_signal(92),
2908	-- grant(09) => grant_signal(93),
2909	-- grant(10) => grant_signal(94),
2910	-- grant(11) => grant_signal(95),
2911	-- grant(12) => grant_signal(96),
2912	-- grant(13) => grant_signal(97),
2913	-- grant(14) => grant_signal(98),
2914	-- fifo_full =>fifo_in_full(7),
2915	-- priority_rotation => priority_rotation_signal(7),
2916	-- fifo_empty => fifo_in_empty(7),
2917	-- data_out =>crossbar_in_port(7),
2918	-- data_out_pulse =>crossbar_in_pulse(7),
2919	-- request(01) =>request_signal(85),
2920	-- request(02) =>request_signal(86),
2921	-- request(03) =>request_signal(87),
2922	-- request(04) =>request_signal(88),
2923	-- request(05) =>request_signal(89),
2924	-- request(06) =>request_signal(90),
2925	-- request(07) =>request_signal(91),
2926	-- request(08) =>request_signal(92),
2927	-- request(09) =>request_signal(93),
2928	-- request(10) =>request_signal(94),
2929	-- request(11) =>request_signal(95),
2930	-- request(12) =>request_signal(96),
2931	-- request(13) =>request_signal(97),
2932	-- request(14) =>request_signal(98)
2933	--);
2934	--
2935	--PORT8_INPUT_PORT_MODULE: INPUT_PORT_MODULE
2936	--GENERIC MAP(number_of_ports =>14)
2937	--PORT MAP(
2938	-- data_in => Port_in(8),
2939	-- data_in_en => data_in_en(8),
2940	-- reset => reset,
2941	-- clk =>clk,
2942	-- grant(01) => grant_signal(99),
2943	-- grant(02) => grant_signal(100),
2944	-- grant(03) => grant_signal(101),
2945	-- grant(04) => grant_signal(102),
2946	-- grant(05) => grant_signal(103),
2947	-- grant(06) => grant_signal(104),
2948	-- grant(07) => grant_signal(105),
2949	-- grant(08) => grant_signal(106),
2950	-- grant(09) => grant_signal(107),
2951	-- grant(10) => grant_signal(108),
2952	-- grant(11) => grant_signal(109),
2953	-- grant(12) => grant_signal(110),
2954	-- grant(13) => grant_signal(111),
2955	-- grant(14) => grant_signal(112),
2956	-- fifo_full =>fifo_in_full(8),
2957	-- priority_rotation => priority_rotation_signal(8),
2958	-- fifo_empty => fifo_in_empty(8),
2959	-- data_out =>crossbar_in_port(8),
2960	-- data_out_pulse =>crossbar_in_pulse(8),
2961	-- request(1) =>request_signal(99),
2962	-- request(2) =>request_signal(100),
2963	-- request(3) =>request_signal(101),
2964	-- request(4) =>request_signal(102),
2965	-- request(5) =>request_signal(103),
2966	-- request(6) =>request_signal(104),
2967	-- request(7) =>request_signal(105),
2968	-- request(8) =>request_signal(106),
2969	-- request(9) =>request_signal(107),
2970	-- request(10) =>request_signal(108),
2971	-- request(11) =>request_signal(109),
2972	-- request(12) =>request_signal(110),
2973	-- request(13) =>request_signal(111),
2974	-- request(14) =>request_signal(112)
2975	--);
2976	--
2977	--PORT9_INPUT_PORT_MODULE: INPUT_PORT_MODULE
2978	--GENERIC MAP(number_of_ports =>14)
2979	--PORT MAP(
2980	-- data_in => Port_in(9),
2981	-- data_in_en => data_in_en(9),
2982	-- reset => reset,
2983	-- clk =>clk,
2984	-- grant(1) => grant_signal(113),
2985	-- grant(2) => grant_signal(114),
2986	-- grant(3) => grant_signal(115),
2987	-- grant(4) => grant_signal(116),
2988	-- grant(5) => grant_signal(117),
2989	-- grant(6) => grant_signal(118),
2990	-- grant(7) => grant_signal(119),
2991	-- grant(8) => grant_signal(120),
2992	-- grant(9) => grant_signal(121),
2993	-- grant(10) => grant_signal(122),
2994	-- grant(11) => grant_signal(123),
2995	-- grant(12) => grant_signal(124),
2996	-- grant(13) => grant_signal(125),
2997	-- grant(14) => grant_signal(126),
2998	-- fifo_full =>fifo_in_full(9),
2999	-- priority_rotation => priority_rotation_signal(9),
3000	-- fifo_empty => fifo_in_empty(9),
3001	-- data_out =>crossbar_in_port(9),
3002	-- data_out_pulse =>crossbar_in_pulse(9),
3003	-- request(1) =>request_signal(113),
3004	-- request(2) =>request_signal(114),
3005	-- request(3) =>request_signal(115),
3006	-- request(4) =>request_signal(116),
3007	-- request(5) =>request_signal(117),
3008	-- request(6) =>request_signal(118),
3009	-- request(7) =>request_signal(119),
3010	-- request(8) =>request_signal(120),
3011	-- request(9) =>request_signal(121),
3012	-- request(10) =>request_signal(122),
3013	-- request(11) =>request_signal(123),
3014	-- request(12) =>request_signal(124),
3015	-- request(13) =>request_signal(125),
3016	-- request(14) =>request_signal(126)
3017	--);
3018	--
3019	--PORT10_INPUT_PORT_MODULE: INPUT_PORT_MODULE
3020	--GENERIC MAP(number_of_ports =>14)
3021	--PORT MAP(
3022	-- data_in => Port_in(10),
3023	-- data_in_en => data_in_en(10),
3024	-- reset => reset,
3025	-- clk =>clk,
3026	-- grant(1) => grant_signal(127),
3027	-- grant(2) => grant_signal(128),
3028	-- grant(3) => grant_signal(129),
3029	-- grant(4) => grant_signal(130),
3030	-- grant(5) => grant_signal(131),
3031	-- grant(6) => grant_signal(132),
3032	-- grant(7) => grant_signal(133),
3033	-- grant(8) => grant_signal(134),
3034	-- grant(9) => grant_signal(135),
3035	-- grant(10) => grant_signal(136),
3036	-- grant(11) => grant_signal(137),
3037	-- grant(12) => grant_signal(138),
3038	-- grant(13) => grant_signal(139),
3039	-- grant(14) => grant_signal(140),
3040	-- fifo_full =>fifo_in_full(10),
3041	-- priority_rotation => priority_rotation_signal(10),
3042	-- fifo_empty => fifo_in_empty(10),
3043	-- data_out =>crossbar_in_port(10),
3044	-- data_out_pulse =>crossbar_in_pulse(10),
3045	-- request(1) =>request_signal(127),
3046	-- request(2) =>request_signal(128),
3047	-- request(3) =>request_signal(129),
3048	-- request(4) =>request_signal(130),
3049	-- request(5) =>request_signal(131),
3050	-- request(6) =>request_signal(132),
3051	-- request(7) =>request_signal(133),
3052	-- request(8) =>request_signal(134),
3053	-- request(9) =>request_signal(135),
3054	-- request(10) =>request_signal(136),
3055	-- request(11) =>request_signal(137),
3056	-- request(12) =>request_signal(138),
3057	-- request(13) =>request_signal(139),
3058	-- request(14) =>request_signal(140)
3059	--);
3060	--
3061	--PORT11_INPUT_PORT_MODULE: INPUT_PORT_MODULE
3062	--GENERIC MAP(number_of_ports =>14)
3063	--PORT MAP(
3064	-- data_in => Port_in(11),
3065	-- data_in_en => data_in_en(11),
3066	-- reset => reset,
3067	-- clk =>clk,
3068	-- grant(1) => grant_signal(141),
3069	-- grant(2) => grant_signal(142),
3070	-- grant(3) => grant_signal(143),
3071	-- grant(4) => grant_signal(144),
3072	-- grant(5) => grant_signal(145),
3073	-- grant(6) => grant_signal(146),
3074	-- grant(7) => grant_signal(147),
3075	-- grant(8) => grant_signal(148),
3076	-- grant(9) => grant_signal(149),
3077	-- grant(10) => grant_signal(150),
3078	-- grant(11) => grant_signal(151),
3079	-- grant(12) => grant_signal(152),
3080	-- grant(13) => grant_signal(153),
3081	-- grant(14) => grant_signal(154),
3082	-- fifo_full =>fifo_in_full(11),
3083	-- priority_rotation => priority_rotation_signal(11),
3084	-- fifo_empty => fifo_in_empty(11),
3085	-- data_out =>crossbar_in_port(11),
3086	-- data_out_pulse =>crossbar_in_pulse(11),
3087	-- request(1) =>request_signal(141),
3088	-- request(2) =>request_signal(142),
3089	-- request(3) =>request_signal(143),
3090	-- request(4) =>request_signal(144),
3091	-- request(5) =>request_signal(145),
3092	-- request(6) =>request_signal(146),
3093	-- request(7) =>request_signal(147),
3094	-- request(8) =>request_signal(148),
3095	-- request(9) =>request_signal(149),
3096	-- request(10) =>request_signal(150),
3097	-- request(11) =>request_signal(151),
3098	-- request(12) =>request_signal(152),
3099	-- request(13) =>request_signal(153),
3100	-- request(14) =>request_signal(154)
3101	--);
3102	--
3103	--PORT12_INPUT_PORT_MODULE: INPUT_PORT_MODULE
3104	--GENERIC MAP(number_of_ports =>14)
3105	--PORT MAP(
3106	-- data_in => Port_in(12),
3107	-- data_in_en => data_in_en(12),
3108	-- reset => reset,
3109	-- clk =>clk,
3110	-- grant(1) => grant_signal(155),
3111	-- grant(2) => grant_signal(156),
3112	-- grant(3) => grant_signal(157),
3113	-- grant(4) => grant_signal(158),
3114	-- grant(5) => grant_signal(159),
3115	-- grant(6) => grant_signal(160),
3116	-- grant(7) => grant_signal(161),
3117	-- grant(8) => grant_signal(162),
3118	-- grant(9) => grant_signal(163),
3119	-- grant(10) => grant_signal(164),
3120	-- grant(11) => grant_signal(165),
3121	-- grant(12) => grant_signal(166),
3122	-- grant(13) => grant_signal(167),
3123	-- grant(14) => grant_signal(168),
3124	-- fifo_full =>fifo_in_full(12),
3125	-- priority_rotation => priority_rotation_signal(12),
3126	-- fifo_empty => fifo_in_empty(12),
3127	-- data_out =>crossbar_in_port(12),
3128	-- data_out_pulse =>crossbar_in_pulse(12),
3129	-- request(1) =>request_signal(155),
3130	-- request(2) =>request_signal(156),
3131	-- request(3) =>request_signal(157),
3132	-- request(4) =>request_signal(158),
3133	-- request(5) =>request_signal(159),
3134	-- request(6) =>request_signal(160),
3135	-- request(7) =>request_signal(161),
3136	-- request(8) =>request_signal(162),
3137	-- request(9) =>request_signal(163),
3138	-- request(10) =>request_signal(164),
3139	-- request(11) =>request_signal(165),
3140	-- request(12) =>request_signal(166),
3141	-- request(13) =>request_signal(167),
3142	-- request(14) =>request_signal(168)
3143	--);
3144	--
3145	--PORT13_INPUT_PORT_MODULE: INPUT_PORT_MODULE
3146	--GENERIC MAP(number_of_ports =>14)
3147	--PORT MAP(
3148	-- data_in => Port_in(13),
3149	-- data_in_en => data_in_en(13),
3150	-- reset => reset,
3151	-- clk =>clk,
3152	-- grant(1) => grant_signal(169),
3153	-- grant(2) => grant_signal(170),
3154	-- grant(3) => grant_signal(171),
3155	-- grant(4) => grant_signal(172),
3156	-- grant(5) => grant_signal(173),
3157	-- grant(6) => grant_signal(174),
3158	-- grant(7) => grant_signal(175),
3159	-- grant(8) => grant_signal(176),
3160	-- grant(9) => grant_signal(177),
3161	-- grant(10) => grant_signal(178),
3162	-- grant(11) => grant_signal(179),
3163	-- grant(12) => grant_signal(180),
3164	-- grant(13) => grant_signal(181),
3165	-- grant(14) => grant_signal(182),
3166	-- fifo_full =>fifo_in_full(13),
3167	-- priority_rotation => priority_rotation_signal(13),
3168	-- fifo_empty => fifo_in_empty(13),
3169	-- data_out =>crossbar_in_port(13),
3170	-- data_out_pulse =>crossbar_in_pulse(13),
3171	-- request(1) =>request_signal(169),
3172	-- request(2) =>request_signal(170),
3173	-- request(3) =>request_signal(171),
3174	-- request(4) =>request_signal(172),
3175	-- request(5) =>request_signal(173),
3176	-- request(6) =>request_signal(174),
3177	-- request(7) =>request_signal(175),
3178	-- request(8) =>request_signal(176),
3179	-- request(9) =>request_signal(177),
3180	-- request(10) =>request_signal(178),
3181	-- request(11) =>request_signal(179),
3182	-- request(12) =>request_signal(180),
3183	-- request(13) =>request_signal(181),
3184	-- request(14) =>request_signal(182)
3185	--);
3186	--
3187	--PORT14_INPUT_PORT_MODULE: INPUT_PORT_MODULE
3188	--GENERIC MAP(number_of_ports =>14)
3189	--PORT MAP(
3190	-- data_in => Port_in(14),
3191	-- data_in_en => data_in_en(14),
3192	-- reset => reset,
3193	-- clk =>clk,
3194	-- grant(1) => grant_signal(183),
3195	-- grant(2) => grant_signal(184),
3196	-- grant(3) => grant_signal(185),
3197	-- grant(4) => grant_signal(186),
3198	-- grant(5) => grant_signal(187),
3199	-- grant(6) => grant_signal(188),
3200	-- grant(7) => grant_signal(189),
3201	-- grant(8) => grant_signal(190),
3202	-- grant(9) => grant_signal(191),
3203	-- grant(10) => grant_signal(192),
3204	-- grant(11) => grant_signal(193),
3205	-- grant(12) => grant_signal(194),
3206	-- grant(13) => grant_signal(195),
3207	-- grant(14) => grant_signal(196),
3208	-- fifo_full =>fifo_in_full(14),
3209	-- priority_rotation => priority_rotation_signal(14),
3210	-- fifo_empty => fifo_in_empty(14),
3211	-- data_out =>crossbar_in_port(14),
3212	-- data_out_pulse =>crossbar_in_pulse(14),
3213	-- request(1) =>request_signal(183),
3214	-- request(2) =>request_signal(184),
3215	-- request(3) =>request_signal(185),
3216	-- request(4) =>request_signal(186),
3217	-- request(5) =>request_signal(187),
3218	-- request(6) =>request_signal(188),
3219	-- request(7) =>request_signal(189),
3220	-- request(8) =>request_signal(190),
3221	-- request(9) =>request_signal(191),
3222	-- request(10) =>request_signal(192),
3223	-- request(11) =>request_signal(193),
3224	-- request(12) =>request_signal(194),
3225	-- request(13) =>request_signal(195),
3226	-- request(14) =>request_signal(196)
3227	--);
3228	--
3229	--end generate switch14x14;
3230	--
3231	--
3232	---- switch 15 ports
3233	--switch15x15 : if number_of_ports = 15 generate
3234	--
3235	--PORT1_INPUT_PORT_MODULE: INPUT_PORT_MODULE
3236	--GENERIC MAP(number_of_ports =>15)
3237	--PORT MAP(
3238	-- data_in => Port_in(1),
3239	-- data_in_en => data_in_en(1),
3240	-- reset => reset,
3241	-- clk =>clk,
3242	-- grant(1) => grant_signal(1),
3243	-- grant(2) => grant_signal(2),
3244	-- grant(3) => grant_signal(3),
3245	-- grant(4) => grant_signal(4),
3246	-- grant(5) => grant_signal(5),
3247	-- grant(6) => grant_signal(6),
3248	-- grant(7) => grant_signal(7),
3249	-- grant(8) => grant_signal(8),
3250	-- grant(9) => grant_signal(9),
3251	-- grant(10) => grant_signal(10),
3252	-- grant(11) => grant_signal(11),
3253	-- grant(12) => grant_signal(12),
3254	-- grant(13) => grant_signal(13),
3255	-- grant(14) => grant_signal(14),
3256	-- grant(15) => grant_signal(15),
3257	-- fifo_full =>fifo_in_full(1),
3258	-- priority_rotation => priority_rotation_signal(1),
3259	-- fifo_empty => fifo_in_empty(1),
3260	-- data_out =>crossbar_in_port(1),
3261	-- data_out_pulse =>crossbar_in_pulse(1),
3262	-- request(1) =>request_signal(1),
3263	-- request(2) =>request_signal(2),
3264	-- request(3) =>request_signal(3),
3265	-- request(4) =>request_signal(4),
3266	-- request(5) =>request_signal(5),
3267	-- request(6) =>request_signal(6),
3268	-- request(7) =>request_signal(7),
3269	-- request(8) =>request_signal(8),
3270	-- request(9) =>request_signal(9),
3271	-- request(10) =>request_signal(10),
3272	-- request(11) =>request_signal(11),
3273	-- request(12) =>request_signal(12),
3274	-- request(13) =>request_signal(13),
3275	-- request(14) =>request_signal(14),
3276	-- request(15) =>request_signal(15)
3277	--);
3278	--
3279	--PORT2_INPUT_PORT_MODULE: INPUT_PORT_MODULE
3280	--GENERIC MAP(number_of_ports =>15)
3281	--PORT MAP(
3282	-- data_in => Port_in(2),
3283	-- data_in_en => data_in_en(2),
3284	-- reset => reset,
3285	-- clk =>clk,
3286	-- grant(16) => grant_signal(16),
3287	-- grant(17) => grant_signal(17),
3288	-- grant(18) => grant_signal(18),
3289	-- grant(19) => grant_signal(19),
3290	-- grant(20) => grant_signal(20),
3291	-- grant(21) => grant_signal(21),
3292	-- grant(22) => grant_signal(22),
3293	-- grant(23) => grant_signal(23),
3294	-- grant(24) => grant_signal(24),
3295	-- grant(25) => grant_signal(25),
3296	-- grant(26) => grant_signal(26),
3297	-- grant(27) => grant_signal(27),
3298	-- grant(28) => grant_signal(28),
3299	-- grant(29) => grant_signal(29),
3300	-- grant(30) => grant_signal(30),
3301	-- fifo_full =>fifo_in_full(2),
3302	-- priority_rotation => priority_rotation_signal(2),
3303	-- fifo_empty => fifo_in_empty(2),
3304	-- data_out =>crossbar_in_port(2),
3305	-- data_out_pulse =>crossbar_in_pulse(2),
3306	-- request(16) =>request_signal(16),
3307	-- request(17) =>request_signal(17),
3308	-- request(18) =>request_signal(18),
3309	-- request(19) =>request_signal(19),
3310	-- request(20) =>request_signal(20),
3311	-- request(21) =>request_signal(21),
3312	-- request(22) =>request_signal(22),
3313	-- request(23) =>request_signal(23),
3314	-- request(24) =>request_signal(24),
3315	-- request(25) =>request_signal(25),
3316	-- request(26) =>request_signal(26),
3317	-- request(27) =>request_signal(27),
3318	-- request(28) =>request_signal(28),
3319	-- request(29) =>request_signal(29),
3320	-- request(30) =>request_signal(30)
3321	--);
3322	--
3323	--PORT3_INPUT_PORT_MODULE: INPUT_PORT_MODULE
3324	--GENERIC MAP(number_of_ports =>15)
3325	--PORT MAP(
3326	-- data_in => Port_in(3),
3327	-- data_in_en => data_in_en(3),
3328	-- reset => reset,
3329	-- clk =>clk,
3330	-- grant(31) => grant_signal(31),
3331	-- grant(32) => grant_signal(32),
3332	-- grant(33) => grant_signal(33),
3333	-- grant(34) => grant_signal(34),
3334	-- grant(35) => grant_signal(35),
3335	-- grant(36) => grant_signal(36),
3336	-- grant(37) => grant_signal(37),
3337	-- grant(38) => grant_signal(38),
3338	-- grant(39) => grant_signal(39),
3339	-- grant(40) => grant_signal(40),
3340	-- grant(41) => grant_signal(41),
3341	-- grant(42) => grant_signal(42),
3342	-- grant(43) => grant_signal(43),
3343	-- grant(44) => grant_signal(44),
3344	-- grant(45) => grant_signal(45),
3345	-- fifo_full =>fifo_in_full(3),
3346	-- priority_rotation => priority_rotation_signal(3),
3347	-- fifo_empty => fifo_in_empty(3),
3348	-- data_out =>crossbar_in_port(3),
3349	-- data_out_pulse =>crossbar_in_pulse(3),
3350	-- request(31) =>request_signal(31),
3351	-- request(32) =>request_signal(32),
3352	-- request(33) =>request_signal(33),
3353	-- request(34) =>request_signal(34),
3354	-- request(35) =>request_signal(35),
3355	-- request(36) =>request_signal(36),
3356	-- request(37) =>request_signal(37),
3357	-- request(38) =>request_signal(38),
3358	-- request(39) =>request_signal(39),
3359	-- request(40) =>request_signal(40),
3360	-- request(41) =>request_signal(41),
3361	-- request(42) =>request_signal(42),
3362	-- request(43) =>request_signal(43),
3363	-- request(44) =>request_signal(44),
3364	-- request(45) =>request_signal(45)
3365	--);
3366	--
3367	--PORT4_INPUT_PORT_MODULE: INPUT_PORT_MODULE
3368	--GENERIC MAP(number_of_ports =>15)
3369	--PORT MAP(
3370	-- data_in => Port_in(4),
3371	-- data_in_en => data_in_en(4),
3372	-- reset => reset,
3373	-- clk =>clk,
3374	-- grant(46) => grant_signal(46),
3375	-- grant(47) => grant_signal(47),
3376	-- grant(48) => grant_signal(48),
3377	-- grant(49) => grant_signal(49),
3378	-- grant(50) => grant_signal(50),
3379	-- grant(51) => grant_signal(51),
3380	-- grant(52) => grant_signal(52),
3381	-- grant(53) => grant_signal(53),
3382	-- grant(54) => grant_signal(54),
3383	-- grant(55) => grant_signal(55),
3384	-- grant(56) => grant_signal(56),
3385	-- grant(57) => grant_signal(57),
3386	-- grant(58) => grant_signal(58),
3387	-- grant(59) => grant_signal(59),
3388	-- grant(60) => grant_signal(60),
3389	-- fifo_full =>fifo_in_full(4),
3390	-- priority_rotation => priority_rotation_signal(4),
3391	-- fifo_empty => fifo_in_empty(4),
3392	-- data_out =>crossbar_in_port(4),
3393	-- data_out_pulse =>crossbar_in_pulse(4),
3394	-- request(46) =>request_signal(46),
3395	-- request(47) =>request_signal(47),
3396	-- request(48) =>request_signal(48),
3397	-- request(49) =>request_signal(49),
3398	-- request(50) =>request_signal(50),
3399	-- request(51) =>request_signal(51),
3400	-- request(52) =>request_signal(52),
3401	-- request(53) =>request_signal(53),
3402	-- request(54) =>request_signal(54),
3403	-- request(55) =>request_signal(55),
3404	-- request(56) =>request_signal(56),
3405	-- request(57) =>request_signal(57),
3406	-- request(58) =>request_signal(58),
3407	-- request(59) =>request_signal(59),
3408	-- request(60) =>request_signal(60)
3409	--);
3410	--
3411	--PORT5_INPUT_PORT_MODULE: INPUT_PORT_MODULE
3412	--GENERIC MAP(number_of_ports =>15)
3413	--PORT MAP(
3414	-- data_in => Port_in(5),
3415	-- data_in_en => data_in_en(5),
3416	-- reset => reset,
3417	-- clk =>clk,
3418	-- grant(61) => grant_signal(61),
3419	-- grant(62) => grant_signal(62),
3420	-- grant(63) => grant_signal(63),
3421	-- grant(64) => grant_signal(64),
3422	-- grant(65) => grant_signal(65),
3423	-- grant(66) => grant_signal(66),
3424	-- grant(67) => grant_signal(67),
3425	-- grant(68) => grant_signal(68),
3426	-- grant(69) => grant_signal(69),
3427	-- grant(70) => grant_signal(70),
3428	-- grant(71) => grant_signal(71),
3429	-- grant(72) => grant_signal(72),
3430	-- grant(73) => grant_signal(73),
3431	-- grant(74) => grant_signal(74),
3432	-- grant(75) => grant_signal(75),
3433	-- fifo_full =>fifo_in_full(5),
3434	-- priority_rotation => priority_rotation_signal(5),
3435	-- fifo_empty => fifo_in_empty(5),
3436	-- data_out =>crossbar_in_port(5),
3437	-- data_out_pulse =>crossbar_in_pulse(5),
3438	-- request(61) =>request_signal(61),
3439	-- request(62) =>request_signal(62),
3440	-- request(63) =>request_signal(63),
3441	-- request(64) =>request_signal(64),
3442	-- request(65) =>request_signal(65),
3443	-- request(66) =>request_signal(66),
3444	-- request(67) =>request_signal(67),
3445	-- request(68) =>request_signal(68),
3446	-- request(69) =>request_signal(69),
3447	-- request(70) =>request_signal(70),
3448	-- request(71) =>request_signal(71),
3449	-- request(72) =>request_signal(72),
3450	-- request(73) =>request_signal(73),
3451	-- request(74) =>request_signal(74),
3452	-- request(75) =>request_signal(75)
3453	--);
3454	--
3455	--PORT6_INPUT_PORT_MODULE: INPUT_PORT_MODULE
3456	--GENERIC MAP(number_of_ports =>15)
3457	--PORT MAP(
3458	-- data_in => Port_in(6),
3459	-- data_in_en => data_in_en(6),
3460	-- reset => reset,
3461	-- clk =>clk,
3462	-- grant(76) => grant_signal(76),
3463	-- grant(77) => grant_signal(77),
3464	-- grant(78) => grant_signal(78),
3465	-- grant(79) => grant_signal(79),
3466	-- grant(80) => grant_signal(80),
3467	-- grant(81) => grant_signal(81),
3468	-- grant(82) => grant_signal(82),
3469	-- grant(83) => grant_signal(83),
3470	-- grant(84) => grant_signal(84),
3471	-- grant(85) => grant_signal(85),
3472	-- grant(86) => grant_signal(86),
3473	-- grant(87) => grant_signal(87),
3474	-- grant(88) => grant_signal(88),
3475	-- grant(89) => grant_signal(89),
3476	-- grant(90) => grant_signal(90),
3477	-- fifo_full =>fifo_in_full(6),
3478	-- priority_rotation => priority_rotation_signal(6),
3479	-- fifo_empty => fifo_in_empty(6),
3480	-- data_out =>crossbar_in_port(6),
3481	-- data_out_pulse =>crossbar_in_pulse(6),
3482	-- request(76) =>request_signal(76),
3483	-- request(77) =>request_signal(77),
3484	-- request(78) =>request_signal(78),
3485	-- request(79) =>request_signal(79),
3486	-- request(80) =>request_signal(80),
3487	-- request(81) =>request_signal(81),
3488	-- request(82) =>request_signal(82),
3489	-- request(83) =>request_signal(83),
3490	-- request(84) =>request_signal(84),
3491	-- request(85) =>request_signal(85),
3492	-- request(86) =>request_signal(86),
3493	-- request(87) =>request_signal(87),
3494	-- request(88) =>request_signal(88),
3495	-- request(89) =>request_signal(89),
3496	-- request(90) =>request_signal(90)
3497	--);
3498	--
3499	--PORT7_INPUT_PORT_MODULE: INPUT_PORT_MODULE
3500	--GENERIC MAP(number_of_ports =>15)
3501	--PORT MAP(
3502	-- data_in => Port_in(7),
3503	-- data_in_en => data_in_en(7),
3504	-- reset => reset,
3505	-- clk =>clk,
3506	-- grant(91) => grant_signal(91),
3507	-- grant(92) => grant_signal(92),
3508	-- grant(93) => grant_signal(93),
3509	-- grant(94) => grant_signal(94),
3510	-- grant(95) => grant_signal(95),
3511	-- grant(96) => grant_signal(96),
3512	-- grant(97) => grant_signal(97),
3513	-- grant(98) => grant_signal(98),
3514	-- grant(99) => grant_signal(99),
3515	-- grant(100) => grant_signal(100),
3516	-- grant(101) => grant_signal(101),
3517	-- grant(102) => grant_signal(102),
3518	-- grant(103) => grant_signal(103),
3519	-- grant(104) => grant_signal(104),
3520	-- grant(105) => grant_signal(105),
3521	-- fifo_full =>fifo_in_full(7),
3522	-- priority_rotation => priority_rotation_signal(7),
3523	-- fifo_empty => fifo_in_empty(7),
3524	-- data_out =>crossbar_in_port(7),
3525	-- data_out_pulse =>crossbar_in_pulse(7),
3526	-- request(91) =>request_signal(91),
3527	-- request(92) =>request_signal(92),
3528	-- request(93) =>request_signal(93),
3529	-- request(94) =>request_signal(94),
3530	-- request(95) =>request_signal(95),
3531	-- request(96) =>request_signal(96),
3532	-- request(97) =>request_signal(97),
3533	-- request(98) =>request_signal(98),
3534	-- request(99) =>request_signal(99),
3535	-- request(100) =>request_signal(100),
3536	-- request(101) =>request_signal(101),
3537	-- request(102) =>request_signal(102),
3538	-- request(103) =>request_signal(103),
3539	-- request(104) =>request_signal(104),
3540	-- request(105) =>request_signal(105)
3541	--);
3542	--
3543	--PORT8_INPUT_PORT_MODULE: INPUT_PORT_MODULE
3544	--GENERIC MAP(number_of_ports =>15)
3545	--PORT MAP(
3546	-- data_in => Port_in(8),
3547	-- data_in_en => data_in_en(8),
3548	-- reset => reset,
3549	-- clk =>clk,
3550	-- grant(106) => grant_signal(106),
3551	-- grant(107) => grant_signal(107),
3552	-- grant(108) => grant_signal(108),
3553	-- grant(109) => grant_signal(109),
3554	-- grant(110) => grant_signal(110),
3555	-- grant(111) => grant_signal(111),
3556	-- grant(112) => grant_signal(112),
3557	-- grant(113) => grant_signal(113),
3558	-- grant(114) => grant_signal(114),
3559	-- grant(115) => grant_signal(115),
3560	-- grant(116) => grant_signal(116),
3561	-- grant(117) => grant_signal(117),
3562	-- grant(118) => grant_signal(118),
3563	-- grant(119) => grant_signal(119),
3564	-- grant(120) => grant_signal(120),
3565	-- fifo_full =>fifo_in_full(8),
3566	-- priority_rotation => priority_rotation_signal(8),
3567	-- fifo_empty => fifo_in_empty(8),
3568	-- data_out =>crossbar_in_port(8),
3569	-- data_out_pulse =>crossbar_in_pulse(8),
3570	-- request(106) =>request_signal(106),
3571	-- request(107) =>request_signal(107),
3572	-- request(108) =>request_signal(108),
3573	-- request(109) =>request_signal(109),
3574	-- request(110) =>request_signal(110),
3575	-- request(111) =>request_signal(111),
3576	-- request(112) =>request_signal(112),
3577	-- request(113) =>request_signal(113),
3578	-- request(114) =>request_signal(114),
3579	-- request(115) =>request_signal(115),
3580	-- request(116) =>request_signal(116),
3581	-- request(117) =>request_signal(117),
3582	-- request(118) =>request_signal(118),
3583	-- request(119) =>request_signal(119),
3584	-- request(120) =>request_signal(120)
3585	--);
3586	--
3587	--PORT9_INPUT_PORT_MODULE: INPUT_PORT_MODULE
3588	--GENERIC MAP(number_of_ports =>15)
3589	--PORT MAP(
3590	-- data_in => Port_in(9),
3591	-- data_in_en => data_in_en(9),
3592	-- reset => reset,
3593	-- clk =>clk,
3594	-- grant(121) => grant_signal(121),
3595	-- grant(122) => grant_signal(122),
3596	-- grant(123) => grant_signal(123),
3597	-- grant(124) => grant_signal(124),
3598	-- grant(125) => grant_signal(125),
3599	-- grant(126) => grant_signal(126),
3600	-- grant(127) => grant_signal(127),
3601	-- grant(128) => grant_signal(128),
3602	-- grant(129) => grant_signal(129),
3603	-- grant(130) => grant_signal(130),
3604	-- grant(131) => grant_signal(131),
3605	-- grant(132) => grant_signal(132),
3606	-- grant(133) => grant_signal(133),
3607	-- grant(134) => grant_signal(134),
3608	-- grant(135) => grant_signal(135),
3609	-- fifo_full =>fifo_in_full(9),
3610	-- priority_rotation => priority_rotation_signal(9),
3611	-- fifo_empty => fifo_in_empty(9),
3612	-- data_out =>crossbar_in_port(9),
3613	-- data_out_pulse =>crossbar_in_pulse(9),
3614	-- request(121) =>request_signal(121),
3615	-- request(122) =>request_signal(122),
3616	-- request(123) =>request_signal(123),
3617	-- request(124) =>request_signal(124),
3618	-- request(125) =>request_signal(125),
3619	-- request(126) =>request_signal(126),
3620	-- request(127) =>request_signal(127),
3621	-- request(128) =>request_signal(128),
3622	-- request(129) =>request_signal(129),
3623	-- request(130) =>request_signal(130),
3624	-- request(131) =>request_signal(131),
3625	-- request(132) =>request_signal(132),
3626	-- request(133) =>request_signal(133),
3627	-- request(134) =>request_signal(134),
3628	-- request(135) =>request_signal(135)
3629	--);
3630	--
3631	--PORT10_INPUT_PORT_MODULE: INPUT_PORT_MODULE
3632	--GENERIC MAP(number_of_ports =>15)
3633	--PORT MAP(
3634	-- data_in => Port_in(10),
3635	-- data_in_en => data_in_en(10),
3636	-- reset => reset,
3637	-- clk =>clk,
3638	-- grant(136) => grant_signal(136),
3639	-- grant(137) => grant_signal(137),
3640	-- grant(138) => grant_signal(138),
3641	-- grant(139) => grant_signal(139),
3642	-- grant(140) => grant_signal(140),
3643	-- grant(141) => grant_signal(141),
3644	-- grant(142) => grant_signal(142),
3645	-- grant(143) => grant_signal(143),
3646	-- grant(144) => grant_signal(144),
3647	-- grant(145) => grant_signal(145),
3648	-- grant(146) => grant_signal(146),
3649	-- grant(147) => grant_signal(147),
3650	-- grant(148) => grant_signal(148),
3651	-- grant(149) => grant_signal(149),
3652	-- grant(150) => grant_signal(150),
3653	-- fifo_full =>fifo_in_full(10),
3654	-- priority_rotation => priority_rotation_signal(10),
3655	-- fifo_empty => fifo_in_empty(10),
3656	-- data_out =>crossbar_in_port(10),
3657	-- data_out_pulse =>crossbar_in_pulse(10),
3658	-- request(136) =>request_signal(136),
3659	-- request(137) =>request_signal(137),
3660	-- request(138) =>request_signal(138),
3661	-- request(139) =>request_signal(139),
3662	-- request(140) =>request_signal(140),
3663	-- request(141) =>request_signal(141),
3664	-- request(142) =>request_signal(142),
3665	-- request(143) =>request_signal(143),
3666	-- request(144) =>request_signal(144),
3667	-- request(145) =>request_signal(145),
3668	-- request(146) =>request_signal(146),
3669	-- request(147) =>request_signal(147),
3670	-- request(148) =>request_signal(148),
3671	-- request(149) =>request_signal(149),
3672	-- request(150) =>request_signal(150)
3673	--);
3674	--
3675	--PORT11_INPUT_PORT_MODULE: INPUT_PORT_MODULE
3676	--GENERIC MAP(number_of_ports =>15)
3677	--PORT MAP(
3678	-- data_in => Port_in(11),
3679	-- data_in_en => data_in_en(11),
3680	-- reset => reset,
3681	-- clk =>clk,
3682	-- grant(151) => grant_signal(151),
3683	-- grant(152) => grant_signal(152),
3684	-- grant(153) => grant_signal(153),
3685	-- grant(154) => grant_signal(154),
3686	-- grant(155) => grant_signal(155),
3687	-- grant(156) => grant_signal(156),
3688	-- grant(157) => grant_signal(157),
3689	-- grant(158) => grant_signal(158),
3690	-- grant(159) => grant_signal(159),
3691	-- grant(160) => grant_signal(160),
3692	-- grant(161) => grant_signal(161),
3693	-- grant(162) => grant_signal(162),
3694	-- grant(163) => grant_signal(163),
3695	-- grant(164) => grant_signal(164),
3696	-- grant(165) => grant_signal(165),
3697	-- fifo_full =>fifo_in_full(11),
3698	-- priority_rotation => priority_rotation_signal(11),
3699	-- fifo_empty => fifo_in_empty(11),
3700	-- data_out =>crossbar_in_port(11),
3701	-- data_out_pulse =>crossbar_in_pulse(11),
3702	-- request(151) =>request_signal(151),
3703	-- request(152) =>request_signal(152),
3704	-- request(153) =>request_signal(153),
3705	-- request(154) =>request_signal(154),
3706	-- request(155) =>request_signal(155),
3707	-- request(156) =>request_signal(156),
3708	-- request(157) =>request_signal(157),
3709	-- request(158) =>request_signal(158),
3710	-- request(159) =>request_signal(159),
3711	-- request(160) =>request_signal(160),
3712	-- request(161) =>request_signal(161),
3713	-- request(162) =>request_signal(162),
3714	-- request(163) =>request_signal(163),
3715	-- request(164) =>request_signal(164),
3716	-- request(165) =>request_signal(165)
3717	--);
3718	--
3719	--PORT12_INPUT_PORT_MODULE: INPUT_PORT_MODULE
3720	--GENERIC MAP(number_of_ports =>15)
3721	--PORT MAP(
3722	-- data_in => Port_in(12),
3723	-- data_in_en => data_in_en(12),
3724	-- reset => reset,
3725	-- clk =>clk,
3726	-- grant(166) => grant_signal(166),
3727	-- grant(167) => grant_signal(167),
3728	-- grant(168) => grant_signal(168),
3729	-- grant(169) => grant_signal(169),
3730	-- grant(170) => grant_signal(170),
3731	-- grant(171) => grant_signal(171),
3732	-- grant(172) => grant_signal(172),
3733	-- grant(173) => grant_signal(173),
3734	-- grant(174) => grant_signal(174),
3735	-- grant(175) => grant_signal(175),
3736	-- grant(176) => grant_signal(176),
3737	-- grant(177) => grant_signal(177),
3738	-- grant(178) => grant_signal(178),
3739	-- grant(179) => grant_signal(179),
3740	-- grant(180) => grant_signal(180),
3741	-- fifo_full =>fifo_in_full(12),
3742	-- priority_rotation => priority_rotation_signal(12),
3743	-- fifo_empty => fifo_in_empty(12),
3744	-- data_out =>crossbar_in_port(12),
3745	-- data_out_pulse =>crossbar_in_pulse(12),
3746	-- request(166) =>request_signal(166),
3747	-- request(167) =>request_signal(167),
3748	-- request(168) =>request_signal(168),
3749	-- request(169) =>request_signal(169),
3750	-- request(170) =>request_signal(170),
3751	-- request(171) =>request_signal(171),
3752	-- request(172) =>request_signal(172),
3753	-- request(173) =>request_signal(173),
3754	-- request(174) =>request_signal(174),
3755	-- request(175) =>request_signal(175),
3756	-- request(176) =>request_signal(176),
3757	-- request(177) =>request_signal(177),
3758	-- request(178) =>request_signal(178),
3759	-- request(179) =>request_signal(179),
3760	-- request(180) =>request_signal(180)
3761	--);
3762	--
3763	--PORT13_INPUT_PORT_MODULE: INPUT_PORT_MODULE
3764	--GENERIC MAP(number_of_ports =>15)
3765	--PORT MAP(
3766	-- data_in => Port_in(13),
3767	-- data_in_en => data_in_en(13),
3768	-- reset => reset,
3769	-- clk =>clk,
3770	-- grant(181) => grant_signal(181),
3771	-- grant(182) => grant_signal(182),
3772	-- grant(183) => grant_signal(183),
3773	-- grant(184) => grant_signal(184),
3774	-- grant(185) => grant_signal(185),
3775	-- grant(186) => grant_signal(186),
3776	-- grant(187) => grant_signal(187),
3777	-- grant(188) => grant_signal(188),
3778	-- grant(189) => grant_signal(189),
3779	-- grant(190) => grant_signal(190),
3780	-- grant(191) => grant_signal(191),
3781	-- grant(192) => grant_signal(192),
3782	-- grant(193) => grant_signal(193),
3783	-- grant(194) => grant_signal(194),
3784	-- grant(195) => grant_signal(195),
3785	-- fifo_full =>fifo_in_full(13),
3786	-- priority_rotation => priority_rotation_signal(13),
3787	-- fifo_empty => fifo_in_empty(13),
3788	-- data_out =>crossbar_in_port(13),
3789	-- data_out_pulse =>crossbar_in_pulse(13),
3790	-- request(181) =>request_signal(181),
3791	-- request(182) =>request_signal(182),
3792	-- request(183) =>request_signal(183),
3793	-- request(184) =>request_signal(184),
3794	-- request(185) =>request_signal(185),
3795	-- request(186) =>request_signal(186),
3796	-- request(187) =>request_signal(187),
3797	-- request(188) =>request_signal(188),
3798	-- request(189) =>request_signal(189),
3799	-- request(190) =>request_signal(190),
3800	-- request(191) =>request_signal(191),
3801	-- request(192) =>request_signal(192),
3802	-- request(193) =>request_signal(193),
3803	-- request(194) =>request_signal(194),
3804	-- request(195) =>request_signal(195)
3805	--);
3806	--
3807	--PORT14_INPUT_PORT_MODULE: INPUT_PORT_MODULE
3808	--GENERIC MAP(number_of_ports =>15)
3809	--PORT MAP(
3810	-- data_in => Port_in(14),
3811	-- data_in_en => data_in_en(14),
3812	-- reset => reset,
3813	-- clk =>clk,
3814	-- grant(196) => grant_signal(196),
3815	-- grant(197) => grant_signal(197),
3816	-- grant(198) => grant_signal(198),
3817	-- grant(199) => grant_signal(199),
3818	-- grant(200) => grant_signal(200),
3819	-- grant(201) => grant_signal(201),
3820	-- grant(202) => grant_signal(202),
3821	-- grant(203) => grant_signal(203),
3822	-- grant(204) => grant_signal(204),
3823	-- grant(205) => grant_signal(205),
3824	-- grant(206) => grant_signal(206),
3825	-- grant(207) => grant_signal(207),
3826	-- grant(208) => grant_signal(208),
3827	-- grant(209) => grant_signal(209),
3828	-- grant(210) => grant_signal(210),
3829	-- fifo_full =>fifo_in_full(14),
3830	-- priority_rotation => priority_rotation_signal(14),
3831	-- fifo_empty => fifo_in_empty(14),
3832	-- data_out =>crossbar_in_port(14),
3833	-- data_out_pulse =>crossbar_in_pulse(14),
3834	-- request(196) =>request_signal(196),
3835	-- request(197) =>request_signal(197),
3836	-- request(198) =>request_signal(198),
3837	-- request(199) =>request_signal(199),
3838	-- request(200) =>request_signal(200),
3839	-- request(201) =>request_signal(201),
3840	-- request(202) =>request_signal(202),
3841	-- request(203) =>request_signal(203),
3842	-- request(204) =>request_signal(204),
3843	-- request(205) =>request_signal(205),
3844	-- request(206) =>request_signal(206),
3845	-- request(207) =>request_signal(207),
3846	-- request(208) =>request_signal(208),
3847	-- request(209) =>request_signal(209),
3848	-- request(210) =>request_signal(210)
3849	--);
3850	--
3851	--PORT15_INPUT_PORT_MODULE: INPUT_PORT_MODULE
3852	--GENERIC MAP(number_of_ports =>15)
3853	--PORT MAP(
3854	-- data_in => Port_in(15),
3855	-- data_in_en => data_in_en(15),
3856	-- reset => reset,
3857	-- clk =>clk,
3858	-- grant(211) => grant_signal(211),
3859	-- grant(212) => grant_signal(212),
3860	-- grant(213) => grant_signal(213),
3861	-- grant(214) => grant_signal(214),
3862	-- grant(215) => grant_signal(215),
3863	-- grant(216) => grant_signal(216),
3864	-- grant(217) => grant_signal(217),
3865	-- grant(218) => grant_signal(218),
3866	-- grant(219) => grant_signal(219),
3867	-- grant(220) => grant_signal(220),
3868	-- grant(221) => grant_signal(221),
3869	-- grant(222) => grant_signal(222),
3870	-- grant(223) => grant_signal(223),
3871	-- grant(224) => grant_signal(224),
3872	-- grant(225) => grant_signal(225),
3873	-- fifo_full =>fifo_in_full(15),
3874	-- priority_rotation => priority_rotation_signal(15),
3875	-- fifo_empty => fifo_in_empty(15),
3876	-- data_out =>crossbar_in_port(15),
3877	-- data_out_pulse =>crossbar_in_pulse(15),
3878	-- request(211) =>request_signal(211),
3879	-- request(212) =>request_signal(212),
3880	-- request(213) =>request_signal(213),
3881	-- request(214) =>request_signal(214),
3882	-- request(215) =>request_signal(215),
3883	-- request(216) =>request_signal(216),
3884	-- request(217) =>request_signal(217),
3885	-- request(218) =>request_signal(218),
3886	-- request(219) =>request_signal(219),
3887	-- request(220) =>request_signal(220),
3888	-- request(221) =>request_signal(221),
3889	-- request(222) =>request_signal(222),
3890	-- request(223) =>request_signal(223),
3891	-- request(224) =>request_signal(224),
3892	-- request(225) =>request_signal(225)
3893	--);
3894	--
3895	--end generate switch15x15;
3896
3897
3898	-- switch 16 ports
3899	switch16x16 : if number_of_ports = 16 generate
3900	switch_16x16 :for i in 1 to number_of_ports generate
3901	Constant j : natural:=number_of_ports*(i-1);
3902	begin
3903	--j<=number_of_ports*(i-1);
3904	PORTx16_INPUT_PORT_MODULE: INPUT_PORT_MODULE
3905	GENERIC MAP(number_of_ports =>16,port_num=>i)
3906	PORT MAP(
3907	data_in => Port_in(i),
3908	data_in_en => data_in_en(i),
3909	cmd_in_en => cmd_in_en(i),
3910	reset => reset,
3911	clk =>clk,
3912	grant(1) => grant_signal(j+1),
3913	grant(2) => grant_signal(j+2),
3914	grant(3) => grant_signal(j+3),
3915	grant(4) => grant_signal(j+4),
3916	grant(5) => grant_signal(j+5),
3917	grant(6) => grant_signal(j+6),
3918	grant(7) => grant_signal(j+7),
3919	grant(8) => grant_signal(j+8),
3920	grant(9) => grant_signal(j+9),
3921	grant(10) => grant_signal(j+10),
3922	grant(11) => grant_signal(j+11),
3923	grant(12) => grant_signal(j+12),
3924	grant(13) => grant_signal(j+13),
3925	grant(14) => grant_signal(j+14),
3926	grant(15) => grant_signal(j+15),
3927	grant(16) => grant_signal(j+16),
3928	fifo_full =>fifo_in_full(i),
3929	priority_rotation => priority_rotation_signal(i),
3930	fifo_empty => fifo_in_empty(i),
3931	data_out =>crossbar_in_port(i),
3932	data_out_pulse =>crossbar_in_pulse(i),
3933	request(1) =>request_signal(j+1),
3934	request(2) =>request_signal(j+2),
3935	request(3) =>request_signal(j+3),
3936	request(4) =>request_signal(j+4),
3937	request(5) =>request_signal(j+5),
3938	request(6) =>request_signal(j+6),
3939	request(7) =>request_signal(j+7),
3940	request(8) =>request_signal(j+8),
3941	request(9) =>request_signal(j+9),
3942	request(10) =>request_signal(j+10),
3943	request(11) =>request_signal(j+11),
3944	request(12) =>request_signal(j+12),
3945	request(13) =>request_signal(j+13),
3946	request(14) =>request_signal(j+14),
3947	request(15) =>request_signal(j+15),
3948	request(16) =>request_signal(j+16)
3949	);
3950	end generate switch_16x16;
3951	end generate switch16x16;
3952	--PORT2_INPUT_PORT_MODULE: INPUT_PORT_MODULE
3953	--GENERIC MAP(number_of_ports =>16)
3954	--PORT MAP(
3955	-- data_in => Port_in(2),
3956	-- data_in_en => data_in_en(2),
3957	-- reset => reset,
3958	-- clk =>clk,
3959	-- grant(17) => grant_signal(17),
3960	-- grant(18) => grant_signal(18),
3961	-- grant(19) => grant_signal(19),
3962	-- grant(20) => grant_signal(20),
3963	-- grant(21) => grant_signal(21),
3964	-- grant(22) => grant_signal(22),
3965	-- grant(23) => grant_signal(23),
3966	-- grant(24) => grant_signal(24),
3967	-- grant(25) => grant_signal(25),
3968	-- grant(26) => grant_signal(26),
3969	-- grant(27) => grant_signal(27),
3970	-- grant(28) => grant_signal(28),
3971	-- grant(29) => grant_signal(29),
3972	-- grant(30) => grant_signal(30),
3973	-- grant(31) => grant_signal(31),
3974	-- grant(32) => grant_signal(32),
3975	-- fifo_full =>fifo_in_full(2),
3976	-- priority_rotation => priority_rotation_signal(2),
3977	-- fifo_empty => fifo_in_empty(2),
3978	-- data_out =>crossbar_in_port2,
3979	-- data_out_pulse =>crossbar_in_pulse(2,
3980	-- request(17) =>request_signal(17),
3981	-- request(18) =>request_signal(18),
3982	-- request(19) =>request_signal(19),
3983	-- request(20) =>request_signal(20),
3984	-- request(21) =>request_signal(21),
3985	-- request(22) =>request_signal(22),
3986	-- request(23) =>request_signal(23),
3987	-- request(24) =>request_signal(24),
3988	-- request(25) =>request_signal(25),
3989	-- request(26) =>request_signal(26),
3990	-- request(27) =>request_signal(27),
3991	-- request(28) =>request_signal(28),
3992	-- request(29) =>request_signal(29),
3993	-- request(30) =>request_signal(30),
3994	-- request(31) =>request_signal(31),
3995	-- request(32) =>request_signal(32)
3996	--);
3997	--
3998	--PORT3_INPUT_PORT_MODULE: INPUT_PORT_MODULE
3999	--GENERIC MAP(number_of_ports =>16)
4000	--PORT MAP(
4001	-- data_in => Port_in(3),
4002	-- data_in_en => data_in_en(3),
4003	-- reset => reset,
4004	-- clk =>clk,
4005	-- grant(33) => grant_signal(33),
4006	-- grant(34) => grant_signal(34),
4007	-- grant(35) => grant_signal(35),
4008	-- grant(36) => grant_signal(36),
4009	-- grant(37) => grant_signal(37),
4010	-- grant(38) => grant_signal(38),
4011	-- grant(39) => grant_signal(39),
4012	-- grant(40) => grant_signal(40),
4013	-- grant(41) => grant_signal(41),
4014	-- grant(42) => grant_signal(42),
4015	-- grant(43) => grant_signal(43),
4016	-- grant(44) => grant_signal(44),
4017	-- grant(45) => grant_signal(45),
4018	-- grant(46) => grant_signal(46),
4019	-- grant(47) => grant_signal(47),
4020	-- grant(48) => grant_signal(48),
4021	-- fifo_full =>fifo_in_full(3),
4022	-- priority_rotation => priority_rotation_signal(3),
4023	-- fifo_empty => fifo_in_empty(3),
4024	-- data_out =>crossbar_in_port3,
4025	-- data_out_pulse =>crossbar_in_pulse(3,
4026	-- request(33) =>request_signal(33),
4027	-- request(34) =>request_signal(34),
4028	-- request(35) =>request_signal(35),
4029	-- request(36) =>request_signal(36),
4030	-- request(37) =>request_signal(37),
4031	-- request(38) =>request_signal(38),
4032	-- request(39) =>request_signal(39),
4033	-- request(40) =>request_signal(40),
4034	-- request(41) =>request_signal(41),
4035	-- request(42) =>request_signal(42),
4036	-- request(43) =>request_signal(43),
4037	-- request(44) =>request_signal(44),
4038	-- request(45) =>request_signal(45),
4039	-- request(46) =>request_signal(46),
4040	-- request(47) =>request_signal(47),
4041	-- request(48) =>request_signal(48)
4042	--);
4043	--
4044	--PORT4_INPUT_PORT_MODULE: INPUT_PORT_MODULE
4045	--GENERIC MAP(number_of_ports =>16)
4046	--PORT MAP(
4047	-- data_in => Port_in(4),
4048	-- data_in_en => data_in_en(4),
4049	-- reset => reset,
4050	-- clk =>clk,
4051	-- grant(49) => grant_signal(49),
4052	-- grant(50) => grant_signal(50),
4053	-- grant(51) => grant_signal(51),
4054	-- grant(52) => grant_signal(52),
4055	-- grant(53) => grant_signal(53),
4056	-- grant(54) => grant_signal(54),
4057	-- grant(55) => grant_signal(55),
4058	-- grant(56) => grant_signal(56),
4059	-- grant(57) => grant_signal(57),
4060	-- grant(58) => grant_signal(58),
4061	-- grant(59) => grant_signal(59),
4062	-- grant(60) => grant_signal(60),
4063	-- grant(61) => grant_signal(61),
4064	-- grant(62) => grant_signal(62),
4065	-- grant(63) => grant_signal(63),
4066	-- grant(64) => grant_signal(64),
4067	-- fifo_full =>fifo_in_full(4),
4068	-- priority_rotation => priority_rotation_signal(4),
4069	-- fifo_empty => fifo_in_empty(4),
4070	-- data_out =>crossbar_in_port(4),
4071	-- data_out_pulse =>crossbar_in_pulse(4,
4072	-- request(49) =>request_signal(49),
4073	-- request(50) =>request_signal(50),
4074	-- request(51) =>request_signal(51),
4075	-- request(52) =>request_signal(52),
4076	-- request(53) =>request_signal(53),
4077	-- request(54) =>request_signal(54),
4078	-- request(55) =>request_signal(55),
4079	-- request(56) =>request_signal(56),
4080	-- request(57) =>request_signal(57),
4081	-- request(58) =>request_signal(58),
4082	-- request(59) =>request_signal(59),
4083	-- request(60) =>request_signal(60),
4084	-- request(61) =>request_signal(61),
4085	-- request(62) =>request_signal(62),
4086	-- request(63) =>request_signal(63),
4087	-- request(64) =>request_signal(64)
4088	--);
4089	--
4090	--PORT5_INPUT_PORT_MODULE: INPUT_PORT_MODULE
4091	--GENERIC MAP(number_of_ports =>16)
4092	--PORT MAP(
4093	-- data_in => Port_in(5),
4094	-- data_in_en => data_in_en(5),
4095	-- reset => reset,
4096	-- clk =>clk,
4097	-- grant(65) => grant_signal(65),
4098	-- grant(66) => grant_signal(66),
4099	-- grant(67) => grant_signal(67),
4100	-- grant(68) => grant_signal(68),
4101	-- grant(69) => grant_signal(69),
4102	-- grant(70) => grant_signal(70),
4103	-- grant(71) => grant_signal(71),
4104	-- grant(72) => grant_signal(72),
4105	-- grant(73) => grant_signal(73),
4106	-- grant(74) => grant_signal(74),
4107	-- grant(75) => grant_signal(75),
4108	-- grant(76) => grant_signal(76),
4109	-- grant(77) => grant_signal(77),
4110	-- grant(78) => grant_signal(78),
4111	-- grant(79) => grant_signal(79),
4112	-- grant(80) => grant_signal(80),
4113	-- fifo_full =>fifo_in_full(5),
4114	-- priority_rotation => priority_rotation_signal(5),
4115	-- fifo_empty => fifo_in_empty(5),
4116	-- data_out =>crossbar_in_port(5),
4117	-- data_out_pulse =>crossbar_in_pulse(5,
4118	-- request(65) =>request_signal(65),
4119	-- request(66) =>request_signal(66),
4120	-- request(67) =>request_signal(67),
4121	-- request(68) =>request_signal(68),
4122	-- request(69) =>request_signal(69),
4123	-- request(70) =>request_signal(70),
4124	-- request(71) =>request_signal(71),
4125	-- request(72) =>request_signal(72),
4126	-- request(73) =>request_signal(73),
4127	-- request(74) =>request_signal(74),
4128	-- request(75) =>request_signal(75),
4129	-- request(76) =>request_signal(76),
4130	-- request(77) =>request_signal(77),
4131	-- request(78) =>request_signal(78),
4132	-- request(79) =>request_signal(79),
4133	-- request(80) =>request_signal(80)
4134	--);
4135	--
4136	--PORT6_INPUT_PORT_MODULE: INPUT_PORT_MODULE
4137	--GENERIC MAP(number_of_ports =>16)
4138	--PORT MAP(
4139	-- data_in => Port_in(6),
4140	-- data_in_en => data_in_en(6),
4141	-- reset => reset,
4142	-- clk =>clk,
4143	-- grant(81) => grant_signal(81),
4144	-- grant(82) => grant_signal(82),
4145	-- grant(83) => grant_signal(83),
4146	-- grant(84) => grant_signal(84),
4147	-- grant(85) => grant_signal(85),
4148	-- grant(86) => grant_signal(86),
4149	-- grant(87) => grant_signal(87),
4150	-- grant(88) => grant_signal(88),
4151	-- grant(89) => grant_signal(89),
4152	-- grant(90) => grant_signal(90),
4153	-- grant(91) => grant_signal(91),
4154	-- grant(92) => grant_signal(92),
4155	-- grant(93) => grant_signal(93),
4156	-- grant(94) => grant_signal(94),
4157	-- grant(95) => grant_signal(95),
4158	-- grant(96) => grant_signal(96),
4159	-- fifo_full =>fifo_in_full(6),
4160	-- priority_rotation => priority_rotation_signal(6),
4161	-- fifo_empty => fifo_in_empty(6),
4162	-- data_out =>crossbar_in_port(6),
4163	-- data_out_pulse =>crossbar_in_pulse(6,
4164	-- request(81) =>request_signal(81),
4165	-- request(82) =>request_signal(82),
4166	-- request(83) =>request_signal(83),
4167	-- request(84) =>request_signal(84),
4168	-- request(85) =>request_signal(85),
4169	-- request(86) =>request_signal(86),
4170	-- request(87) =>request_signal(87),
4171	-- request(88) =>request_signal(88),
4172	-- request(89) =>request_signal(89),
4173	-- request(90) =>request_signal(90),
4174	-- request(91) =>request_signal(91),
4175	-- request(92) =>request_signal(92),
4176	-- request(93) =>request_signal(93),
4177	-- request(94) =>request_signal(94),
4178	-- request(95) =>request_signal(95),
4179	-- request(96) =>request_signal(96)
4180	--);
4181	--
4182	--PORT7_INPUT_PORT_MODULE: INPUT_PORT_MODULE
4183	--GENERIC MAP(number_of_ports =>16)
4184	--PORT MAP(
4185	-- data_in => Port_in(7),
4186	-- data_in_en => data_in_en(7),
4187	-- reset => reset,
4188	-- clk =>clk,
4189	-- grant(97) => grant_signal(97),
4190	-- grant(98) => grant_signal(98),
4191	-- grant(99) => grant_signal(99),
4192	-- grant(0) => grant_signal(100),
4193	-- grant(1) => grant_signal(101),
4194	-- grant(2) => grant_signal(102),
4195	-- grant(3) => grant_signal(103),
4196	-- grant(4) => grant_signal(104),
4197	-- grant(5) => grant_signal(105),
4198	-- grant(6) => grant_signal(106),
4199	-- grant(7) => grant_signal(107),
4200	-- grant(8) => grant_signal(108),
4201	-- grant(9) => grant_signal(109),
4202	-- grant(110) => grant_signal(110),
4203	-- grant(111) => grant_signal(111),
4204	-- grant(112) => grant_signal(112),
4205	-- fifo_full =>fifo_in_full(7),
4206	-- priority_rotation => priority_rotation_signal(7),
4207	-- fifo_empty => fifo_in_empty(7),
4208	-- data_out =>crossbar_in_port(8),
4209	-- data_out_pulse =>crossbar_in_pulse(7,
4210	-- request(97) =>request_signal(97),
4211	-- request(98) =>request_signal(98),
4212	-- request(99) =>request_signal(99),
4213	-- request(100) =>request_signal(100),
4214	-- request(101) =>request_signal(101),
4215	-- request(102) =>request_signal(102),
4216	-- request(103) =>request_signal(103),
4217	-- request(104) =>request_signal(104),
4218	-- request(105) =>request_signal(105),
4219	-- request(106) =>request_signal(106),
4220	-- request(107) =>request_signal(107),
4221	-- request(108) =>request_signal(108),
4222	-- request(109) =>request_signal(109),
4223	-- request(110) =>request_signal(110),
4224	-- request(111) =>request_signal(111),
4225	-- request(112) =>request_signal(112)
4226	--);
4227	--
4228	--PORT8_INPUT_PORT_MODULE: INPUT_PORT_MODULE
4229	--GENERIC MAP(number_of_ports =>16)
4230	--PORT MAP(
4231	-- data_in => Port_in(8),
4232	-- data_in_en => data_in_en(8),
4233	-- reset => reset,
4234	-- clk =>clk,
4235	-- grant(113) => grant_signal(113),
4236	-- grant(114) => grant_signal(114),
4237	-- grant(115) => grant_signal(115),
4238	-- grant(116) => grant_signal(116),
4239	-- grant(117) => grant_signal(117),
4240	-- grant(118) => grant_signal(118),
4241	-- grant(119) => grant_signal(119),
4242	-- grant(120) => grant_signal(120),
4243	-- grant(121) => grant_signal(121),
4244	-- grant(122) => grant_signal(122),
4245	-- grant(123) => grant_signal(123),
4246	-- grant(124) => grant_signal(124),
4247	-- grant(125) => grant_signal(125),
4248	-- grant(126) => grant_signal(126),
4249	-- grant(127) => grant_signal(127),
4250	-- grant(128) => grant_signal(128),
4251	-- fifo_full =>fifo_in_full(8),
4252	-- priority_rotation => priority_rotation_signal(8),
4253	-- fifo_empty => fifo_in_empty(8),
4254	-- data_out =>crossbar_in_port8,
4255	-- data_out_pulse =>crossbar_in_pulse(8,
4256	-- request(113) =>request_signal(113),
4257	-- request(114) =>request_signal(114),
4258	-- request(115) =>request_signal(115),
4259	-- request(116) =>request_signal(116),
4260	-- request(117) =>request_signal(117),
4261	-- request(118) =>request_signal(118),
4262	-- request(119) =>request_signal(119),
4263	-- request(120) =>request_signal(120),
4264	-- request(121) =>request_signal(121),
4265	-- request(122) =>request_signal(122),
4266	-- request(123) =>request_signal(123),
4267	-- request(124) =>request_signal(124),
4268	-- request(125) =>request_signal(125),
4269	-- request(126) =>request_signal(126),
4270	-- request(127) =>request_signal(127),
4271	-- request(128) =>request_signal(128)
4272	--);
4273	--
4274	--PORT9_INPUT_PORT_MODULE: INPUT_PORT_MODULE
4275	--GENERIC MAP(number_of_ports =>16)
4276	--PORT MAP(
4277	-- data_in => Port_in(9),
4278	-- data_in_en => data_in_en(9),
4279	-- reset => reset,
4280	-- clk =>clk,
4281	-- grant(129) => grant_signal(129),
4282	-- grant(130) => grant_signal(130),
4283	-- grant(131) => grant_signal(131),
4284	-- grant(132) => grant_signal(132),
4285	-- grant(133) => grant_signal(133),
4286	-- grant(134) => grant_signal(134),
4287	-- grant(135) => grant_signal(135),
4288	-- grant(136) => grant_signal(136),
4289	-- grant(137) => grant_signal(137),
4290	-- grant(138) => grant_signal(138),
4291	-- grant(139) => grant_signal(139),
4292	-- grant(140) => grant_signal(140),
4293	-- grant(141) => grant_signal(141),
4294	-- grant(142) => grant_signal(142),
4295	-- grant(143) => grant_signal(143),
4296	-- grant(144) => grant_signal(144),
4297	-- fifo_full =>fifo_in_full(9),
4298	-- priority_rotation => priority_rotation_signal(9),
4299	-- fifo_empty => fifo_in_empty(9),
4300	-- data_out =>crossbar_in_port9,
4301	-- data_out_pulse =>crossbar_in_pulse(9),
4302	-- request(129) =>request_signal(129),
4303	-- request(130) =>request_signal(130),
4304	-- request(131) =>request_signal(131),
4305	-- request(132) =>request_signal(132),
4306	-- request(133) =>request_signal(133),
4307	-- request(134) =>request_signal(134),
4308	-- request(135) =>request_signal(135),
4309	-- request(136) =>request_signal(136),
4310	-- request(137) =>request_signal(137),
4311	-- request(138) =>request_signal(138),
4312	-- request(139) =>request_signal(139),
4313	-- request(140) =>request_signal(140),
4314	-- request(141) =>request_signal(141),
4315	-- request(142) =>request_signal(142),
4316	-- request(143) =>request_signal(143),
4317	-- request(144) =>request_signal(144)
4318	--);
4319	--
4320	--PORT10_INPUT_PORT_MODULE: INPUT_PORT_MODULE
4321	--GENERIC MAP(number_of_ports =>16)
4322	--PORT MAP(
4323	-- data_in => Port_in(10),
4324	-- data_in_en => data_in_en(10),
4325	-- reset => reset,
4326	-- clk =>clk,
4327	-- grant(145) => grant_signal(145),
4328	-- grant(146) => grant_signal(146),
4329	-- grant(147) => grant_signal(147),
4330	-- grant(148) => grant_signal(148),
4331	-- grant(149) => grant_signal(149),
4332	-- grant(150) => grant_signal(150),
4333	-- grant(151) => grant_signal(151),
4334	-- grant(152) => grant_signal(152),
4335	-- grant(153) => grant_signal(153),
4336	-- grant(154) => grant_signal(154),
4337	-- grant(155) => grant_signal(155),
4338	-- grant(156) => grant_signal(156),
4339	-- grant(157) => grant_signal(157),
4340	-- grant(158) => grant_signal(158),
4341	-- grant(159) => grant_signal(159),
4342	-- grant(160) => grant_signal(160),
4343	-- fifo_full =>fifo_in_full(10),
4344	-- priority_rotation => priority_rotation_signal(10),
4345	-- fifo_empty => fifo_in_empty(10),
4346	-- data_out =>crossbar_in_port(10),
4347	-- data_out_pulse =>crossbar_in_pulse(10),
4348	-- request(145) =>request_signal(145),
4349	-- request(146) =>request_signal(146),
4350	-- request(147) =>request_signal(147),
4351	-- request(148) =>request_signal(148),
4352	-- request(149) =>request_signal(149),
4353	-- request(150) =>request_signal(150),
4354	-- request(151) =>request_signal(151),
4355	-- request(152) =>request_signal(152),
4356	-- request(153) =>request_signal(153),
4357	-- request(154) =>request_signal(154),
4358	-- request(155) =>request_signal(155),
4359	-- request(156) =>request_signal(156),
4360	-- request(157) =>request_signal(157),
4361	-- request(158) =>request_signal(158),
4362	-- request(159) =>request_signal(159),
4363	-- request(160) =>request_signal(160)
4364	--);
4365	--
4366	--PORT11_INPUT_PORT_MODULE: INPUT_PORT_MODULE
4367	--GENERIC MAP(number_of_ports =>16)
4368	--PORT MAP(
4369	-- data_in => Port_in(11),
4370	-- data_in_en => data_in_en(11),
4371	-- reset => reset,
4372	-- clk =>clk,
4373	-- grant(161) => grant_signal(161),
4374	-- grant(162) => grant_signal(162),
4375	-- grant(163) => grant_signal(163),
4376	-- grant(164) => grant_signal(164),
4377	-- grant(165) => grant_signal(165),
4378	-- grant(166) => grant_signal(166),
4379	-- grant(167) => grant_signal(167),
4380	-- grant(168) => grant_signal(168),
4381	-- grant(169) => grant_signal(169),
4382	-- grant(170) => grant_signal(170),
4383	-- grant(171) => grant_signal(171),
4384	-- grant(172) => grant_signal(172),
4385	-- grant(173) => grant_signal(173),
4386	-- grant(174) => grant_signal(174),
4387	-- grant(175) => grant_signal(175),
4388	-- grant(176) => grant_signal(176),
4389	-- fifo_full =>fifo_in_full(11),
4390	-- priority_rotation => priority_rotation_signal(11),
4391	-- fifo_empty => fifo_in_empty(11),
4392	-- data_out =>crossbar_in_port(11),
4393	-- data_out_pulse =>crossbar_in_pulse(11),
4394	-- request(161) =>request_signal(161),
4395	-- request(162) =>request_signal(162),
4396	-- request(163) =>request_signal(163),
4397	-- request(164) =>request_signal(164),
4398	-- request(165) =>request_signal(165),
4399	-- request(166) =>request_signal(166),
4400	-- request(167) =>request_signal(167),
4401	-- request(168) =>request_signal(168),
4402	-- request(169) =>request_signal(169),
4403	-- request(170) =>request_signal(170),
4404	-- request(171) =>request_signal(171),
4405	-- request(172) =>request_signal(172),
4406	-- request(173) =>request_signal(173),
4407	-- request(174) =>request_signal(174),
4408	-- request(175) =>request_signal(175),
4409	-- request(176) =>request_signal(176)
4410	--);
4411	--
4412	--PORT12_INPUT_PORT_MODULE: INPUT_PORT_MODULE
4413	--GENERIC MAP(number_of_ports =>16)
4414	--PORT MAP(
4415	-- data_in => Port_in(12),
4416	-- data_in_en => data_in_en(12),
4417	-- reset => reset,
4418	-- clk =>clk,
4419	-- grant(177) => grant_signal(177),
4420	-- grant(178) => grant_signal(178),
4421	-- grant(179) => grant_signal(179),
4422	-- grant(180) => grant_signal(180),
4423	-- grant(181) => grant_signal(181),
4424	-- grant(182) => grant_signal(182),
4425	-- grant(183) => grant_signal(183),
4426	-- grant(184) => grant_signal(184),
4427	-- grant(185) => grant_signal(185),
4428	-- grant(186) => grant_signal(186),
4429	-- grant(187) => grant_signal(187),
4430	-- grant(188) => grant_signal(188),
4431	-- grant(189) => grant_signal(189),
4432	-- grant(190) => grant_signal(190),
4433	-- grant(191) => grant_signal(191),
4434	-- grant(192) => grant_signal(192),
4435	-- fifo_full =>fifo_in_full(12),
4436	-- priority_rotation => priority_rotation_signal(12),
4437	-- fifo_empty => fifo_in_empty(12),
4438	-- data_out =>crossbar_in_port(12),
4439	-- data_out_pulse =>crossbar_in_pulse(12),
4440	-- request(177) =>request_signal(177),
4441	-- request(178) =>request_signal(178),
4442	-- request(179) =>request_signal(179),
4443	-- request(180) =>request_signal(180),
4444	-- request(181) =>request_signal(181),
4445	-- request(182) =>request_signal(182),
4446	-- request(183) =>request_signal(183),
4447	-- request(184) =>request_signal(184),
4448	-- request(185) =>request_signal(185),
4449	-- request(186) =>request_signal(186),
4450	-- request(187) =>request_signal(187),
4451	-- request(188) =>request_signal(188),
4452	-- request(189) =>request_signal(189),
4453	-- request(190) =>request_signal(190),
4454	-- request(191) =>request_signal(191),
4455	-- request(192) =>request_signal(192)
4456	--);
4457	--
4458	--PORT13_INPUT_PORT_MODULE: INPUT_PORT_MODULE
4459	--GENERIC MAP(number_of_ports =>16)
4460	--PORT MAP(
4461	-- data_in => Port_in(13),
4462	-- data_in_en => data_in_en(13),
4463	-- reset => reset,
4464	-- clk =>clk,
4465	-- grant(193) => grant_signal(193),
4466	-- grant(194) => grant_signal(194),
4467	-- grant(195) => grant_signal(195),
4468	-- grant(196) => grant_signal(196),
4469	-- grant(197) => grant_signal(197),
4470	-- grant(198) => grant_signal(198),
4471	-- grant(199) => grant_signal(199),
4472	-- grant(200) => grant_signal(200),
4473	-- grant(201) => grant_signal(201),
4474	-- grant(202) => grant_signal(202),
4475	-- grant(203) => grant_signal(203),
4476	-- grant(204) => grant_signal(204),
4477	-- grant(205) => grant_signal(205),
4478	-- grant(206) => grant_signal(206),
4479	-- grant(207) => grant_signal(207),
4480	-- grant(208) => grant_signal(208),
4481	-- fifo_full =>fifo_in_full(13),
4482	-- priority_rotation => priority_rotation_signal(13),
4483	-- fifo_empty => fifo_in_empty(13),
4484	-- data_out =>crossbar_in_port13,
4485	-- data_out_pulse =>crossbar_in_pulse(13,
4486	-- request(193) =>request_signal(193),
4487	-- request(194) =>request_signal(194),
4488	-- request(195) =>request_signal(195),
4489	-- request(196) =>request_signal(196),
4490	-- request(197) =>request_signal(197),
4491	-- request(198) =>request_signal(198),
4492	-- request(199) =>request_signal(199),
4493	-- request(200) =>request_signal(200),
4494	-- request(201) =>request_signal(201),
4495	-- request(202) =>request_signal(202),
4496	-- request(203) =>request_signal(203),
4497	-- request(204) =>request_signal(204),
4498	-- request(205) =>request_signal(205),
4499	-- request(206) =>request_signal(206),
4500	-- request(207) =>request_signal(207),
4501	-- request(208) =>request_signal(208)
4502	--);
4503	--
4504	--PORT14_INPUT_PORT_MODULE: INPUT_PORT_MODULE
4505	--GENERIC MAP(number_of_ports =>16)
4506	--PORT MAP(
4507	-- data_in => Port_in(14),
4508	-- data_in_en => data_in_en(14),
4509	-- reset => reset,
4510	-- clk =>clk,
4511	-- grant(209) => grant_signal(209),
4512	-- grant(210) => grant_signal(210),
4513	-- grant(211) => grant_signal(211),
4514	-- grant(212) => grant_signal(212),
4515	-- grant(213) => grant_signal(213),
4516	-- grant(214) => grant_signal(214),
4517	-- grant(215) => grant_signal(215),
4518	-- grant(216) => grant_signal(216),
4519	-- grant(217) => grant_signal(217),
4520	-- grant(218) => grant_signal(218),
4521	-- grant(219) => grant_signal(219),
4522	-- grant(220) => grant_signal(220),
4523	-- grant(221) => grant_signal(221),
4524	-- grant(222) => grant_signal(222),
4525	-- grant(223) => grant_signal(223),
4526	-- grant(224) => grant_signal(224),
4527	-- fifo_full =>fifo_in_full(14),
4528	-- priority_rotation => priority_rotation_signal(14),
4529	-- fifo_empty => fifo_in_empty(14),
4530	-- data_out =>crossbar_in_port(14),
4531	-- data_out_pulse =>crossbar_in_pulse(14),
4532	-- request(209) =>request_signal(209),
4533	-- request(210) =>request_signal(210),
4534	-- request(211) =>request_signal(211),
4535	-- request(212) =>request_signal(212),
4536	-- request(213) =>request_signal(213),
4537	-- request(214) =>request_signal(214),
4538	-- request(215) =>request_signal(215),
4539	-- request(216) =>request_signal(216),
4540	-- request(217) =>request_signal(217),
4541	-- request(218) =>request_signal(218),
4542	-- request(219) =>request_signal(219),
4543	-- request(220) =>request_signal(220),
4544	-- request(221) =>request_signal(221),
4545	-- request(222) =>request_signal(222),
4546	-- request(223) =>request_signal(223),
4547	-- request(224) =>request_signal(224)
4548	--);
4549	--
4550	--PORT15_INPUT_PORT_MODULE: INPUT_PORT_MODULE
4551	--GENERIC MAP(number_of_ports =>16)
4552	--PORT MAP(
4553	-- data_in => Port_in(15),
4554	-- data_in_en => data_in_en(15),
4555	-- reset => reset,
4556	-- clk =>clk,
4557	-- grant(225) => grant_signal(225),
4558	-- grant(226) => grant_signal(226),
4559	-- grant(227) => grant_signal(227),
4560	-- grant(228) => grant_signal(228),
4561	-- grant(229) => grant_signal(229),
4562	-- grant(230) => grant_signal(230),
4563	-- grant(231) => grant_signal(231),
4564	-- grant(232) => grant_signal(232),
4565	-- grant(233) => grant_signal(233),
4566	-- grant(234) => grant_signal(234),
4567	-- grant(235) => grant_signal(235),
4568	-- grant(236) => grant_signal(236),
4569	-- grant(237) => grant_signal(237),
4570	-- grant(238) => grant_signal(238),
4571	-- grant(239) => grant_signal(239),
4572	-- grant(240) => grant_signal(240),
4573	-- fifo_full =>fifo_in_full(15),
4574	-- priority_rotation => priority_rotation_signal(15),
4575	-- fifo_empty => fifo_in_empty(15),
4576	-- data_out =>crossbar_in_port(15),
4577	-- data_out_pulse =>crossbar_in_pulse(15),
4578	-- request(225) =>request_signal(225),
4579	-- request(226) =>request_signal(226),
4580	-- request(227) =>request_signal(227),
4581	-- request(228) =>request_signal(228),
4582	-- request(229) =>request_signal(229),
4583	-- request(230) =>request_signal(230),
4584	-- request(231) =>request_signal(231),
4585	-- request(232) =>request_signal(232),
4586	-- request(233) =>request_signal(233),
4587	-- request(234) =>request_signal(234),
4588	-- request(235) =>request_signal(235),
4589	-- request(236) =>request_signal(236),
4590	-- request(237) =>request_signal(237),
4591	-- request(238) =>request_signal(238),
4592	-- request(239) =>request_signal(239),
4593	-- request(240) =>request_signal(240)
4594	--);
4595	--
4596	--PORT16_INPUT_PORT_MODULE: INPUT_PORT_MODULE
4597	--GENERIC MAP(number_of_ports =>16)
4598	--PORT MAP(
4599	-- data_in => Port_in(16),
4600	-- data_in_en => data_in_en(16),
4601	-- reset => reset,
4602	-- clk =>clk,
4603	-- grant(241) => grant_signal(241),
4604	-- grant(242) => grant_signal(242),
4605	-- grant(243) => grant_signal(243),
4606	-- grant(244) => grant_signal(244),
4607	-- grant(245) => grant_signal(245),
4608	-- grant(246) => grant_signal(246),
4609	-- grant(247) => grant_signal(247),
4610	-- grant(248) => grant_signal(248),
4611	-- grant(249) => grant_signal(249),
4612	-- grant(250) => grant_signal(250),
4613	-- grant(251) => grant_signal(251),
4614	-- grant(252) => grant_signal(252),
4615	-- grant(253) => grant_signal(253),
4616	-- grant(254) => grant_signal(254),
4617	-- grant(255) => grant_signal(255),
4618	-- grant(256) => grant_signal(256),
4619	-- fifo_full =>fifo_in_full(16),
4620	-- priority_rotation => priority_rotation_signal(16),
4621	-- fifo_empty => fifo_in_empty(16),
4622	-- data_out =>crossbar_in_port(16),
4623	-- data_out_pulse =>crossbar_in_pulse(16),
4624	-- request(241) =>request_signal(241),
4625	-- request(242) =>request_signal(242),
4626	-- request(243) =>request_signal(243),
4627	-- request(244) =>request_signal(244),
4628	-- request(245) =>request_signal(245),
4629	-- request(246) =>request_signal(246),
4630	-- request(247) =>request_signal(247),
4631	-- request(248) =>request_signal(248),
4632	-- request(249) =>request_signal(249),
4633	-- request(250) =>request_signal(250),
4634	-- request(251) =>request_signal(251),
4635	-- request(252) =>request_signal(252),
4636	-- request(253) =>request_signal(253),
4637	-- request(254) =>request_signal(254),
4638	-- request(255) =>request_signal(255),
4639	-- request(256) =>request_signal(256)
4640	--);
4641	--
4642	--end generate switch16x16;
4643	-- intstanciation et connexion des modules des ports de sorties fonction du nombre de ports
4644	-- le circuit genere depend du parametre generique nombre de ports
4645	-- switch 2 ports
4646	port_out_switch2x2 : if number_of_ports = 2 generate
4647
4648	PORT1_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE
4649	PORT MAP(
4650	data_in => crossbar_out_port(1),
4651	reset => reset,
4652	clk => clk,
4653	wr_en =>crossbar_out_pulse(1),
4654	data_out =>Port_out(1),
4655	fifo_full =>fifo_out_full_signal(1),
4656	data_avalaible => data_available(1),
4657	rd_out_en => data_out_en(1)
4658	);
4659
4660	PORT2_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE
4661	PORT MAP(
4662	data_in => crossbar_out_port(2),
4663	reset => reset,
4664	clk => clk,
4665	wr_en =>crossbar_out_pulse(2),
4666	data_out =>Port_out(2),
4667	fifo_full =>fifo_out_full_signal(2),
4668	data_avalaible => data_available(2),
4669	rd_out_en => data_out_en(2)
4670	);
4671
4672	end generate port_out_switch2x2;
4673
4674
4675	-- switch 3 ports
4676	port_out_switch3x3 : if number_of_ports = 3 generate
4677
4678	PORT1_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE
4679	PORT MAP(
4680	data_in => crossbar_out_port(1),
4681	reset => reset,
4682	clk => clk,
4683	wr_en =>crossbar_out_pulse(1),
4684	data_out =>Port_out(1),
4685	fifo_full =>fifo_out_full_signal(1),
4686	data_avalaible => data_available(1),
4687	rd_out_en => data_out_en(1)
4688	);
4689
4690	PORT2_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE
4691	PORT MAP(
4692	data_in => crossbar_out_port(2),
4693	reset => reset,
4694	clk => clk,
4695	wr_en =>crossbar_out_pulse(2),
4696	data_out =>Port_out(2),
4697	fifo_full =>fifo_out_full_signal(2),
4698	data_avalaible => data_available(2),
4699	rd_out_en => data_out_en(2)
4700	);
4701
4702	PORT3_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE
4703	PORT MAP(
4704	data_in => crossbar_out_port(3),
4705	reset => reset,
4706	clk => clk,
4707	wr_en =>crossbar_out_pulse(3),
4708	data_out =>Port_out(3),
4709	fifo_full =>fifo_out_full_signal(3),
4710	data_avalaible => data_available(3),
4711	rd_out_en => data_out_en(3)
4712	);
4713
4714	end generate port_out_switch3x3;
4715
4716
4717	-- switch 4 ports
4718	port_out_switch4x4 : if number_of_ports = 4 generate
4719
4720	PORT1_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE
4721	PORT MAP(
4722	data_in => crossbar_out_port(1),
4723	reset => reset,
4724	clk => clk,
4725	wr_en =>crossbar_out_pulse(1),
4726	data_out =>Port_out(1),
4727	fifo_full =>fifo_out_full_signal(1),
4728	data_avalaible => data_available(1),
4729	rd_out_en => data_out_en(1)
4730	);
4731
4732	PORT2_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE
4733	PORT MAP(
4734	data_in => crossbar_out_port(2),
4735	reset => reset,
4736	clk => clk,
4737	wr_en =>crossbar_out_pulse(2),
4738	data_out =>Port_out(2),
4739	fifo_full =>fifo_out_full_signal(2),
4740	data_avalaible => data_available(2),
4741	rd_out_en => data_out_en(2)
4742	);
4743
4744	PORT3_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE
4745	PORT MAP(
4746	data_in => crossbar_out_port(3),
4747	reset => reset,
4748	clk => clk,
4749	wr_en =>crossbar_out_pulse(3),
4750	data_out =>Port_out(3),
4751	fifo_full =>fifo_out_full_signal(3),
4752	data_avalaible => data_available(3),
4753	rd_out_en => data_out_en(3)
4754	);
4755
4756	PORT4_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE
4757	PORT MAP(
4758	data_in => crossbar_out_port(4),
4759	reset => reset,
4760	clk => clk,
4761	wr_en =>crossbar_out_pulse(4),
4762	data_out =>Port_out(4),
4763	fifo_full =>fifo_out_full_signal(4),
4764	data_avalaible => data_available(4),
4765	rd_out_en => data_out_en(4)
4766	);
4767
4768	end generate port_out_switch4x4;
4769
4770
4771	-- switch 5 ports
4772	port_out_switch5x5 : if number_of_ports = 5 generate
4773
4774	PORT1_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE
4775	PORT MAP(
4776	data_in => crossbar_out_port(1),
4777	reset => reset,
4778	clk => clk,
4779	wr_en =>crossbar_out_pulse(1),
4780	data_out =>Port_out(1),
4781	fifo_full =>fifo_out_full_signal(1),
4782	data_avalaible => data_available(1),
4783	rd_out_en => data_out_en(1)
4784	);
4785
4786	PORT2_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE
4787	PORT MAP(
4788	data_in => crossbar_out_port(2),
4789	reset => reset,
4790	clk => clk,
4791	wr_en =>crossbar_out_pulse(2),
4792	data_out =>Port_out(2),
4793	fifo_full =>fifo_out_full_signal(2),
4794	data_avalaible => data_available(2),
4795	rd_out_en => data_out_en(2)
4796	);
4797
4798	PORT3_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE
4799	PORT MAP(
4800	data_in => crossbar_out_port(3),
4801	reset => reset,
4802	clk => clk,
4803	wr_en =>crossbar_out_pulse(3),
4804	data_out =>Port_out(3),
4805	fifo_full =>fifo_out_full_signal(3),
4806	data_avalaible => data_available(3),
4807	rd_out_en => data_out_en(3)
4808	);
4809
4810	PORT4_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE
4811	PORT MAP(
4812	data_in => crossbar_out_port(4),
4813	reset => reset,
4814	clk => clk,
4815	wr_en =>crossbar_out_pulse(4),
4816	data_out =>Port_out(4),
4817	fifo_full =>fifo_out_full_signal(4),
4818	data_avalaible => data_available(4),
4819	rd_out_en => data_out_en(4)
4820	);
4821
4822	PORT5_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE
4823	PORT MAP(
4824	data_in => crossbar_out_port(5),
4825	reset => reset,
4826	clk => clk,
4827	wr_en =>crossbar_out_pulse(5),
4828	data_out =>Port_out(5),
4829	fifo_full =>fifo_out_full_signal(5),
4830	data_avalaible => data_available(5),
4831	rd_out_en => data_out_en(5)
4832	);
4833
4834	end generate port_out_switch5x5;
4835
4836
4837	-- switch 6 ports
4838	port_out_switch6x6 : if number_of_ports = 6 generate
4839
4840	PORT1_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE
4841	PORT MAP(
4842	data_in => crossbar_out_port(1),
4843	reset => reset,
4844	clk => clk,
4845	wr_en =>crossbar_out_pulse(1),
4846	data_out =>Port_out(1),
4847	fifo_full =>fifo_out_full_signal(1),
4848	data_avalaible => data_available(1),
4849	rd_out_en => data_out_en(1)
4850	);
4851
4852	PORT2_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE
4853	PORT MAP(
4854	data_in => crossbar_out_port(2),
4855	reset => reset,
4856	clk => clk,
4857	wr_en =>crossbar_out_pulse(2),
4858	data_out =>Port_out(2),
4859	fifo_full =>fifo_out_full_signal(2),
4860	data_avalaible => data_available(2),
4861	rd_out_en => data_out_en(2)
4862	);
4863
4864	PORT3_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE
4865	PORT MAP(
4866	data_in => crossbar_out_port(3),
4867	reset => reset,
4868	clk => clk,
4869	wr_en =>crossbar_out_pulse(3),
4870	data_out =>Port_out(3),
4871	fifo_full =>fifo_out_full_signal(3),
4872	data_avalaible => data_available(3),
4873	rd_out_en => data_out_en(3)
4874	);
4875
4876	PORT4_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE
4877	PORT MAP(
4878	data_in => crossbar_out_port(4),
4879	reset => reset,
4880	clk => clk,
4881	wr_en =>crossbar_out_pulse(4),
4882	data_out =>Port_out(4),
4883	fifo_full =>fifo_out_full_signal(4),
4884	data_avalaible => data_available(4),
4885	rd_out_en => data_out_en(4)
4886	);
4887
4888	PORT5_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE
4889	PORT MAP(
4890	data_in => crossbar_out_port(5),
4891	reset => reset,
4892	clk => clk,
4893	wr_en =>crossbar_out_pulse(5),
4894	data_out =>Port_out(5),
4895	fifo_full =>fifo_out_full_signal(5),
4896	data_avalaible => data_available(5),
4897	rd_out_en => data_out_en(5)
4898	);
4899
4900	PORT6_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE
4901	PORT MAP(
4902	data_in => crossbar_out_port(6),
4903	reset => reset,
4904	clk => clk,
4905	wr_en =>crossbar_out_pulse(6),
4906	data_out =>Port_out(6),
4907	fifo_full =>fifo_out_full_signal(6),
4908	data_avalaible => data_available(6),
4909	rd_out_en => data_out_en(6)
4910	);
4911
4912	end generate port_out_switch6x6;
4913
4914
4915	-- switch 7 ports
4916	port_out_switch7x7 : if number_of_ports = 7 generate
4917
4918	PORT1_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE
4919	PORT MAP(
4920	data_in => crossbar_out_port(1),
4921	reset => reset,
4922	clk => clk,
4923	wr_en =>crossbar_out_pulse(1),
4924	data_out =>Port_out(1),
4925	fifo_full =>fifo_out_full_signal(1),
4926	data_avalaible => data_available(1),
4927	rd_out_en => data_out_en(1)
4928	);
4929
4930	PORT2_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE
4931	PORT MAP(
4932	data_in => crossbar_out_port(2),
4933	reset => reset,
4934	clk => clk,
4935	wr_en =>crossbar_out_pulse(2),
4936	data_out =>Port_out(2),
4937	fifo_full =>fifo_out_full_signal(2),
4938	data_avalaible => data_available(2),
4939	rd_out_en => data_out_en(2)
4940	);
4941
4942	PORT3_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE
4943	PORT MAP(
4944	data_in => crossbar_out_port(3),
4945	reset => reset,
4946	clk => clk,
4947	wr_en =>crossbar_out_pulse(3),
4948	data_out =>Port_out(3),
4949	fifo_full =>fifo_out_full_signal(3),
4950	data_avalaible => data_available(3),
4951	rd_out_en => data_out_en(3)
4952	);
4953
4954	PORT4_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE
4955	PORT MAP(
4956	data_in => crossbar_out_port(4),
4957	reset => reset,
4958	clk => clk,
4959	wr_en =>crossbar_out_pulse(4),
4960	data_out =>Port_out(4),
4961	fifo_full =>fifo_out_full_signal(4),
4962	data_avalaible => data_available(4),
4963	rd_out_en => data_out_en(4)
4964	);
4965
4966	PORT5_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE
4967	PORT MAP(
4968	data_in => crossbar_out_port(5),
4969	reset => reset,
4970	clk => clk,
4971	wr_en =>crossbar_out_pulse(5),
4972	data_out =>Port_out(5),
4973	fifo_full =>fifo_out_full_signal(5),
4974	data_avalaible => data_available(5),
4975	rd_out_en => data_out_en(5)
4976	);
4977
4978	PORT6_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE
4979	PORT MAP(
4980	data_in => crossbar_out_port(6),
4981	reset => reset,
4982	clk => clk,
4983	wr_en =>crossbar_out_pulse(6),
4984	data_out =>Port_out(6),
4985	fifo_full =>fifo_out_full_signal(6),
4986	data_avalaible => data_available(6),
4987	rd_out_en => data_out_en(6)
4988	);
4989
4990	PORT7_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE
4991	PORT MAP(
4992	data_in => crossbar_out_port(7),
4993	reset => reset,
4994	clk => clk,
4995	wr_en =>crossbar_out_pulse(7),
4996	data_out =>Port_out(7),
4997	fifo_full =>fifo_out_full_signal(7),
4998	data_avalaible => data_available(7),
4999	rd_out_en => data_out_en(7)
5000	);
5001
5002	end generate port_out_switch7x7;
5003
5004
5005	-- switch 8 ports
5006	port_out_switch8x8 : if number_of_ports = 8 generate
5007
5008	PORT1_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE
5009	PORT MAP(
5010	data_in => crossbar_out_port(1),
5011	reset => reset,
5012	clk => clk,
5013	wr_en =>crossbar_out_pulse(1),
5014	data_out =>Port_out(1),
5015	fifo_full =>fifo_out_full_signal(1),
5016	data_avalaible => data_available(1),
5017	rd_out_en => data_out_en(1)
5018	);
5019
5020	PORT2_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE
5021	PORT MAP(
5022	data_in => crossbar_out_port(2),
5023	reset => reset,
5024	clk => clk,
5025	wr_en =>crossbar_out_pulse(2),
5026	data_out =>Port_out(2),
5027	fifo_full =>fifo_out_full_signal(2),
5028	data_avalaible => data_available(2),
5029	rd_out_en => data_out_en(2)
5030	);
5031
5032	PORT3_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE
5033	PORT MAP(
5034	data_in => crossbar_out_port(3),
5035	reset => reset,
5036	clk => clk,
5037	wr_en =>crossbar_out_pulse(3),
5038	data_out =>Port_out(3),
5039	fifo_full =>fifo_out_full_signal(3),
5040	data_avalaible => data_available(3),
5041	rd_out_en => data_out_en(3)
5042	);
5043
5044	PORT4_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE
5045	PORT MAP(
5046	data_in => crossbar_out_port(4),
5047	reset => reset,
5048	clk => clk,
5049	wr_en =>crossbar_out_pulse(4),
5050	data_out =>Port_out(4),
5051	fifo_full =>fifo_out_full_signal(4),
5052	data_avalaible => data_available(4),
5053	rd_out_en => data_out_en(4)
5054	);
5055
5056	PORT5_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE
5057	PORT MAP(
5058	data_in => crossbar_out_port(5),
5059	reset => reset,
5060	clk => clk,
5061	wr_en =>crossbar_out_pulse(5),
5062	data_out =>Port_out(5),
5063	fifo_full =>fifo_out_full_signal(5),
5064	data_avalaible => data_available(5),
5065	rd_out_en => data_out_en(5)
5066	);
5067
5068	PORT6_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE
5069	PORT MAP(
5070	data_in => crossbar_out_port(6),
5071	reset => reset,
5072	clk => clk,
5073	wr_en =>crossbar_out_pulse(6),
5074	data_out =>Port_out(6),
5075	fifo_full =>fifo_out_full_signal(6),
5076	data_avalaible => data_available(6),
5077	rd_out_en => data_out_en(6)
5078	);
5079
5080	PORT7_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE
5081	PORT MAP(
5082	data_in => crossbar_out_port(7),
5083	reset => reset,
5084	clk => clk,
5085	wr_en =>crossbar_out_pulse(7),
5086	data_out =>Port_out(7),
5087	fifo_full =>fifo_out_full_signal(7),
5088	data_avalaible => data_available(7),
5089	rd_out_en => data_out_en(7)
5090	);
5091
5092	PORT8_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE
5093	PORT MAP(
5094	data_in => crossbar_out_port(8),
5095	reset => reset,
5096	clk => clk,
5097	wr_en =>crossbar_out_pulse(8),
5098	data_out =>Port_out(8),
5099	fifo_full =>fifo_out_full_signal(8),
5100	data_avalaible => data_available(8),
5101	rd_out_en => data_out_en(8)
5102	);
5103
5104	end generate port_out_switch8x8;
5105
5106
5107	-- switch 9 ports
5108	port_out_switch9x9 : if number_of_ports = 9 generate
5109
5110	PORT1_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE
5111	PORT MAP(
5112	data_in => crossbar_out_port(1),
5113	reset => reset,
5114	clk => clk,
5115	wr_en =>crossbar_out_pulse(1),
5116	data_out =>Port_out(1),
5117	fifo_full =>fifo_out_full_signal(1),
5118	data_avalaible => data_available(1),
5119	rd_out_en => data_out_en(1)
5120	);
5121
5122	PORT2_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE
5123	PORT MAP(
5124	data_in => crossbar_out_port(2),
5125	reset => reset,
5126	clk => clk,
5127	wr_en =>crossbar_out_pulse(2),
5128	data_out =>Port_out(2),
5129	fifo_full =>fifo_out_full_signal(2),
5130	data_avalaible => data_available(2),
5131	rd_out_en => data_out_en(2)
5132	);
5133
5134	PORT3_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE
5135	PORT MAP(
5136	data_in => crossbar_out_port(3),
5137	reset => reset,
5138	clk => clk,
5139	wr_en =>crossbar_out_pulse(3),
5140	data_out =>Port_out(3),
5141	fifo_full =>fifo_out_full_signal(3),
5142	data_avalaible => data_available(3),
5143	rd_out_en => data_out_en(3)
5144	);
5145
5146	PORT4_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE
5147	PORT MAP(
5148	data_in => crossbar_out_port(4),
5149	reset => reset,
5150	clk => clk,
5151	wr_en =>crossbar_out_pulse(4),
5152	data_out =>Port_out(4),
5153	fifo_full =>fifo_out_full_signal(4),
5154	data_avalaible => data_available(4),
5155	rd_out_en => data_out_en(4)
5156	);
5157
5158	PORT5_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE
5159	PORT MAP(
5160	data_in => crossbar_out_port(5),
5161	reset => reset,
5162	clk => clk,
5163	wr_en =>crossbar_out_pulse(5),
5164	data_out =>Port_out(5),
5165	fifo_full =>fifo_out_full_signal(5),
5166	data_avalaible => data_available(5),
5167	rd_out_en => data_out_en(5)
5168	);
5169
5170	PORT6_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE
5171	PORT MAP(
5172	data_in => crossbar_out_port(6),
5173	reset => reset,
5174	clk => clk,
5175	wr_en =>crossbar_out_pulse(6),
5176	data_out =>Port_out(6),
5177	fifo_full =>fifo_out_full_signal(6),
5178	data_avalaible => data_available(6),
5179	rd_out_en => data_out_en(6)
5180	);
5181
5182	PORT7_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE
5183	PORT MAP(
5184	data_in => crossbar_out_port(7),
5185	reset => reset,
5186	clk => clk,
5187	wr_en =>crossbar_out_pulse(7),
5188	data_out =>Port_out(7),
5189	fifo_full =>fifo_out_full_signal(7),
5190	data_avalaible => data_available(7),
5191	rd_out_en => data_out_en(7)
5192	);
5193
5194	PORT8_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE
5195	PORT MAP(
5196	data_in => crossbar_out_port(8),
5197	reset => reset,
5198	clk => clk,
5199	wr_en =>crossbar_out_pulse(8),
5200	data_out =>Port_out(8),
5201	fifo_full =>fifo_out_full_signal(8),
5202	data_avalaible => data_available(8),
5203	rd_out_en => data_out_en(8)
5204	);
5205
5206	PORT9_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE
5207	PORT MAP(
5208	data_in => crossbar_out_port(9),
5209	reset => reset,
5210	clk => clk,
5211	wr_en =>crossbar_out_pulse(9),
5212	data_out =>Port_out(9),
5213	fifo_full =>fifo_out_full_signal(9),
5214	data_avalaible => data_available(9),
5215	rd_out_en => data_out_en(9)
5216	);
5217
5218	end generate port_out_switch9x9;
5219
5220
5221	-- switch 10 ports
5222	port_out_switch10x10 : if number_of_ports = 10 generate
5223
5224	PORT1_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE
5225	PORT MAP(
5226	data_in => crossbar_out_port(1),
5227	reset => reset,
5228	clk => clk,
5229	wr_en =>crossbar_out_pulse(1),
5230	data_out =>Port_out(1),
5231	fifo_full =>fifo_out_full_signal(1),
5232	data_avalaible => data_available(1),
5233	rd_out_en => data_out_en(1)
5234	);
5235
5236	PORT2_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE
5237	PORT MAP(
5238	data_in => crossbar_out_port(2),
5239	reset => reset,
5240	clk => clk,
5241	wr_en =>crossbar_out_pulse(2),
5242	data_out =>Port_out(2),
5243	fifo_full =>fifo_out_full_signal(2),
5244	data_avalaible => data_available(2),
5245	rd_out_en => data_out_en(2)
5246	);
5247
5248	PORT3_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE
5249	PORT MAP(
5250	data_in => crossbar_out_port(3),
5251	reset => reset,
5252	clk => clk,
5253	wr_en =>crossbar_out_pulse(3),
5254	data_out =>Port_out(3),
5255	fifo_full =>fifo_out_full_signal(3),
5256	data_avalaible => data_available(3),
5257	rd_out_en => data_out_en(3)
5258	);
5259
5260	PORT4_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE
5261	PORT MAP(
5262	data_in => crossbar_out_port(4),
5263	reset => reset,
5264	clk => clk,
5265	wr_en =>crossbar_out_pulse(4),
5266	data_out =>Port_out(4),
5267	fifo_full =>fifo_out_full_signal(4),
5268	data_avalaible => data_available(4),
5269	rd_out_en => data_out_en(4)
5270	);
5271
5272	PORT5_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE
5273	PORT MAP(
5274	data_in => crossbar_out_port(5),
5275	reset => reset,
5276	clk => clk,
5277	wr_en =>crossbar_out_pulse(5),
5278	data_out =>Port_out(5),
5279	fifo_full =>fifo_out_full_signal(5),
5280	data_avalaible => data_available(5),
5281	rd_out_en => data_out_en(5)
5282	);
5283
5284	PORT6_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE
5285	PORT MAP(
5286	data_in => crossbar_out_port(6),
5287	reset => reset,
5288	clk => clk,
5289	wr_en =>crossbar_out_pulse(6),
5290	data_out =>Port_out(6),
5291	fifo_full =>fifo_out_full_signal(6),
5292	data_avalaible => data_available(6),
5293	rd_out_en => data_out_en(6)
5294	);
5295
5296	PORT7_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE
5297	PORT MAP(
5298	data_in => crossbar_out_port(7),
5299	reset => reset,
5300	clk => clk,
5301	wr_en =>crossbar_out_pulse(7),
5302	data_out =>Port_out(7),
5303	fifo_full =>fifo_out_full_signal(7),
5304	data_avalaible => data_available(7),
5305	rd_out_en => data_out_en(7)
5306	);
5307
5308	PORT8_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE
5309	PORT MAP(
5310	data_in => crossbar_out_port(8),
5311	reset => reset,
5312	clk => clk,
5313	wr_en =>crossbar_out_pulse(8),
5314	data_out =>Port_out(8),
5315	fifo_full =>fifo_out_full_signal(8),
5316	data_avalaible => data_available(8),
5317	rd_out_en => data_out_en(8)
5318	);
5319
5320	PORT9_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE
5321	PORT MAP(
5322	data_in => crossbar_out_port(9),
5323	reset => reset,
5324	clk => clk,
5325	wr_en =>crossbar_out_pulse(9),
5326	data_out =>Port_out(9),
5327	fifo_full =>fifo_out_full_signal(9),
5328	data_avalaible => data_available(9),
5329	rd_out_en => data_out_en(9)
5330	);
5331
5332	PORT10_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE
5333	PORT MAP(
5334	data_in => crossbar_out_port(10),
5335	reset => reset,
5336	clk => clk,
5337	wr_en =>crossbar_out_pulse(10),
5338	data_out =>Port_out(10),
5339	fifo_full =>fifo_out_full_signal(10),
5340	data_avalaible => data_available(10),
5341	rd_out_en => data_out_en(10)
5342	);
5343
5344	end generate port_out_switch10x10;
5345
5346
5347	-- switch 11 ports
5348	port_out_switch11x11 : if number_of_ports = 11 generate
5349
5350	PORT1_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE
5351	PORT MAP(
5352	data_in => crossbar_out_port(1),
5353	reset => reset,
5354	clk => clk,
5355	wr_en =>crossbar_out_pulse(1),
5356	data_out =>Port_out(1),
5357	fifo_full =>fifo_out_full_signal(1),
5358	data_avalaible => data_available(1),
5359	rd_out_en => data_out_en(1)
5360	);
5361
5362	PORT2_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE
5363	PORT MAP(
5364	data_in => crossbar_out_port(2),
5365	reset => reset,
5366	clk => clk,
5367	wr_en =>crossbar_out_pulse(2),
5368	data_out =>Port_out(2),
5369	fifo_full =>fifo_out_full_signal(2),
5370	data_avalaible => data_available(2),
5371	rd_out_en => data_out_en(2)
5372	);
5373
5374	PORT3_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE
5375	PORT MAP(
5376	data_in => crossbar_out_port(3),
5377	reset => reset,
5378	clk => clk,
5379	wr_en =>crossbar_out_pulse(3),
5380	data_out =>Port_out(3),
5381	fifo_full =>fifo_out_full_signal(3),
5382	data_avalaible => data_available(3),
5383	rd_out_en => data_out_en(3)
5384	);
5385
5386	PORT4_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE
5387	PORT MAP(
5388	data_in => crossbar_out_port(4),
5389	reset => reset,
5390	clk => clk,
5391	wr_en =>crossbar_out_pulse(4),
5392	data_out =>Port_out(4),
5393	fifo_full =>fifo_out_full_signal(4),
5394	data_avalaible => data_available(4),
5395	rd_out_en => data_out_en(4)
5396	);
5397
5398	PORT5_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE
5399	PORT MAP(
5400	data_in => crossbar_out_port(5),
5401	reset => reset,
5402	clk => clk,
5403	wr_en =>crossbar_out_pulse(5),
5404	data_out =>Port_out(5),
5405	fifo_full =>fifo_out_full_signal(5),
5406	data_avalaible => data_available(5),
5407	rd_out_en => data_out_en(5)
5408	);
5409
5410	PORT6_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE
5411	PORT MAP(
5412	data_in => crossbar_out_port(6),
5413	reset => reset,
5414	clk => clk,
5415	wr_en =>crossbar_out_pulse(6),
5416	data_out =>Port_out(6),
5417	fifo_full =>fifo_out_full_signal(6),
5418	data_avalaible => data_available(6),
5419	rd_out_en => data_out_en(6)
5420	);
5421
5422	PORT7_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE
5423	PORT MAP(
5424	data_in => crossbar_out_port(7),
5425	reset => reset,
5426	clk => clk,
5427	wr_en =>crossbar_out_pulse(7),
5428	data_out =>Port_out(7),
5429	fifo_full =>fifo_out_full_signal(7),
5430	data_avalaible => data_available(7),
5431	rd_out_en => data_out_en(7)
5432	);
5433
5434	PORT8_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE
5435	PORT MAP(
5436	data_in => crossbar_out_port(8),
5437	reset => reset,
5438	clk => clk,
5439	wr_en =>crossbar_out_pulse(8),
5440	data_out =>Port_out(8),
5441	fifo_full =>fifo_out_full_signal(8),
5442	data_avalaible => data_available(8),
5443	rd_out_en => data_out_en(8)
5444	);
5445
5446	PORT9_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE
5447	PORT MAP(
5448	data_in => crossbar_out_port(9),
5449	reset => reset,
5450	clk => clk,
5451	wr_en =>crossbar_out_pulse(9),
5452	data_out =>Port_out(9),
5453	fifo_full =>fifo_out_full_signal(9),
5454	data_avalaible => data_available(9),
5455	rd_out_en => data_out_en(9)
5456	);
5457
5458	PORT10_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE
5459	PORT MAP(
5460	data_in => crossbar_out_port(10),
5461	reset => reset,
5462	clk => clk,
5463	wr_en =>crossbar_out_pulse(10),
5464	data_out =>Port_out(10),
5465	fifo_full =>fifo_out_full_signal(10),
5466	data_avalaible => data_available(10),
5467	rd_out_en => data_out_en(10)
5468	);
5469
5470	PORT11_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE
5471	PORT MAP(
5472	data_in => crossbar_out_port(11),
5473	reset => reset,
5474	clk => clk,
5475	wr_en =>crossbar_out_pulse(11),
5476	data_out =>Port_out(11),
5477	fifo_full =>fifo_out_full_signal(11),
5478	data_avalaible => data_available(11),
5479	rd_out_en => data_out_en(11)
5480	);
5481
5482	end generate port_out_switch11x11;
5483
5484
5485	-- switch 12 ports
5486	port_out_switch12x12 : if number_of_ports = 12 generate
5487
5488	PORT1_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE
5489	PORT MAP(
5490	data_in => crossbar_out_port(1),
5491	reset => reset,
5492	clk => clk,
5493	wr_en =>crossbar_out_pulse(1),
5494	data_out =>Port_out(1),
5495	fifo_full =>fifo_out_full_signal(1),
5496	data_avalaible => data_available(1),
5497	rd_out_en => data_out_en(1)
5498	);
5499
5500	PORT2_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE
5501	PORT MAP(
5502	data_in => crossbar_out_port(2),
5503	reset => reset,
5504	clk => clk,
5505	wr_en =>crossbar_out_pulse(2),
5506	data_out =>Port_out(2),
5507	fifo_full =>fifo_out_full_signal(2),
5508	data_avalaible => data_available(2),
5509	rd_out_en => data_out_en(2)
5510	);
5511
5512	PORT3_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE
5513	PORT MAP(
5514	data_in => crossbar_out_port(3),
5515	reset => reset,
5516	clk => clk,
5517	wr_en =>crossbar_out_pulse(3),
5518	data_out =>Port_out(3),
5519	fifo_full =>fifo_out_full_signal(3),
5520	data_avalaible => data_available(3),
5521	rd_out_en => data_out_en(3)
5522	);
5523
5524	PORT4_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE
5525	PORT MAP(
5526	data_in => crossbar_out_port(4),
5527	reset => reset,
5528	clk => clk,
5529	wr_en =>crossbar_out_pulse(4),
5530	data_out =>Port_out(4),
5531	fifo_full =>fifo_out_full_signal(4),
5532	data_avalaible => data_available(4),
5533	rd_out_en => data_out_en(4)
5534	);
5535
5536	PORT5_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE
5537	PORT MAP(
5538	data_in => crossbar_out_port(5),
5539	reset => reset,
5540	clk => clk,
5541	wr_en =>crossbar_out_pulse(5),
5542	data_out =>Port_out(5),
5543	fifo_full =>fifo_out_full_signal(5),
5544	data_avalaible => data_available(5),
5545	rd_out_en => data_out_en(5)
5546	);
5547
5548	PORT6_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE
5549	PORT MAP(
5550	data_in => crossbar_out_port(6),
5551	reset => reset,
5552	clk => clk,
5553	wr_en =>crossbar_out_pulse(6),
5554	data_out =>Port_out(6),
5555	fifo_full =>fifo_out_full_signal(6),
5556	data_avalaible => data_available(6),
5557	rd_out_en => data_out_en(6)
5558	);
5559
5560	PORT7_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE
5561	PORT MAP(
5562	data_in => crossbar_out_port(7),
5563	reset => reset,
5564	clk => clk,
5565	wr_en =>crossbar_out_pulse(7),
5566	data_out =>Port_out(7),
5567	fifo_full =>fifo_out_full_signal(7),
5568	data_avalaible => data_available(7),
5569	rd_out_en => data_out_en(7)
5570	);
5571
5572	PORT8_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE
5573	PORT MAP(
5574	data_in => crossbar_out_port(8),
5575	reset => reset,
5576	clk => clk,
5577	wr_en =>crossbar_out_pulse(8),
5578	data_out =>Port_out(8),
5579	fifo_full =>fifo_out_full_signal(8),
5580	data_avalaible => data_available(8),
5581	rd_out_en => data_out_en(8)
5582	);
5583
5584	PORT9_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE
5585	PORT MAP(
5586	data_in => crossbar_out_port(9),
5587	reset => reset,
5588	clk => clk,
5589	wr_en =>crossbar_out_pulse(9),
5590	data_out =>Port_out(9),
5591	fifo_full =>fifo_out_full_signal(9),
5592	data_avalaible => data_available(9),
5593	rd_out_en => data_out_en(9)
5594	);
5595
5596	PORT10_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE
5597	PORT MAP(
5598	data_in => crossbar_out_port(10),
5599	reset => reset,
5600	clk => clk,
5601	wr_en =>crossbar_out_pulse(10),
5602	data_out =>Port_out(10),
5603	fifo_full =>fifo_out_full_signal(10),
5604	data_avalaible => data_available(10),
5605	rd_out_en => data_out_en(10)
5606	);
5607
5608	PORT11_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE
5609	PORT MAP(
5610	data_in => crossbar_out_port(11),
5611	reset => reset,
5612	clk => clk,
5613	wr_en =>crossbar_out_pulse(11),
5614	data_out =>Port_out(11),
5615	fifo_full =>fifo_out_full_signal(11),
5616	data_avalaible => data_available(11),
5617	rd_out_en => data_out_en(11)
5618	);
5619
5620	PORT12_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE
5621	PORT MAP(
5622	data_in => crossbar_out_port(12),
5623	reset => reset,
5624	clk => clk,
5625	wr_en =>crossbar_out_pulse(12),
5626	data_out =>Port_out(12),
5627	fifo_full =>fifo_out_full_signal(12),
5628	data_avalaible => data_available(12),
5629	rd_out_en => data_out_en(12)
5630	);
5631
5632	end generate port_out_switch12x12;
5633
5634
5635	-- switch 13 ports
5636	port_out_switch13x13 : if number_of_ports = 13 generate
5637
5638	PORT1_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE
5639	PORT MAP(
5640	data_in => crossbar_out_port(1),
5641	reset => reset,
5642	clk => clk,
5643	wr_en =>crossbar_out_pulse(1),
5644	data_out =>Port_out(1),
5645	fifo_full =>fifo_out_full_signal(1),
5646	data_avalaible => data_available(1),
5647	rd_out_en => data_out_en(1)
5648	);
5649
5650	PORT2_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE
5651	PORT MAP(
5652	data_in => crossbar_out_port(2),
5653	reset => reset,
5654	clk => clk,
5655	wr_en =>crossbar_out_pulse(2),
5656	data_out =>Port_out(2),
5657	fifo_full =>fifo_out_full_signal(2),
5658	data_avalaible => data_available(2),
5659	rd_out_en => data_out_en(2)
5660	);
5661
5662	PORT3_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE
5663	PORT MAP(
5664	data_in => crossbar_out_port(3),
5665	reset => reset,
5666	clk => clk,
5667	wr_en =>crossbar_out_pulse(3),
5668	data_out =>Port_out(3),
5669	fifo_full =>fifo_out_full_signal(3),
5670	data_avalaible => data_available(3),
5671	rd_out_en => data_out_en(3)
5672	);
5673
5674	PORT4_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE
5675	PORT MAP(
5676	data_in => crossbar_out_port(4),
5677	reset => reset,
5678	clk => clk,
5679	wr_en =>crossbar_out_pulse(4),
5680	data_out =>Port_out(4),
5681	fifo_full =>fifo_out_full_signal(4),
5682	data_avalaible => data_available(4),
5683	rd_out_en => data_out_en(4)
5684	);
5685
5686	PORT5_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE
5687	PORT MAP(
5688	data_in => crossbar_out_port(5),
5689	reset => reset,
5690	clk => clk,
5691	wr_en =>crossbar_out_pulse(5),
5692	data_out =>Port_out(5),
5693	fifo_full =>fifo_out_full_signal(5),
5694	data_avalaible => data_available(5),
5695	rd_out_en => data_out_en(5)
5696	);
5697
5698	PORT6_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE
5699	PORT MAP(
5700	data_in => crossbar_out_port(6),
5701	reset => reset,
5702	clk => clk,
5703	wr_en =>crossbar_out_pulse(6),
5704	data_out =>Port_out(6),
5705	fifo_full =>fifo_out_full_signal(6),
5706	data_avalaible => data_available(6),
5707	rd_out_en => data_out_en(6)
5708	);
5709
5710	PORT7_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE
5711	PORT MAP(
5712	data_in => crossbar_out_port(7),
5713	reset => reset,
5714	clk => clk,
5715	wr_en =>crossbar_out_pulse(7),
5716	data_out =>Port_out(7),
5717	fifo_full =>fifo_out_full_signal(7),
5718	data_avalaible => data_available(7),
5719	rd_out_en => data_out_en(7)
5720	);
5721
5722	PORT8_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE
5723	PORT MAP(
5724	data_in => crossbar_out_port(8),
5725	reset => reset,
5726	clk => clk,
5727	wr_en =>crossbar_out_pulse(8),
5728	data_out =>Port_out(8),
5729	fifo_full =>fifo_out_full_signal(8),
5730	data_avalaible => data_available(8),
5731	rd_out_en => data_out_en(8)
5732	);
5733
5734	PORT9_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE
5735	PORT MAP(
5736	data_in => crossbar_out_port(9),
5737	reset => reset,
5738	clk => clk,
5739	wr_en =>crossbar_out_pulse(9),
5740	data_out =>Port_out(9),
5741	fifo_full =>fifo_out_full_signal(9),
5742	data_avalaible => data_available(9),
5743	rd_out_en => data_out_en(9)
5744	);
5745
5746	PORT10_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE
5747	PORT MAP(
5748	data_in => crossbar_out_port(10),
5749	reset => reset,
5750	clk => clk,
5751	wr_en =>crossbar_out_pulse(10),
5752	data_out =>Port_out(10),
5753	fifo_full =>fifo_out_full_signal(10),
5754	data_avalaible => data_available(10),
5755	rd_out_en => data_out_en(10)
5756	);
5757
5758	PORT11_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE
5759	PORT MAP(
5760	data_in => crossbar_out_port(11),
5761	reset => reset,
5762	clk => clk,
5763	wr_en =>crossbar_out_pulse(11),
5764	data_out =>Port_out(11),
5765	fifo_full =>fifo_out_full_signal(11),
5766	data_avalaible => data_available(11),
5767	rd_out_en => data_out_en(11)
5768	);
5769
5770	PORT12_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE
5771	PORT MAP(
5772	data_in => crossbar_out_port(12),
5773	reset => reset,
5774	clk => clk,
5775	wr_en =>crossbar_out_pulse(12),
5776	data_out =>Port_out(12),
5777	fifo_full =>fifo_out_full_signal(12),
5778	data_avalaible => data_available(12),
5779	rd_out_en => data_out_en(12)
5780	);
5781
5782	PORT13_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE
5783	PORT MAP(
5784	data_in => crossbar_out_port(13),
5785	reset => reset,
5786	clk => clk,
5787	wr_en =>crossbar_out_pulse(13),
5788	data_out =>Port_out(13),
5789	fifo_full =>fifo_out_full_signal(13),
5790	data_avalaible => data_available(13),
5791	rd_out_en => data_out_en(13)
5792	);
5793
5794	end generate port_out_switch13x13;
5795
5796
5797	-- switch 14 ports
5798	port_out_switch14x14 : if number_of_ports = 14 generate
5799
5800	PORT1_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE
5801	PORT MAP(
5802	data_in => crossbar_out_port(1),
5803	reset => reset,
5804	clk => clk,
5805	wr_en =>crossbar_out_pulse(1),
5806	data_out =>Port_out(1),
5807	fifo_full =>fifo_out_full_signal(1),
5808	data_avalaible => data_available(1),
5809	rd_out_en => data_out_en(1)
5810	);
5811
5812	PORT2_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE
5813	PORT MAP(
5814	data_in => crossbar_out_port(2),
5815	reset => reset,
5816	clk => clk,
5817	wr_en =>crossbar_out_pulse(2),
5818	data_out =>Port_out(2),
5819	fifo_full =>fifo_out_full_signal(2),
5820	data_avalaible => data_available(2),
5821	rd_out_en => data_out_en(2)
5822	);
5823
5824	PORT3_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE
5825	PORT MAP(
5826	data_in => crossbar_out_port(3),
5827	reset => reset,
5828	clk => clk,
5829	wr_en =>crossbar_out_pulse(3),
5830	data_out =>Port_out(3),
5831	fifo_full =>fifo_out_full_signal(3),
5832	data_avalaible => data_available(3),
5833	rd_out_en => data_out_en(3)
5834	);
5835
5836	PORT4_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE
5837	PORT MAP(
5838	data_in => crossbar_out_port(4),
5839	reset => reset,
5840	clk => clk,
5841	wr_en =>crossbar_out_pulse(4),
5842	data_out =>Port_out(4),
5843	fifo_full =>fifo_out_full_signal(4),
5844	data_avalaible => data_available(4),
5845	rd_out_en => data_out_en(4)
5846	);
5847
5848	PORT5_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE
5849	PORT MAP(
5850	data_in => crossbar_out_port(5),
5851	reset => reset,
5852	clk => clk,
5853	wr_en =>crossbar_out_pulse(5),
5854	data_out =>Port_out(5),
5855	fifo_full =>fifo_out_full_signal(5),
5856	data_avalaible => data_available(5),
5857	rd_out_en => data_out_en(5)
5858	);
5859
5860	PORT6_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE
5861	PORT MAP(
5862	data_in => crossbar_out_port(6),
5863	reset => reset,
5864	clk => clk,
5865	wr_en =>crossbar_out_pulse(6),
5866	data_out =>Port_out(6),
5867	fifo_full =>fifo_out_full_signal(6),
5868	data_avalaible => data_available(6),
5869	rd_out_en => data_out_en(6)
5870	);
5871
5872	PORT7_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE
5873	PORT MAP(
5874	data_in => crossbar_out_port(7),
5875	reset => reset,
5876	clk => clk,
5877	wr_en =>crossbar_out_pulse(7),
5878	data_out =>Port_out(7),
5879	fifo_full =>fifo_out_full_signal(7),
5880	data_avalaible => data_available(7),
5881	rd_out_en => data_out_en(7)
5882	);
5883
5884	PORT8_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE
5885	PORT MAP(
5886	data_in => crossbar_out_port(8),
5887	reset => reset,
5888	clk => clk,
5889	wr_en =>crossbar_out_pulse(8),
5890	data_out =>Port_out(8),
5891	fifo_full =>fifo_out_full_signal(8),
5892	data_avalaible => data_available(8),
5893	rd_out_en => data_out_en(8)
5894	);
5895
5896	PORT9_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE
5897	PORT MAP(
5898	data_in => crossbar_out_port(9),
5899	reset => reset,
5900	clk => clk,
5901	wr_en =>crossbar_out_pulse(9),
5902	data_out =>Port_out(9),
5903	fifo_full =>fifo_out_full_signal(9),
5904	data_avalaible => data_available(9),
5905	rd_out_en => data_out_en(9)
5906	);
5907
5908	PORT10_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE
5909	PORT MAP(
5910	data_in => crossbar_out_port(10),
5911	reset => reset,
5912	clk => clk,
5913	wr_en =>crossbar_out_pulse(10),
5914	data_out =>Port_out(10),
5915	fifo_full =>fifo_out_full_signal(10),
5916	data_avalaible => data_available(10),
5917	rd_out_en => data_out_en(10)
5918	);
5919
5920	PORT11_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE
5921	PORT MAP(
5922	data_in => crossbar_out_port(11),
5923	reset => reset,
5924	clk => clk,
5925	wr_en =>crossbar_out_pulse(11),
5926	data_out =>Port_out(11),
5927	fifo_full =>fifo_out_full_signal(11),
5928	data_avalaible => data_available(11),
5929	rd_out_en => data_out_en(11)
5930	);
5931
5932	PORT12_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE
5933	PORT MAP(
5934	data_in => crossbar_out_port(12),
5935	reset => reset,
5936	clk => clk,
5937	wr_en =>crossbar_out_pulse(12),
5938	data_out =>Port_out(12),
5939	fifo_full =>fifo_out_full_signal(12),
5940	data_avalaible => data_available(12),
5941	rd_out_en => data_out_en(12)
5942	);
5943
5944	PORT13_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE
5945	PORT MAP(
5946	data_in => crossbar_out_port(13),
5947	reset => reset,
5948	clk => clk,
5949	wr_en =>crossbar_out_pulse(13),
5950	data_out =>Port_out(13),
5951	fifo_full =>fifo_out_full_signal(13),
5952	data_avalaible => data_available(13),
5953	rd_out_en => data_out_en(13)
5954	);
5955
5956	PORT14_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE
5957	PORT MAP(
5958	data_in => crossbar_out_port(14),
5959	reset => reset,
5960	clk => clk,
5961	wr_en =>crossbar_out_pulse(14),
5962	data_out =>Port_out(14),
5963	fifo_full =>fifo_out_full_signal(14),
5964	data_avalaible => data_available(14),
5965	rd_out_en => data_out_en(14)
5966	);
5967
5968	end generate port_out_switch14x14;
5969
5970
5971	-- switch 15 ports
5972	port_out_switch15x15 : if number_of_ports = 15 generate
5973
5974	PORT1_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE
5975	PORT MAP(
5976	data_in => crossbar_out_port(1),
5977	reset => reset,
5978	clk => clk,
5979	wr_en =>crossbar_out_pulse(1),
5980	data_out =>Port_out(1),
5981	fifo_full =>fifo_out_full_signal(1),
5982	data_avalaible => data_available(1),
5983	rd_out_en => data_out_en(1)
5984	);
5985
5986	PORT2_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE
5987	PORT MAP(
5988	data_in => crossbar_out_port(2),
5989	reset => reset,
5990	clk => clk,
5991	wr_en =>crossbar_out_pulse(2),
5992	data_out =>Port_out(2),
5993	fifo_full =>fifo_out_full_signal(2),
5994	data_avalaible => data_available(2),
5995	rd_out_en => data_out_en(2)
5996	);
5997
5998	PORT3_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE
5999	PORT MAP(
6000	data_in => crossbar_out_port(3),
6001	reset => reset,
6002	clk => clk,
6003	wr_en =>crossbar_out_pulse(3),
6004	data_out =>Port_out(3),
6005	fifo_full =>fifo_out_full_signal(3),
6006	data_avalaible => data_available(3),
6007	rd_out_en => data_out_en(3)
6008	);
6009
6010	PORT4_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE
6011	PORT MAP(
6012	data_in => crossbar_out_port(4),
6013	reset => reset,
6014	clk => clk,
6015	wr_en =>crossbar_out_pulse(4),
6016	data_out =>Port_out(4),
6017	fifo_full =>fifo_out_full_signal(4),
6018	data_avalaible => data_available(4),
6019	rd_out_en => data_out_en(4)
6020	);
6021
6022	PORT5_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE
6023	PORT MAP(
6024	data_in => crossbar_out_port(5),
6025	reset => reset,
6026	clk => clk,
6027	wr_en =>crossbar_out_pulse(5),
6028	data_out =>Port_out(5),
6029	fifo_full =>fifo_out_full_signal(5),
6030	data_avalaible => data_available(5),
6031	rd_out_en => data_out_en(5)
6032	);
6033
6034	PORT6_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE
6035	PORT MAP(
6036	data_in => crossbar_out_port(6),
6037	reset => reset,
6038	clk => clk,
6039	wr_en =>crossbar_out_pulse(6),
6040	data_out =>Port_out(6),
6041	fifo_full =>fifo_out_full_signal(6),
6042	data_avalaible => data_available(6),
6043	rd_out_en => data_out_en(6)
6044	);
6045
6046	PORT7_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE
6047	PORT MAP(
6048	data_in => crossbar_out_port(7),
6049	reset => reset,
6050	clk => clk,
6051	wr_en =>crossbar_out_pulse(7),
6052	data_out =>Port_out(7),
6053	fifo_full =>fifo_out_full_signal(7),
6054	data_avalaible => data_available(7),
6055	rd_out_en => data_out_en(7)
6056	);
6057
6058	PORT8_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE
6059	PORT MAP(
6060	data_in => crossbar_out_port(8),
6061	reset => reset,
6062	clk => clk,
6063	wr_en =>crossbar_out_pulse(8),
6064	data_out =>Port_out(8),
6065	fifo_full =>fifo_out_full_signal(8),
6066	data_avalaible => data_available(8),
6067	rd_out_en => data_out_en(8)
6068	);
6069
6070	PORT9_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE
6071	PORT MAP(
6072	data_in => crossbar_out_port(9),
6073	reset => reset,
6074	clk => clk,
6075	wr_en =>crossbar_out_pulse(9),
6076	data_out =>Port_out(9),
6077	fifo_full =>fifo_out_full_signal(9),
6078	data_avalaible => data_available(9),
6079	rd_out_en => data_out_en(9)
6080	);
6081
6082	PORT10_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE
6083	PORT MAP(
6084	data_in => crossbar_out_port(10),
6085	reset => reset,
6086	clk => clk,
6087	wr_en =>crossbar_out_pulse(10),
6088	data_out =>Port_out(10),
6089	fifo_full =>fifo_out_full_signal(10),
6090	data_avalaible => data_available(10),
6091	rd_out_en => data_out_en(10)
6092	);
6093
6094	PORT11_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE
6095	PORT MAP(
6096	data_in => crossbar_out_port(11),
6097	reset => reset,
6098	clk => clk,
6099	wr_en =>crossbar_out_pulse(11),
6100	data_out =>Port_out(11),
6101	fifo_full =>fifo_out_full_signal(11),
6102	data_avalaible => data_available(11),
6103	rd_out_en => data_out_en(11)
6104	);
6105
6106	PORT12_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE
6107	PORT MAP(
6108	data_in => crossbar_out_port(12),
6109	reset => reset,
6110	clk => clk,
6111	wr_en =>crossbar_out_pulse(12),
6112	data_out =>Port_out(12),
6113	fifo_full =>fifo_out_full_signal(12),
6114	data_avalaible => data_available(12),
6115	rd_out_en => data_out_en(12)
6116	);
6117
6118	PORT13_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE
6119	PORT MAP(
6120	data_in => crossbar_out_port(13),
6121	reset => reset,
6122	clk => clk,
6123	wr_en =>crossbar_out_pulse(13),
6124	data_out =>Port_out(13),
6125	fifo_full =>fifo_out_full_signal(13),
6126	data_avalaible => data_available(13),
6127	rd_out_en => data_out_en(13)
6128	);
6129
6130	PORT14_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE
6131	PORT MAP(
6132	data_in => crossbar_out_port(14),
6133	reset => reset,
6134	clk => clk,
6135	wr_en =>crossbar_out_pulse(14),
6136	data_out =>Port_out(14),
6137	fifo_full =>fifo_out_full_signal(14),
6138	data_avalaible => data_available(14),
6139	rd_out_en => data_out_en(14)
6140	);
6141
6142	PORT15_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE
6143	PORT MAP(
6144	data_in => crossbar_out_port(15),
6145	reset => reset,
6146	clk => clk,
6147	wr_en =>crossbar_out_pulse(15),
6148	data_out =>Port_out(15),
6149	fifo_full =>fifo_out_full_signal(15),
6150	data_avalaible => data_available(15),
6151	rd_out_en => data_out_en(15)
6152	);
6153
6154	end generate port_out_switch15x15;
6155
6156
6157	-- switch 16 ports
6158	port_out_switch16x16 : if number_of_ports = 16 generate
6159	port_out_switch_16x16:for i in 1 to number_of_ports generate
6160	begin
6161	PORTx16_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE
6162	PORT MAP(
6163	data_in => crossbar_out_port(i),
6164	reset => reset,
6165	clk => clk,
6166	wr_en =>crossbar_out_pulse(i),
6167	data_out =>Port_out(i),
6168	fifo_full =>fifo_out_full_signal(i),
6169	data_avalaible => data_available(i),
6170	rd_out_en => data_out_en(i)
6171	);
6172	end generate port_out_switch_16x16;
6173
6174	end generate port_out_switch16x16;
6175
6176	-- intstanciation et connexion des crossbars du switch en fonction du nombre de ports
6177	-- le circuit genere depend du parametre generique nombre de ports
6178	-- switch 2 ports
6179	crossbar_switch2x2 : if number_of_ports = 2 generate
6180
6181	Switch_Crossbar2_2: Crossbar
6182	GENERIC MAP(number_of_crossbar_ports =>2)
6183	PORT MAP(
6184	reset => reset,
6185	clk => clk,
6186	Port1_in => crossbar_in_port(1),
6187	Port2_in => crossbar_in_port(2),
6188	Port3_in => "00000000",
6189	Port4_in => "00000000",
6190	Port5_in => "00000000",
6191	Port6_in => "00000000",
6192	Port7_in => "00000000",
6193	Port8_in => "00000000",
6194	Port9_in => "00000000",
6195	Port10_in => "00000000",
6196	Port11_in => "00000000",
6197	Port12_in => "00000000",
6198	Port13_in => "00000000",
6199	Port14_in => "00000000",
6200	Port15_in => "00000000",
6201	Port16_in => "00000000",
6202	Port1_pulse_in => crossbar_in_pulse(1),
6203	Port2_pulse_in => crossbar_in_pulse(2),
6204	Port3_pulse_in =>'0' ,
6205	Port4_pulse_in =>'0' ,
6206	Port5_pulse_in =>'0' ,
6207	Port6_pulse_in =>'0' ,
6208	Port7_pulse_in =>'0' ,
6209	Port8_pulse_in =>'0' ,
6210	Port9_pulse_in =>'0' ,
6211	Port10_pulse_in =>'0' ,
6212	Port11_pulse_in =>'0' ,
6213	Port12_pulse_in =>'0' ,
6214	Port13_pulse_in =>'0' ,
6215	Port14_pulse_in =>'0' ,
6216	Port15_pulse_in =>'0' ,
6217	Port16_pulse_in =>'0' ,
6218	Port1_pulse_out => crossbar_out_pulse(1),
6219	Port2_pulse_out => crossbar_out_pulse(2),
6220	Port1_out => crossbar_out_port(1),
6221	Port2_out => crossbar_out_port(2),
6222	Ctrl => Grant_signal);
6223	end generate crossbar_switch2x2;
6224
6225
6226	-- switch 3 ports
6227	crossbar_switch3x3 : if number_of_ports = 3 generate
6228
6229	Switch_Crossbar3_3: Crossbar
6230	GENERIC MAP(number_of_crossbar_ports =>3)
6231	PORT MAP(
6232	reset => reset,
6233	clk => clk,
6234	Port1_in => crossbar_in_port(1),
6235	Port2_in => crossbar_in_port(2),
6236	Port3_in => crossbar_in_port(3),
6237	Port4_in => "00000000",
6238	Port5_in => "00000000",
6239	Port6_in => "00000000",
6240	Port7_in => "00000000",
6241	Port8_in => "00000000",
6242	Port9_in => "00000000",
6243	Port10_in => "00000000",
6244	Port11_in => "00000000",
6245	Port12_in => "00000000",
6246	Port13_in => "00000000",
6247	Port14_in => "00000000",
6248	Port15_in => "00000000",
6249	Port16_in => "00000000",
6250	Port1_pulse_in => crossbar_in_pulse(1),
6251	Port2_pulse_in => crossbar_in_pulse(2),
6252	Port3_pulse_in => crossbar_in_pulse(3),
6253	Port4_pulse_in =>'0' ,
6254	Port5_pulse_in =>'0' ,
6255	Port6_pulse_in =>'0' ,
6256	Port7_pulse_in =>'0' ,
6257	Port8_pulse_in =>'0' ,
6258	Port9_pulse_in =>'0' ,
6259	Port10_pulse_in =>'0' ,
6260	Port11_pulse_in =>'0' ,
6261	Port12_pulse_in =>'0' ,
6262	Port13_pulse_in =>'0' ,
6263	Port14_pulse_in =>'0' ,
6264	Port15_pulse_in =>'0' ,
6265	Port16_pulse_in =>'0' ,
6266	Port1_pulse_out => crossbar_out_pulse(1),
6267	Port2_pulse_out => crossbar_out_pulse(2),
6268	Port3_pulse_out => crossbar_out_pulse(3),
6269	Port1_out => crossbar_out_port(1),
6270	Port2_out => crossbar_out_port(2),
6271	Port3_out => crossbar_out_port(3),
6272	Ctrl => Grant_signal);
6273	end generate crossbar_switch3x3;
6274
6275
6276	-- switch 4 ports
6277	crossbar_switch4x4 : if number_of_ports = 4 generate
6278
6279	Switch_Crossbar4_4: Crossbar
6280	GENERIC MAP(number_of_crossbar_ports =>4)
6281	PORT MAP(
6282	reset => reset,
6283	clk => clk,
6284	Port1_in => crossbar_in_port(1),
6285	Port2_in => crossbar_in_port(2),
6286	Port3_in => crossbar_in_port(3),
6287	Port4_in => crossbar_in_port(4),
6288	Port5_in => "00000000",
6289	Port6_in => "00000000",
6290	Port7_in => "00000000",
6291	Port8_in => "00000000",
6292	Port9_in => "00000000",
6293	Port10_in => "00000000",
6294	Port11_in => "00000000",
6295	Port12_in => "00000000",
6296	Port13_in => "00000000",
6297	Port14_in => "00000000",
6298	Port15_in => "00000000",
6299	Port16_in => "00000000",
6300	Port1_pulse_in => crossbar_in_pulse(1),
6301	Port2_pulse_in => crossbar_in_pulse(2),
6302	Port3_pulse_in => crossbar_in_pulse(3),
6303	Port4_pulse_in => crossbar_in_pulse(4),
6304	Port5_pulse_in =>'0' ,
6305	Port6_pulse_in =>'0' ,
6306	Port7_pulse_in =>'0' ,
6307	Port8_pulse_in =>'0' ,
6308	Port9_pulse_in =>'0' ,
6309	Port10_pulse_in =>'0' ,
6310	Port11_pulse_in =>'0' ,
6311	Port12_pulse_in =>'0' ,
6312	Port13_pulse_in =>'0' ,
6313	Port14_pulse_in =>'0' ,
6314	Port15_pulse_in =>'0' ,
6315	Port16_pulse_in =>'0' ,
6316	Port1_pulse_out => crossbar_out_pulse(1),
6317	Port2_pulse_out => crossbar_out_pulse(2),
6318	Port3_pulse_out => crossbar_out_pulse(3),
6319	Port4_pulse_out => crossbar_out_pulse(4),
6320	Port1_out => crossbar_out_port(1),
6321	Port2_out => crossbar_out_port(2),
6322	Port3_out => crossbar_out_port(3),
6323	Port4_out => crossbar_out_port(4),
6324	Ctrl => Grant_signal);
6325	end generate crossbar_switch4x4;
6326
6327
6328	-- switch 5 ports
6329	crossbar_switch5x5 : if number_of_ports = 5 generate
6330
6331	Switch_Crossbar5_5: Crossbar
6332	GENERIC MAP(number_of_crossbar_ports =>5)
6333	PORT MAP(
6334	reset => reset,
6335	clk => clk,
6336	Port1_in => crossbar_in_port(1),
6337	Port2_in => crossbar_in_port(2),
6338	Port3_in => crossbar_in_port(3),
6339	Port4_in => crossbar_in_port(4),
6340	Port5_in => crossbar_in_port(5),
6341	Port6_in => "00000000",
6342	Port7_in => "00000000",
6343	Port8_in => "00000000",
6344	Port9_in => "00000000",
6345	Port10_in => "00000000",
6346	Port11_in => "00000000",
6347	Port12_in => "00000000",
6348	Port13_in => "00000000",
6349	Port14_in => "00000000",
6350	Port15_in => "00000000",
6351	Port16_in => "00000000",
6352	Port1_pulse_in => crossbar_in_pulse(1),
6353	Port2_pulse_in => crossbar_in_pulse(2),
6354	Port3_pulse_in => crossbar_in_pulse(3),
6355	Port4_pulse_in => crossbar_in_pulse(4),
6356	Port5_pulse_in => crossbar_in_pulse(5),
6357	Port6_pulse_in =>'0' ,
6358	Port7_pulse_in =>'0' ,
6359	Port8_pulse_in =>'0' ,
6360	Port9_pulse_in =>'0' ,
6361	Port10_pulse_in =>'0' ,
6362	Port11_pulse_in =>'0' ,
6363	Port12_pulse_in =>'0' ,
6364	Port13_pulse_in =>'0' ,
6365	Port14_pulse_in =>'0' ,
6366	Port15_pulse_in =>'0' ,
6367	Port16_pulse_in =>'0' ,
6368	Port1_pulse_out => crossbar_out_pulse(1),
6369	Port2_pulse_out => crossbar_out_pulse(2),
6370	Port3_pulse_out => crossbar_out_pulse(3),
6371	Port4_pulse_out => crossbar_out_pulse(4),
6372	Port5_pulse_out => crossbar_out_pulse(5),
6373	Port1_out => crossbar_out_port(1),
6374	Port2_out => crossbar_out_port(2),
6375	Port3_out => crossbar_out_port(3),
6376	Port4_out => crossbar_out_port(4),
6377	Port5_out => crossbar_out_port(5),
6378	Ctrl => Grant_signal);
6379	end generate crossbar_switch5x5;
6380
6381
6382	-- switch 6 ports
6383	crossbar_switch6x6 : if number_of_ports = 6 generate
6384
6385	Switch_Crossbar6_6: Crossbar
6386	GENERIC MAP(number_of_crossbar_ports =>6)
6387	PORT MAP(
6388
6389	reset => reset,
6390	clk => clk,
6391	Port1_in => crossbar_in_port(1),
6392	Port2_in => crossbar_in_port(2),
6393	Port3_in => crossbar_in_port(3),
6394	Port4_in => crossbar_in_port(4),
6395	Port5_in => crossbar_in_port(5),
6396	Port6_in => crossbar_in_port(6),
6397	Port7_in => "00000000",
6398	Port8_in => "00000000",
6399	Port9_in => "00000000",
6400	Port10_in => "00000000",
6401	Port11_in => "00000000",
6402	Port12_in => "00000000",
6403	Port13_in => "00000000",
6404	Port14_in => "00000000",
6405	Port15_in => "00000000",
6406	Port16_in => "00000000",
6407	Port1_pulse_in => crossbar_in_pulse(1),
6408	Port2_pulse_in => crossbar_in_pulse(2),
6409	Port3_pulse_in => crossbar_in_pulse(3),
6410	Port4_pulse_in => crossbar_in_pulse(4),
6411	Port5_pulse_in => crossbar_in_pulse(5),
6412	Port6_pulse_in => crossbar_in_pulse(6),
6413	Port7_pulse_in =>'0' ,
6414	Port8_pulse_in =>'0' ,
6415	Port9_pulse_in =>'0' ,
6416	Port10_pulse_in =>'0' ,
6417	Port11_pulse_in =>'0' ,
6418	Port12_pulse_in =>'0' ,
6419	Port13_pulse_in =>'0' ,
6420	Port14_pulse_in =>'0' ,
6421	Port15_pulse_in =>'0' ,
6422	Port16_pulse_in =>'0' ,
6423	Port1_pulse_out => crossbar_out_pulse(1),
6424	Port2_pulse_out => crossbar_out_pulse(2),
6425	Port3_pulse_out => crossbar_out_pulse(3),
6426	Port4_pulse_out => crossbar_out_pulse(4),
6427	Port5_pulse_out => crossbar_out_pulse(5),
6428	Port6_pulse_out => crossbar_out_pulse(6),
6429	Port1_out => crossbar_out_port(1),
6430	Port2_out => crossbar_out_port(2),
6431	Port3_out => crossbar_out_port(3),
6432	Port4_out => crossbar_out_port(4),
6433	Port5_out => crossbar_out_port(5),
6434	Port6_out => crossbar_out_port(6),
6435	Ctrl => Grant_signal);
6436	end generate crossbar_switch6x6;
6437
6438
6439	-- switch 7 ports
6440	crossbar_switch7x7 : if number_of_ports = 7 generate
6441
6442	Switch_Crossbar7_7: Crossbar
6443	GENERIC MAP(number_of_crossbar_ports =>7)
6444	PORT MAP(
6445	reset => reset,
6446	clk => clk,
6447	Port1_in => crossbar_in_port(1),
6448	Port2_in => crossbar_in_port(2),
6449	Port3_in => crossbar_in_port(3),
6450	Port4_in => crossbar_in_port(4),
6451	Port5_in => crossbar_in_port(5),
6452	Port6_in => crossbar_in_port(6),
6453	Port7_in => crossbar_in_port(7),
6454	Port8_in => "00000000",
6455	Port9_in => "00000000",
6456	Port10_in => "00000000",
6457	Port11_in => "00000000",
6458	Port12_in => "00000000",
6459	Port13_in => "00000000",
6460	Port14_in => "00000000",
6461	Port15_in => "00000000",
6462	Port16_in => "00000000",
6463	Port1_pulse_in => crossbar_in_pulse(1),
6464	Port2_pulse_in => crossbar_in_pulse(2),
6465	Port3_pulse_in => crossbar_in_pulse(3),
6466	Port4_pulse_in => crossbar_in_pulse(4),
6467	Port5_pulse_in => crossbar_in_pulse(5),
6468	Port6_pulse_in => crossbar_in_pulse(6),
6469	Port7_pulse_in => crossbar_in_pulse(7),
6470	Port8_pulse_in =>'0' ,
6471	Port9_pulse_in =>'0' ,
6472	Port10_pulse_in =>'0' ,
6473	Port11_pulse_in =>'0' ,
6474	Port12_pulse_in =>'0' ,
6475	Port13_pulse_in =>'0' ,
6476	Port14_pulse_in =>'0' ,
6477	Port15_pulse_in =>'0' ,
6478	Port16_pulse_in =>'0' ,
6479	Port1_pulse_out => crossbar_out_pulse(1),
6480	Port2_pulse_out => crossbar_out_pulse(2),
6481	Port3_pulse_out => crossbar_out_pulse(3),
6482	Port4_pulse_out => crossbar_out_pulse(4),
6483	Port5_pulse_out => crossbar_out_pulse(5),
6484	Port6_pulse_out => crossbar_out_pulse(6),
6485	Port7_pulse_out => crossbar_out_pulse(7),
6486	Port1_out => crossbar_out_port(1),
6487	Port2_out => crossbar_out_port(2),
6488	Port3_out => crossbar_out_port(3),
6489	Port4_out => crossbar_out_port(4),
6490	Port5_out => crossbar_out_port(5),
6491	Port6_out => crossbar_out_port(6),
6492	Port7_out => crossbar_out_port(7),
6493	Ctrl => Grant_signal);
6494	end generate crossbar_switch7x7;
6495
6496
6497	-- switch 8 ports
6498	crossbar_switch8x8 : if number_of_ports = 8 generate
6499
6500	Switch_Crossbar8_8: Crossbar
6501	GENERIC MAP(number_of_crossbar_ports =>8)
6502	PORT MAP(
6503	reset => reset,
6504	clk =>clk,
6505	Port1_in => crossbar_in_port(1),
6506	Port2_in => crossbar_in_port(2),
6507	Port3_in => crossbar_in_port(3),
6508	Port4_in => crossbar_in_port(4),
6509	Port5_in => crossbar_in_port(5),
6510	Port6_in => crossbar_in_port(6),
6511	Port7_in => crossbar_in_port(7),
6512	Port8_in => crossbar_in_port(8),
6513	Port9_in => "00000000",
6514	Port10_in => "00000000",
6515	Port11_in => "00000000",
6516	Port12_in => "00000000",
6517	Port13_in => "00000000",
6518	Port14_in => "00000000",
6519	Port15_in => "00000000",
6520	Port16_in => "00000000",
6521	Port1_pulse_in => crossbar_in_pulse(1),
6522	Port2_pulse_in => crossbar_in_pulse(2),
6523	Port3_pulse_in => crossbar_in_pulse(3),
6524	Port4_pulse_in => crossbar_in_pulse(4),
6525	Port5_pulse_in => crossbar_in_pulse(5),
6526	Port6_pulse_in => crossbar_in_pulse(6),
6527	Port7_pulse_in => crossbar_in_pulse(7),
6528	Port8_pulse_in => crossbar_in_pulse(8),
6529	Port9_pulse_in =>'0' ,
6530	Port10_pulse_in =>'0' ,
6531	Port11_pulse_in =>'0' ,
6532	Port12_pulse_in =>'0' ,
6533	Port13_pulse_in =>'0' ,
6534	Port14_pulse_in =>'0' ,
6535	Port15_pulse_in =>'0' ,
6536	Port16_pulse_in =>'0' ,
6537	Port1_pulse_out => crossbar_out_pulse(1),
6538	Port2_pulse_out => crossbar_out_pulse(2),
6539	Port3_pulse_out => crossbar_out_pulse(3),
6540	Port4_pulse_out => crossbar_out_pulse(4),
6541	Port5_pulse_out => crossbar_out_pulse(5),
6542	Port6_pulse_out => crossbar_out_pulse(6),
6543	Port7_pulse_out => crossbar_out_pulse(7),
6544	Port8_pulse_out => crossbar_out_pulse(8),
6545	Port1_out => crossbar_out_port(1),
6546	Port2_out => crossbar_out_port(2),
6547	Port3_out => crossbar_out_port(3),
6548	Port4_out => crossbar_out_port(4),
6549	Port5_out => crossbar_out_port(5),
6550	Port6_out => crossbar_out_port(6),
6551	Port7_out => crossbar_out_port(7),
6552	Port8_out => crossbar_out_port(8),
6553	Ctrl => Grant_signal);
6554	end generate crossbar_switch8x8;
6555
6556
6557	-- switch 9 ports
6558	crossbar_switch9x9 : if number_of_ports = 9 generate
6559
6560	Switch_Crossbar9_9: Crossbar
6561	GENERIC MAP(number_of_crossbar_ports =>9)
6562	PORT MAP(
6563	reset => reset,
6564	clk => clk,
6565	Port1_in => crossbar_in_port(1),
6566	Port2_in => crossbar_in_port(2),
6567	Port3_in => crossbar_in_port(3),
6568	Port4_in => crossbar_in_port(4),
6569	Port5_in => crossbar_in_port(5),
6570	Port6_in => crossbar_in_port(6),
6571	Port7_in => crossbar_in_port(7),
6572	Port8_in => crossbar_in_port(8),
6573	Port9_in => crossbar_in_port(9),
6574	Port10_in => "00000000",
6575	Port11_in => "00000000",
6576	Port12_in => "00000000",
6577	Port13_in => "00000000",
6578	Port14_in => "00000000",
6579	Port15_in => "00000000",
6580	Port16_in => "00000000",
6581	Port1_pulse_in => crossbar_in_pulse(1),
6582	Port2_pulse_in => crossbar_in_pulse(2),
6583	Port3_pulse_in => crossbar_in_pulse(3),
6584	Port4_pulse_in => crossbar_in_pulse(4),
6585	Port5_pulse_in => crossbar_in_pulse(5),
6586	Port6_pulse_in => crossbar_in_pulse(6),
6587	Port7_pulse_in => crossbar_in_pulse(7),
6588	Port8_pulse_in => crossbar_in_pulse(8),
6589	Port9_pulse_in => crossbar_in_pulse(9),
6590	Port10_pulse_in =>'0' ,
6591	Port11_pulse_in =>'0' ,
6592	Port12_pulse_in =>'0' ,
6593	Port13_pulse_in =>'0' ,
6594	Port14_pulse_in =>'0' ,
6595	Port15_pulse_in =>'0' ,
6596	Port16_pulse_in =>'0' ,
6597	Port1_pulse_out => crossbar_out_pulse(1),
6598	Port2_pulse_out => crossbar_out_pulse(2),
6599	Port3_pulse_out => crossbar_out_pulse(3),
6600	Port4_pulse_out => crossbar_out_pulse(4),
6601	Port5_pulse_out => crossbar_out_pulse(5),
6602	Port6_pulse_out => crossbar_out_pulse(6),
6603	Port7_pulse_out => crossbar_out_pulse(7),
6604	Port8_pulse_out => crossbar_out_pulse(8),
6605	Port9_pulse_out => crossbar_out_pulse(9),
6606	Port1_out => crossbar_out_port(1),
6607	Port2_out => crossbar_out_port(2),
6608	Port3_out => crossbar_out_port(3),
6609	Port4_out => crossbar_out_port(4),
6610	Port5_out => crossbar_out_port(5),
6611	Port6_out => crossbar_out_port(6),
6612	Port7_out => crossbar_out_port(7),
6613	Port8_out => crossbar_out_port(8),
6614	Port9_out => crossbar_out_port(9),
6615	Ctrl => Grant_signal);
6616	end generate crossbar_switch9x9;
6617
6618
6619	-- switch 10 ports
6620	crossbar_switch10x10 : if number_of_ports = 10 generate
6621
6622	Switch_Crossbar10_10: Crossbar
6623	GENERIC MAP(number_of_crossbar_ports =>10)
6624	PORT MAP(
6625	reset => reset,
6626	clk => clk,
6627	Port1_in => crossbar_in_port(1),
6628	Port2_in => crossbar_in_port(2),
6629	Port3_in => crossbar_in_port(3),
6630	Port4_in => crossbar_in_port(4),
6631	Port5_in => crossbar_in_port(5),
6632	Port6_in => crossbar_in_port(6),
6633	Port7_in => crossbar_in_port(7),
6634	Port8_in => crossbar_in_port(8),
6635	Port9_in => crossbar_in_port(9),
6636	Port10_in => crossbar_in_port(10),
6637	Port11_in => "00000000",
6638	Port12_in => "00000000",
6639	Port13_in => "00000000",
6640	Port14_in => "00000000",
6641	Port15_in => "00000000",
6642	Port16_in => "00000000",
6643	Port1_pulse_in => crossbar_in_pulse(1),
6644	Port2_pulse_in => crossbar_in_pulse(2),
6645	Port3_pulse_in => crossbar_in_pulse(3),
6646	Port4_pulse_in => crossbar_in_pulse(4),
6647	Port5_pulse_in => crossbar_in_pulse(5),
6648	Port6_pulse_in => crossbar_in_pulse(6),
6649	Port7_pulse_in => crossbar_in_pulse(7),
6650	Port8_pulse_in => crossbar_in_pulse(8),
6651	Port9_pulse_in => crossbar_in_pulse(9),
6652	Port10_pulse_in => crossbar_in_pulse(10),
6653	Port11_pulse_in =>'0' ,
6654	Port12_pulse_in =>'0' ,
6655	Port13_pulse_in =>'0' ,
6656	Port14_pulse_in =>'0' ,
6657	Port15_pulse_in =>'0' ,
6658	Port16_pulse_in =>'0' ,
6659	Port1_pulse_out => crossbar_out_pulse(1),
6660	Port2_pulse_out => crossbar_out_pulse(2),
6661	Port3_pulse_out => crossbar_out_pulse(3),
6662	Port4_pulse_out => crossbar_out_pulse(4),
6663	Port5_pulse_out => crossbar_out_pulse(5),
6664	Port6_pulse_out => crossbar_out_pulse(6),
6665	Port7_pulse_out => crossbar_out_pulse(7),
6666	Port8_pulse_out => crossbar_out_pulse(8),
6667	Port9_pulse_out => crossbar_out_pulse(9),
6668	Port10_pulse_out => crossbar_out_pulse(10),
6669	Port1_out => crossbar_out_port(1),
6670	Port2_out => crossbar_out_port(2),
6671	Port3_out => crossbar_out_port(3),
6672	Port4_out => crossbar_out_port(4),
6673	Port5_out => crossbar_out_port(5),
6674	Port6_out => crossbar_out_port(6),
6675	Port7_out => crossbar_out_port(7),
6676	Port8_out => crossbar_out_port(8),
6677	Port9_out => crossbar_out_port(9),
6678	Port10_out => crossbar_out_port(10),
6679	Ctrl => Grant_signal);
6680	end generate crossbar_switch10x10;
6681
6682
6683	-- switch 11 ports
6684	crossbar_switch11x11 : if number_of_ports = 11 generate
6685
6686	Switch_Crossbar11_11: Crossbar
6687	GENERIC MAP(number_of_crossbar_ports =>11)
6688	PORT MAP(
6689	reset => reset,
6690	clk => clk,
6691	Port1_in => crossbar_in_port(1),
6692	Port2_in => crossbar_in_port(2),
6693	Port3_in => crossbar_in_port(3),
6694	Port4_in => crossbar_in_port(4),
6695	Port5_in => crossbar_in_port(5),
6696	Port6_in => crossbar_in_port(6),
6697	Port7_in => crossbar_in_port(7),
6698	Port8_in => crossbar_in_port(8),
6699	Port9_in => crossbar_in_port(9),
6700	Port10_in => crossbar_in_port(10),
6701	Port11_in => crossbar_in_port(11),
6702	Port12_in => "00000000",
6703	Port13_in => "00000000",
6704	Port14_in => "00000000",
6705	Port15_in => "00000000",
6706	Port16_in => "00000000",
6707	Port1_pulse_in => crossbar_in_pulse(1),
6708	Port2_pulse_in => crossbar_in_pulse(2),
6709	Port3_pulse_in => crossbar_in_pulse(3),
6710	Port4_pulse_in => crossbar_in_pulse(4),
6711	Port5_pulse_in => crossbar_in_pulse(5),
6712	Port6_pulse_in => crossbar_in_pulse(6),
6713	Port7_pulse_in => crossbar_in_pulse(7),
6714	Port8_pulse_in => crossbar_in_pulse(8),
6715	Port9_pulse_in => crossbar_in_pulse(9),
6716	Port10_pulse_in => crossbar_in_pulse(10),
6717	Port11_pulse_in => crossbar_in_pulse(11),
6718	Port12_pulse_in =>'0' ,
6719	Port13_pulse_in =>'0' ,
6720	Port14_pulse_in =>'0' ,
6721	Port15_pulse_in =>'0' ,
6722	Port16_pulse_in =>'0' ,
6723	Port1_pulse_out => crossbar_out_pulse(1),
6724	Port2_pulse_out => crossbar_out_pulse(2),
6725	Port3_pulse_out => crossbar_out_pulse(3),
6726	Port4_pulse_out => crossbar_out_pulse(4),
6727	Port5_pulse_out => crossbar_out_pulse(5),
6728	Port6_pulse_out => crossbar_out_pulse(6),
6729	Port7_pulse_out => crossbar_out_pulse(7),
6730	Port8_pulse_out => crossbar_out_pulse(8),
6731	Port9_pulse_out => crossbar_out_pulse(9),
6732	Port10_pulse_out => crossbar_out_pulse(10),
6733	Port11_pulse_out => crossbar_out_pulse(11),
6734	Port1_out => crossbar_out_port(1),
6735	Port2_out => crossbar_out_port(2),
6736	Port3_out => crossbar_out_port(3),
6737	Port4_out => crossbar_out_port(4),
6738	Port5_out => crossbar_out_port(5),
6739	Port6_out => crossbar_out_port(6),
6740	Port7_out => crossbar_out_port(7),
6741	Port8_out => crossbar_out_port(8),
6742	Port9_out => crossbar_out_port(9),
6743	Port10_out => crossbar_out_port(10),
6744	Port11_out => crossbar_out_port(11),
6745	Ctrl => Grant_signal);
6746	end generate crossbar_switch11x11;
6747
6748
6749	-- switch 12 ports
6750	crossbar_switch12x12 : if number_of_ports = 12 generate
6751
6752	Switch_Crossbar12_12: Crossbar
6753	GENERIC MAP(number_of_crossbar_ports =>12)
6754	PORT MAP(
6755	reset => reset,
6756	clk => clk,
6757	Port1_in => crossbar_in_port(1),
6758	Port2_in => crossbar_in_port(2),
6759	Port3_in => crossbar_in_port(3),
6760	Port4_in => crossbar_in_port(4),
6761	Port5_in => crossbar_in_port(5),
6762	Port6_in => crossbar_in_port(6),
6763	Port7_in => crossbar_in_port(7),
6764	Port8_in => crossbar_in_port(8),
6765	Port9_in => crossbar_in_port(9),
6766	Port10_in => crossbar_in_port(10),
6767	Port11_in => crossbar_in_port(11),
6768	Port12_in => crossbar_in_port(12),
6769	Port13_in => "00000000",
6770	Port14_in => "00000000",
6771	Port15_in => "00000000",
6772	Port16_in => "00000000",
6773	Port1_pulse_in => crossbar_in_pulse(1),
6774	Port2_pulse_in => crossbar_in_pulse(2),
6775	Port3_pulse_in => crossbar_in_pulse(3),
6776	Port4_pulse_in => crossbar_in_pulse(4),
6777	Port5_pulse_in => crossbar_in_pulse(5),
6778	Port6_pulse_in => crossbar_in_pulse(6),
6779	Port7_pulse_in => crossbar_in_pulse(7),
6780	Port8_pulse_in => crossbar_in_pulse(8),
6781	Port9_pulse_in => crossbar_in_pulse(9),
6782	Port10_pulse_in => crossbar_in_pulse(10),
6783	Port11_pulse_in => crossbar_in_pulse(11),
6784	Port12_pulse_in => crossbar_in_pulse(12),
6785	Port13_pulse_in =>'0' ,
6786	Port14_pulse_in =>'0' ,
6787	Port15_pulse_in =>'0' ,
6788	Port16_pulse_in =>'0' ,
6789	Port1_pulse_out => crossbar_out_pulse(1),
6790	Port2_pulse_out => crossbar_out_pulse(2),
6791	Port3_pulse_out => crossbar_out_pulse(3),
6792	Port4_pulse_out => crossbar_out_pulse(4),
6793	Port5_pulse_out => crossbar_out_pulse(5),
6794	Port6_pulse_out => crossbar_out_pulse(6),
6795	Port7_pulse_out => crossbar_out_pulse(7),
6796	Port8_pulse_out => crossbar_out_pulse(8),
6797	Port9_pulse_out => crossbar_out_pulse(9),
6798	Port10_pulse_out => crossbar_out_pulse(10),
6799	Port11_pulse_out => crossbar_out_pulse(11),
6800	Port12_pulse_out => crossbar_out_pulse(12),
6801	Port1_out => crossbar_out_port(1),
6802	Port2_out => crossbar_out_port(2),
6803	Port3_out => crossbar_out_port(3),
6804	Port4_out => crossbar_out_port(4),
6805	Port5_out => crossbar_out_port(5),
6806	Port6_out => crossbar_out_port(6),
6807	Port7_out => crossbar_out_port(7),
6808	Port8_out => crossbar_out_port(8),
6809	Port9_out => crossbar_out_port(9),
6810	Port10_out => crossbar_out_port(10),
6811	Port11_out => crossbar_out_port(11),
6812	Port12_out => crossbar_out_port(12),
6813	Ctrl => Grant_signal);
6814	end generate crossbar_switch12x12;
6815
6816
6817	-- switch 13 ports
6818	crossbar_switch13x13 : if number_of_ports = 13 generate
6819
6820	Switch_Crossbar13_13: Crossbar
6821	GENERIC MAP(number_of_crossbar_ports =>13)
6822	PORT MAP(
6823	reset => reset,
6824	clk => clk,
6825	Port1_in => crossbar_in_port(1),
6826	Port2_in => crossbar_in_port(2),
6827	Port3_in => crossbar_in_port(3),
6828	Port4_in => crossbar_in_port(4),
6829	Port5_in => crossbar_in_port(5),
6830	Port6_in => crossbar_in_port(6),
6831	Port7_in => crossbar_in_port(7),
6832	Port8_in => crossbar_in_port(8),
6833	Port9_in => crossbar_in_port(9),
6834	Port10_in => crossbar_in_port(10),
6835	Port11_in => crossbar_in_port(11),
6836	Port12_in => crossbar_in_port(12),
6837	Port13_in => crossbar_in_port(13),
6838	Port14_in => "00000000",
6839	Port15_in => "00000000",
6840	Port16_in => "00000000",
6841	Port1_pulse_in => crossbar_in_pulse(1),
6842	Port2_pulse_in => crossbar_in_pulse(2),
6843	Port3_pulse_in => crossbar_in_pulse(3),
6844	Port4_pulse_in => crossbar_in_pulse(4),
6845	Port5_pulse_in => crossbar_in_pulse(5),
6846	Port6_pulse_in => crossbar_in_pulse(6),
6847	Port7_pulse_in => crossbar_in_pulse(7),
6848	Port8_pulse_in => crossbar_in_pulse(8),
6849	Port9_pulse_in => crossbar_in_pulse(9),
6850	Port10_pulse_in => crossbar_in_pulse(10),
6851	Port11_pulse_in => crossbar_in_pulse(11),
6852	Port12_pulse_in => crossbar_in_pulse(12),
6853	Port13_pulse_in => crossbar_in_pulse(13),
6854	Port14_pulse_in =>'0' ,
6855	Port15_pulse_in =>'0' ,
6856	Port16_pulse_in =>'0' ,
6857	Port1_pulse_out => crossbar_out_pulse(1),
6858	Port2_pulse_out => crossbar_out_pulse(2),
6859	Port3_pulse_out => crossbar_out_pulse(3),
6860	Port4_pulse_out => crossbar_out_pulse(4),
6861	Port5_pulse_out => crossbar_out_pulse(5),
6862	Port6_pulse_out => crossbar_out_pulse(6),
6863	Port7_pulse_out => crossbar_out_pulse(7),
6864	Port8_pulse_out => crossbar_out_pulse(8),
6865	Port9_pulse_out => crossbar_out_pulse(9),
6866	Port10_pulse_out => crossbar_out_pulse(10),
6867	Port11_pulse_out => crossbar_out_pulse(11),
6868	Port12_pulse_out => crossbar_out_pulse(12),
6869	Port13_pulse_out => crossbar_out_pulse(13),
6870	Port1_out => crossbar_out_port(1),
6871	Port2_out => crossbar_out_port(2),
6872	Port3_out => crossbar_out_port(3),
6873	Port4_out => crossbar_out_port(4),
6874	Port5_out => crossbar_out_port(5),
6875	Port6_out => crossbar_out_port(6),
6876	Port7_out => crossbar_out_port(7),
6877	Port8_out => crossbar_out_port(8),
6878	Port9_out => crossbar_out_port(9),
6879	Port10_out => crossbar_out_port(10),
6880	Port11_out => crossbar_out_port(11),
6881	Port12_out => crossbar_out_port(12),
6882	Port13_out => crossbar_out_port(13),
6883	Ctrl => Grant_signal);
6884	end generate crossbar_switch13x13;
6885
6886
6887	-- switch 14 ports
6888	crossbar_switch14x14 : if number_of_ports = 14 generate
6889
6890	Switch_Crossbar14_14: Crossbar
6891	GENERIC MAP(number_of_crossbar_ports =>14)
6892	PORT MAP(
6893	reset => reset,
6894	clk => clk,
6895	Port1_in => crossbar_in_port(1),
6896	Port2_in => crossbar_in_port(2),
6897	Port3_in => crossbar_in_port(3),
6898	Port4_in => crossbar_in_port(4),
6899	Port5_in => crossbar_in_port(5),
6900	Port6_in => crossbar_in_port(6),
6901	Port7_in => crossbar_in_port(7),
6902	Port8_in => crossbar_in_port(8),
6903	Port9_in => crossbar_in_port(9),
6904	Port10_in => crossbar_in_port(10),
6905	Port11_in => crossbar_in_port(11),
6906	Port12_in => crossbar_in_port(12),
6907	Port13_in => crossbar_in_port(13),
6908	Port14_in => crossbar_in_port(14),
6909	Port15_in => "00000000",
6910	Port16_in => "00000000",
6911	Port1_pulse_in => crossbar_in_pulse(1),
6912	Port2_pulse_in => crossbar_in_pulse(2),
6913	Port3_pulse_in => crossbar_in_pulse(3),
6914	Port4_pulse_in => crossbar_in_pulse(4),
6915	Port5_pulse_in => crossbar_in_pulse(5),
6916	Port6_pulse_in => crossbar_in_pulse(6),
6917	Port7_pulse_in => crossbar_in_pulse(7),
6918	Port8_pulse_in => crossbar_in_pulse(8),
6919	Port9_pulse_in => crossbar_in_pulse(9),
6920	Port10_pulse_in => crossbar_in_pulse(10),
6921	Port11_pulse_in => crossbar_in_pulse(11),
6922	Port12_pulse_in => crossbar_in_pulse(12),
6923	Port13_pulse_in => crossbar_in_pulse(13),
6924	Port14_pulse_in => crossbar_in_pulse(14),
6925	Port15_pulse_in =>'0' ,
6926	Port16_pulse_in =>'0' ,
6927	Port1_pulse_out => crossbar_out_pulse(1),
6928	Port2_pulse_out => crossbar_out_pulse(2),
6929	Port3_pulse_out => crossbar_out_pulse(3),
6930	Port4_pulse_out => crossbar_out_pulse(4),
6931	Port5_pulse_out => crossbar_out_pulse(5),
6932	Port6_pulse_out => crossbar_out_pulse(6),
6933	Port7_pulse_out => crossbar_out_pulse(7),
6934	Port8_pulse_out => crossbar_out_pulse(8),
6935	Port9_pulse_out => crossbar_out_pulse(9),
6936	Port10_pulse_out => crossbar_out_pulse(10),
6937	Port11_pulse_out => crossbar_out_pulse(11),
6938	Port12_pulse_out => crossbar_out_pulse(12),
6939	Port13_pulse_out => crossbar_out_pulse(13),
6940	Port14_pulse_out => crossbar_out_pulse(14),
6941	Port1_out => crossbar_out_port(1),
6942	Port2_out => crossbar_out_port(2),
6943	Port3_out => crossbar_out_port(3),
6944	Port4_out => crossbar_out_port(4),
6945	Port5_out => crossbar_out_port(5),
6946	Port6_out => crossbar_out_port(6),
6947	Port7_out => crossbar_out_port(7),
6948	Port8_out => crossbar_out_port(8),
6949	Port9_out => crossbar_out_port(9),
6950	Port10_out => crossbar_out_port(10),
6951	Port11_out => crossbar_out_port(11),
6952	Port12_out => crossbar_out_port(12),
6953	Port13_out => crossbar_out_port(13),
6954	Port14_out => crossbar_out_port(14),
6955	Ctrl => Grant_signal);
6956	end generate crossbar_switch14x14;
6957
6958
6959	-- switch 15 ports
6960	crossbar_switch15x15 : if number_of_ports = 15 generate
6961
6962	Switch_Crossbar15_15: Crossbar
6963	GENERIC MAP(number_of_crossbar_ports =>15)
6964	PORT MAP(
6965	reset => reset,
6966	clk => clk,
6967	Port1_in => crossbar_in_port(1),
6968	Port2_in => crossbar_in_port(2),
6969	Port3_in => crossbar_in_port(3),
6970	Port4_in => crossbar_in_port(4),
6971	Port5_in => crossbar_in_port(5),
6972	Port6_in => crossbar_in_port(6),
6973	Port7_in => crossbar_in_port(7),
6974	Port8_in => crossbar_in_port(8),
6975	Port9_in => crossbar_in_port(9),
6976	Port10_in => crossbar_in_port(10),
6977	Port11_in => crossbar_in_port(11),
6978	Port12_in => crossbar_in_port(12),
6979	Port13_in => crossbar_in_port(13),
6980	Port14_in => crossbar_in_port(14),
6981	Port15_in => crossbar_in_port(15),
6982	Port16_in => "00000000",
6983	Port1_pulse_in => crossbar_in_pulse(1),
6984	Port2_pulse_in => crossbar_in_pulse(2),
6985	Port3_pulse_in => crossbar_in_pulse(3),
6986	Port4_pulse_in => crossbar_in_pulse(4),
6987	Port5_pulse_in => crossbar_in_pulse(5),
6988	Port6_pulse_in => crossbar_in_pulse(6),
6989	Port7_pulse_in => crossbar_in_pulse(7),
6990	Port8_pulse_in => crossbar_in_pulse(8),
6991	Port9_pulse_in => crossbar_in_pulse(9),
6992	Port10_pulse_in => crossbar_in_pulse(10),
6993	Port11_pulse_in => crossbar_in_pulse(11),
6994	Port12_pulse_in => crossbar_in_pulse(12),
6995	Port13_pulse_in => crossbar_in_pulse(13),
6996	Port14_pulse_in => crossbar_in_pulse(14),
6997	Port15_pulse_in => crossbar_in_pulse(15),
6998	Port16_pulse_in =>'0' ,
6999	Port1_pulse_out => crossbar_out_pulse(1),
7000	Port2_pulse_out => crossbar_out_pulse(2),
7001	Port3_pulse_out => crossbar_out_pulse(3),
7002	Port4_pulse_out => crossbar_out_pulse(4),
7003	Port5_pulse_out => crossbar_out_pulse(5),
7004	Port6_pulse_out => crossbar_out_pulse(6),
7005	Port7_pulse_out => crossbar_out_pulse(7),
7006	Port8_pulse_out => crossbar_out_pulse(8),
7007	Port9_pulse_out => crossbar_out_pulse(9),
7008	Port10_pulse_out => crossbar_out_pulse(10),
7009	Port11_pulse_out => crossbar_out_pulse(11),
7010	Port12_pulse_out => crossbar_out_pulse(12),
7011	Port13_pulse_out => crossbar_out_pulse(13),
7012	Port14_pulse_out => crossbar_out_pulse(14),
7013	Port15_pulse_out => crossbar_out_pulse(15),
7014	Port1_out => crossbar_out_port(1),
7015	Port2_out => crossbar_out_port(2),
7016	Port3_out => crossbar_out_port(3),
7017	Port4_out => crossbar_out_port(4),
7018	Port5_out => crossbar_out_port(5),
7019	Port6_out => crossbar_out_port(6),
7020	Port7_out => crossbar_out_port(7),
7021	Port8_out => crossbar_out_port(8),
7022	Port9_out => crossbar_out_port(9),
7023	Port10_out => crossbar_out_port(10),
7024	Port11_out => crossbar_out_port(11),
7025	Port12_out => crossbar_out_port(12),
7026	Port13_out => crossbar_out_port(13),
7027	Port14_out => crossbar_out_port(14),
7028	Port15_out => crossbar_out_port(15),
7029	Ctrl => Grant_signal);
7030	end generate crossbar_switch15x15;
7031
7032
7033	-- switch 16 ports
7034	crossbar_switch16x16 : if number_of_ports = 16 generate
7035
7036	Switch_Crossbar16_16: Crossbar
7037	GENERIC MAP(number_of_crossbar_ports =>16)
7038	PORT MAP(
7039	reset => reset,
7040	clk => clk,
7041	Port1_in => crossbar_in_port(1),
7042	Port2_in => crossbar_in_port(2),
7043	Port3_in => crossbar_in_port(3),
7044	Port4_in => crossbar_in_port(4),
7045	Port5_in => crossbar_in_port(5),
7046	Port6_in => crossbar_in_port(6),
7047	Port7_in => crossbar_in_port(7),
7048	Port8_in => crossbar_in_port(8),
7049	Port9_in => crossbar_in_port(9),
7050	Port10_in => crossbar_in_port(10),
7051	Port11_in => crossbar_in_port(11),
7052	Port12_in => crossbar_in_port(12),
7053	Port13_in => crossbar_in_port(13),
7054	Port14_in => crossbar_in_port(14),
7055	Port15_in => crossbar_in_port(15),
7056	Port16_in => crossbar_in_port(16),
7057	Port1_pulse_in => crossbar_in_pulse(1),
7058	Port2_pulse_in => crossbar_in_pulse(2),
7059	Port3_pulse_in => crossbar_in_pulse(3),
7060	Port4_pulse_in => crossbar_in_pulse(4),
7061	Port5_pulse_in => crossbar_in_pulse(5),
7062	Port6_pulse_in => crossbar_in_pulse(6),
7063	Port7_pulse_in => crossbar_in_pulse(7),
7064	Port8_pulse_in => crossbar_in_pulse(8),
7065	Port9_pulse_in => crossbar_in_pulse(9),
7066	Port10_pulse_in => crossbar_in_pulse(10),
7067	Port11_pulse_in => crossbar_in_pulse(11),
7068	Port12_pulse_in => crossbar_in_pulse(12),
7069	Port13_pulse_in => crossbar_in_pulse(13),
7070	Port14_pulse_in => crossbar_in_pulse(14),
7071	Port15_pulse_in => crossbar_in_pulse(15),
7072	Port16_pulse_in => crossbar_in_pulse(16),
7073	Port1_pulse_out => crossbar_out_pulse(1),
7074	Port2_pulse_out => crossbar_out_pulse(2),
7075	Port3_pulse_out => crossbar_out_pulse(3),
7076	Port4_pulse_out => crossbar_out_pulse(4),
7077	Port5_pulse_out => crossbar_out_pulse(5),
7078	Port6_pulse_out => crossbar_out_pulse(6),
7079	Port7_pulse_out => crossbar_out_pulse(7),
7080	Port8_pulse_out => crossbar_out_pulse(8),
7081	Port9_pulse_out => crossbar_out_pulse(9),
7082	Port10_pulse_out => crossbar_out_pulse(10),
7083	Port11_pulse_out => crossbar_out_pulse(11),
7084	Port12_pulse_out => crossbar_out_pulse(12),
7085	Port13_pulse_out => crossbar_out_pulse(13),
7086	Port14_pulse_out => crossbar_out_pulse(14),
7087	Port15_pulse_out => crossbar_out_pulse(15),
7088	Port16_pulse_out => crossbar_out_pulse(16),
7089	Port1_out => crossbar_out_port(1),
7090	Port2_out => crossbar_out_port(2),
7091	Port3_out => crossbar_out_port(3),
7092	Port4_out => crossbar_out_port(4),
7093	Port5_out => crossbar_out_port(5),
7094	Port6_out => crossbar_out_port(6),
7095	Port7_out => crossbar_out_port(7),
7096	Port8_out => crossbar_out_port(8),
7097	Port9_out => crossbar_out_port(9),
7098	Port10_out => crossbar_out_port(10),
7099	Port11_out => crossbar_out_port(11),
7100	Port12_out => crossbar_out_port(12),
7101	Port13_out => crossbar_out_port(13),
7102	Port14_out => crossbar_out_port(14),
7103	Port15_out => crossbar_out_port(15),
7104	Port16_out => crossbar_out_port(16),
7105	Ctrl => Grant_signal);
7106	end generate crossbar_switch16x16;
7107	-- intstanciation et connexion du scheduler en fonction du nombre de ports
7108	-- le circuit genere depend du parametre generique nombre de ports
7109	-- switch 2 ports
7110	scheduler_switch2x2 : if number_of_ports = 2 generate
7111
7112	Scheduler2_2: Scheduler
7113	GENERIC MAP(number_of_ports => 2 )
7114	PORT MAP(
7115	Request => Request_signal,
7116	Fifo_full => fifo_out_full_signal,
7117	clk => clk,
7118	priority_rotation =>priority_rotation_signal,
7119	reset => reset,
7120	port_grant => grant_signal
7121	);
7122
7123	end generate scheduler_switch2x2;
7124
7125
7126	-- switch 3 ports
7127	scheduler_switch3x3 : if number_of_ports = 3 generate
7128
7129	Scheduler3_3: Scheduler
7130	GENERIC MAP(number_of_ports => 3 )
7131	PORT MAP(
7132	Request => Request_signal,
7133	Fifo_full => fifo_out_full_signal,
7134	clk => clk,
7135	priority_rotation =>priority_rotation_signal,
7136	reset => reset,
7137	port_grant => grant_signal
7138	);
7139
7140	end generate scheduler_switch3x3;
7141
7142
7143	-- switch 4 ports
7144	scheduler_switch4x4 : if number_of_ports = 4 generate
7145
7146	Scheduler4_4: Scheduler
7147	GENERIC MAP(number_of_ports => 4 )
7148	PORT MAP(
7149	Request => Request_signal,
7150	Fifo_full => fifo_out_full_signal,
7151	clk => clk,
7152	priority_rotation =>priority_rotation_signal,
7153	reset => reset,
7154	port_grant => grant_signal
7155	);
7156
7157	end generate scheduler_switch4x4;
7158
7159
7160	-- switch 5 ports
7161	scheduler_switch5x5 : if number_of_ports = 5 generate
7162
7163	Scheduler5_5: Scheduler
7164	GENERIC MAP(number_of_ports => 5 )
7165	PORT MAP(
7166	Request => Request_signal,
7167	Fifo_full => fifo_out_full_signal,
7168	clk => clk,
7169	priority_rotation =>priority_rotation_signal,
7170	reset => reset,
7171	port_grant => grant_signal
7172	);
7173
7174	end generate scheduler_switch5x5;
7175
7176
7177	-- switch 6 ports
7178	scheduler_switch6x6 : if number_of_ports = 6 generate
7179
7180	Scheduler6_6: Scheduler
7181	GENERIC MAP(number_of_ports => 6 )
7182	PORT MAP(
7183	Request => Request_signal,
7184	Fifo_full => fifo_out_full_signal,
7185	clk => clk,
7186	priority_rotation =>priority_rotation_signal,
7187	reset => reset,
7188	port_grant => grant_signal
7189	);
7190
7191	end generate scheduler_switch6x6;
7192
7193
7194	-- switch 7 ports
7195	scheduler_switch7x7 : if number_of_ports = 7 generate
7196
7197	Scheduler7_7: Scheduler
7198	GENERIC MAP(number_of_ports => 7 )
7199	PORT MAP(
7200	Request => Request_signal,
7201	Fifo_full => fifo_out_full_signal,
7202	clk => clk,
7203	priority_rotation =>priority_rotation_signal,
7204	reset => reset,
7205	port_grant => grant_signal
7206	);
7207
7208	end generate scheduler_switch7x7;
7209
7210
7211	-- switch 8 ports
7212	scheduler_switch8x8 : if number_of_ports = 8 generate
7213
7214	Scheduler8_8: Scheduler
7215	GENERIC MAP(number_of_ports => 8 )
7216	PORT MAP(
7217	Request => Request_signal,
7218	Fifo_full => fifo_out_full_signal,
7219	clk => clk,
7220	priority_rotation =>priority_rotation_signal,
7221	reset => reset,
7222	port_grant => grant_signal
7223	);
7224
7225	end generate scheduler_switch8x8;
7226
7227
7228	-- switch 9 ports
7229	scheduler_switch9x9 : if number_of_ports = 9 generate
7230
7231	Scheduler9_9: Scheduler
7232	GENERIC MAP(number_of_ports => 9 )
7233	PORT MAP(
7234	Request => Request_signal,
7235	Fifo_full => fifo_out_full_signal,
7236	clk => clk,
7237	priority_rotation =>priority_rotation_signal,
7238	reset => reset,
7239	port_grant => grant_signal
7240	);
7241
7242	end generate scheduler_switch9x9;
7243
7244
7245	-- switch 10 ports
7246	scheduler_switch10x10 : if number_of_ports = 10 generate
7247
7248	Scheduler10_10: Scheduler
7249	GENERIC MAP(number_of_ports => 10 )
7250	PORT MAP(
7251	Request => Request_signal,
7252	Fifo_full => fifo_out_full_signal,
7253	clk => clk,
7254	priority_rotation =>priority_rotation_signal,
7255	reset => reset,
7256	port_grant => grant_signal
7257	);
7258
7259	end generate scheduler_switch10x10;
7260
7261
7262	-- switch 11 ports
7263	scheduler_switch11x11 : if number_of_ports = 11 generate
7264
7265	Scheduler11_11: Scheduler
7266	GENERIC MAP(number_of_ports => 11 )
7267	PORT MAP(
7268	Request => Request_signal,
7269	Fifo_full => fifo_out_full_signal,
7270	clk => clk,
7271	priority_rotation =>priority_rotation_signal,
7272	reset => reset,
7273	port_grant => grant_signal
7274	);
7275
7276	end generate scheduler_switch11x11;
7277
7278
7279	-- switch 12 ports
7280	scheduler_switch12x12 : if number_of_ports = 12 generate
7281
7282	Scheduler12_12: Scheduler
7283	GENERIC MAP(number_of_ports => 12 )
7284	PORT MAP(
7285	Request => Request_signal,
7286	Fifo_full => fifo_out_full_signal,
7287	clk => clk,
7288	priority_rotation =>priority_rotation_signal,
7289	reset => reset,
7290	port_grant => grant_signal
7291	);
7292
7293	end generate scheduler_switch12x12;
7294
7295
7296	-- switch 13 ports
7297	scheduler_switch13x13 : if number_of_ports = 13 generate
7298
7299	Scheduler13_13: Scheduler
7300	GENERIC MAP(number_of_ports => 13 )
7301	PORT MAP(
7302	Request => Request_signal,
7303	Fifo_full => fifo_out_full_signal,
7304	clk => clk,
7305	priority_rotation =>priority_rotation_signal,
7306	reset => reset,
7307	port_grant => grant_signal
7308	);
7309
7310	end generate scheduler_switch13x13;
7311
7312
7313	-- switch 14 ports
7314	scheduler_switch14x14 : if number_of_ports = 14 generate
7315
7316	Scheduler14_14: Scheduler
7317	GENERIC MAP(number_of_ports => 14 )
7318	PORT MAP(
7319	Request => Request_signal,
7320	Fifo_full => fifo_out_full_signal,
7321	clk => clk,
7322	priority_rotation =>priority_rotation_signal,
7323	reset => reset,
7324	port_grant => grant_signal
7325	);
7326
7327	end generate scheduler_switch14x14;
7328
7329
7330	-- switch 15 ports
7331	scheduler_switch15x15 : if number_of_ports = 15 generate
7332
7333	Scheduler15_15: Scheduler
7334	GENERIC MAP(number_of_ports => 15 )
7335	PORT MAP(
7336	Request => Request_signal,
7337	Fifo_full => fifo_out_full_signal,
7338	clk => clk,
7339	priority_rotation =>priority_rotation_signal,
7340	reset => reset,
7341	port_grant => grant_signal
7342	);
7343
7344	end generate scheduler_switch15x15;
7345
7346
7347	-- switch 16 ports
7348	scheduler_switch16x16 : if number_of_ports = 16 generate
7349
7350	Scheduler16_16: Scheduler
7351	GENERIC MAP(number_of_ports => 16 )
7352	PORT MAP(
7353	Request => Request_signal,
7354	Fifo_full => fifo_out_full_signal,
7355	clk => clk,
7356	priority_rotation =>priority_rotation_signal,
7357	reset => reset,
7358	port_grant => grant_signal
7359	);
7360
7361	end generate scheduler_switch16x16;
7362
7363
7364	end Behavioral;

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source: PROJECT_CORE_MPI/MPI_HCL/TRUNK/NOC/SWITCH_GEN.vhd @ 101

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