source: PROJECT_CORE_MPI/MPI_HCL/TRUNK/NOC/proto_send.vhd

Last change on this file was 101, checked in by rolagamo, 13 years ago
File size: 5.5 KB
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1----------------------------------------------------------------------------------
2-- Company:
3-- Engineer:
4--
5-- Create Date: 18:01:21 10/23/2012
6-- Design Name:
7-- Module Name: proto_send - Behavioral
8-- Project Name:
9-- Target Devices:
10-- Tool versions:
11-- Description:
12--
13-- Dependencies:
14--
15-- Revision:
16-- Revision 0.01 - File Created
17-- Additional Comments:
18--
19----------------------------------------------------------------------------------
20library IEEE;
21use IEEE.STD_LOGIC_1164.ALL;
22USE ieee.numeric_std.ALL;
23use work.CoreTypes.all;
24-- Uncomment the following library declaration if using
25-- arithmetic functions with Signed or Unsigned values
26--use IEEE.NUMERIC_STD.ALL;
27
28-- Uncomment the following library declaration if instantiating
29-- any Xilinx primitives in this code.
30--library UNISIM;
31--use UNISIM.VComponents.all;
32
33entity proto_send is
34generic (sizemem : natural := 64);
35 port (
36 clk,reset : in std_logic;
37 fifo_in_empty,fifo_in_full : in std_logic; --signaux pour le fifo d'entrée
38 fifo_out_empty,fifo_out_full : in std_logic; --signaux pour le fifo de sortie
39 fifo_out_wr_en : out std_logic:='0'; --écriture autorisée dans la fifo de sortie
40 fifo_in_rd_en : out std_logic:='0'; --lecture autorisée dans la fifo d'entrée
41 fifo_in_data_out : in std_logic_vector(Word-1 downto 0);
42 fifo_out_data_in : out std_logic_vector(Word-1 downto 0);
43 packet_len : in std_logic_vector(Word-1 downto 0); --la longueur du paquet
44 copy_mode : in std_logic; --Fifo_to_mem ou Fifo_to_fifo
45 snd_start : in std_logic; --début de la réception
46 snd_ack :in std_logic; -- acquittement de la réception
47 snd_comp : out std_logic; -- fin de la réception
48 mem :in memory(0 to sizemem-1)); --données à copier vers le fifo
49
50end proto_send;
51
52architecture Behavioral of proto_send is
53type typ_send is (s_head,s_len,s_len2,s_data,s_pulse,s_end);
54 signal etsnd : typ_send;
55 signal snd_state,next_snd_state:natural range 0 to 7:=0;
56 signal p_len,p_len_i : natural range 0 to 255;
57 signal n,n_i:natural range 0 to 7;
58 signal wr_ok,rd_ok:std_logic:='0';
59 signal wr_ok_i,rd_ok_i:std_logic:='0';
60 signal sfifo_in,Data_to_send,Data_to_send_i : std_logic_vector(Word-1 downto 0);
61 signal spush : std_logic:='0';
62 signal err : std_logic_vector(Word-1 downto 0):=(others =>'0');
63begin
64
65Fifo_copy_sync:process(clk,reset)
66
67begin
68
69
70 if reset='1' then
71 n<=0;
72 Snd_state<=0;
73 P_len<=0;
74 Data_to_send<=(others=>'0');
75else
76 if rising_edge(clk) then
77 Snd_state<=Next_Snd_state;
78 n<=n_i;
79 p_len<=P_len_i;
80 Data_to_send<=Data_to_send_i;
81 wr_ok<=wr_ok_i;
82 rd_ok<=rd_ok_i;
83end if;
84end if;
85end process fifo_copy_sync;
86 -- affectation concurentes
87 Fifo_copy_val:process (Snd_state,Etsnd,copy_mode,data_to_send,rd_ok,wr_ok,spush)
88begin
89 fifo_out_wr_en<='0';
90 fifo_in_rd_en<='0';
91 fifo_out_data_in<=data_to_send;
92 if copy_mode='0' then
93 fifo_out_wr_en<=wr_ok;
94 fifo_out_data_in<=data_to_send;
95 fifo_in_rd_en<='0';
96else
97 if (Snd_state=1) or (snd_state=2) then
98 fifo_out_wr_en<=wr_ok;
99 fifo_in_rd_en<=rd_ok;
100 fifo_out_data_in<=data_to_send;
101 end if;
102end if;
103end process fifo_copy_val;
104 -- process qui envoie des données en provenance d'un Fifo vers un Fifo
105 FIfo_to_fifo:process(snd_state,copy_mode,snd_start,snd_ack,fifo_in_empty,
106 fifo_out_full,Fifo_in_data_out,p_len,n,mem,wr_ok,rd_ok,packet_len)
107 variable onepop:std_logic:='0';
108 begin
109 Next_snd_state<=snd_state; --valeur par defaut
110 Data_To_Send_i<=Data_to_send;
111 wr_ok_i<=wr_ok;
112 rd_ok_i<=rd_ok;
113 n_i<=n;
114 p_len_i<=p_len;
115 snd_comp<='0';
116 case snd_state is
117
118 when 0 => if snd_start='1' then
119 P_len_i<=to_integer(unsigned(packet_len));
120 next_snd_state<=1;
121 n_i<=0;
122 end if;
123 wr_ok_i<='0';rd_ok_i<='0';onepop:='0';
124 snd_comp<='0';
125 when 1=> --placer la première donnée sur le bus
126 if copy_mode='1' then
127 if fifo_in_empty='0' then
128 data_to_send_i <=fifo_in_data_out ;
129 end if;
130 else
131 data_to_send_i<=mem(n);
132 end if;
133 next_snd_state<=2;
134 when 2=> if P_len>0 then
135 if copy_mode='1' then
136 if fifo_in_empty='0' and onepop='0' then
137 data_to_send_i <=fifo_in_data_out ;
138 rd_Ok_i<='1';
139 onepop:='1'; --une donnée lue il faut arrêter de dépiler
140
141 else
142 rd_Ok_i<='0';
143 end if;
144 else
145 onepop:='1';rd_ok_i<='0'; --pas besoin de signal de lecture ici
146 data_to_send_i<=mem(n);
147 end if;
148
149 if (fifo_out_full = '0') and onepop='1' then
150 wr_ok_i<='1';
151 onepop:='0';
152 p_len_i<=p_len-1;
153 n_i<=n+1;
154 else
155 wr_Ok_i<='0';
156 end if;
157 else
158 rd_ok_i<='0';
159 wr_ok_i<='0';
160 next_snd_state<=3;
161 snd_comp<='1';
162 end if;
163 when 3 => --fin de la copie
164 if snd_ack='1' then
165
166 next_snd_state<=4;
167 end if;
168 wr_ok_i<='0';rd_ok_i<='0';
169 snd_comp<='1';
170
171 when 4 =>next_snd_state<=0;
172 snd_comp<='0';
173
174when others => next_snd_state<=0;
175 snd_comp<='0';
176 rd_ok_i<='0';
177 wr_ok_i<='0';
178 data_to_send_i <=(others=>'U');
179 end case;
180 end process FIfo_to_fifo;
181
182end Behavioral;
183
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