[106] | 1 | ---------------------------------------------------------------------------------- |
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| 2 | -- Company: |
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| 3 | -- Engineer: GAMOM Roland Christian |
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| 4 | -- |
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| 5 | -- Create Date: 21:20:54 07/16/2012 |
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| 6 | -- Design Name: |
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| 7 | -- Module Name: PE - Behavioral |
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| 8 | -- Project Name: |
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| 9 | -- Target Devices: |
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| 10 | -- Tool versions: |
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| 11 | -- Description: Ce module permet d'encapsuler une tâche matérielle |
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| 12 | -- et lui donne la possiblité de communiquer à l'aide des fonctions MPI-2 RMA |
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| 13 | -- Dependencies: |
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| 14 | -- |
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| 15 | -- Revision: |
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| 16 | -- Revision 0.01 - File Created |
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| 17 | -- Additional Comments: |
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| 18 | -- |
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| 19 | ---------------------------------------------------------------------------------- |
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| 20 | library IEEE; |
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| 21 | use IEEE.STD_LOGIC_1164.ALL; |
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| 22 | library NocLib ; |
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| 23 | library Std; |
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| 24 | --use IEEE.STD_LOGIC_ARITH.ALL; |
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| 25 | --use IEEE.STD_LOGIC_UNSIGNED.ALL; |
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| 26 | Library MPI_HCL; |
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| 27 | use NocLib.CoreTypes.all; |
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| 28 | use MPI_HCL.Packet_type.all; |
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| 29 | use MPI_HCL.MPI_RMA.all; |
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| 30 | -- synthesis translate_off |
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| 31 | use std.textio.all; |
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| 32 | -- synthesis translate_on |
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| 33 | use IEEE.NUMERIC_STD.ALL; |
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| 34 | |
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| 35 | |
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| 36 | entity PE is |
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| 37 | Generic (DestId : natural:=0 ); |
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| 38 | Port ( Instruction : out STD_LOGIC_VECTOR (Word-1 downto 0); |
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| 39 | Instruction_en : out STD_LOGIC; |
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| 40 | Core_PushOut : in STD_LOGIC_VECTOR (Word-1 downto 0); |
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| 41 | clk : in STD_LOGIC; |
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| 42 | reset : in STD_LOGIC; |
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| 43 | CE : in STD_LOGIC; -- Active le PE après sa synthèse |
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| 44 | Core_RAM_Data_Out : out STD_LOGIC_VECTOR (Word-1 downto 0); |
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| 45 | Core_RAM_Data_In : in STD_LOGIC_VECTOR (Word-1 downto 0); |
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| 46 | Core_RAM_WE : in STD_LOGIC; |
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| 47 | Core_RAM_EN : in STD_LOGIC; |
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| 48 | --Core_RAM_ENB : in STD_LOGIC; |
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| 49 | Core_RAM_ADDRESS_WR : in STD_LOGIC_VECTOR (ADRLEN-1 downto 0); |
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| 50 | Core_RAM_ADDRESS_RD : in STD_LOGIC_VECTOR (ADRLEN-1 downto 0); |
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| 51 | Core_Hold_req : in STD_LOGIC; |
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| 52 | Core_Hold_Ack : out STD_LOGIC); |
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| 53 | end PE; |
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| 54 | |
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| 55 | architecture Behavioral of PE is |
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| 56 | COMPONENT RAM_v |
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| 57 | generic (width : positive;size :positive); |
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| 58 | PORT( |
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| 59 | clka : IN std_logic; |
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| 60 | clkb : IN std_logic; |
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| 61 | wea : IN std_logic; |
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| 62 | ena : IN std_logic; |
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| 63 | enb : IN std_logic; |
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| 64 | addra : IN std_logic_vector; |
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| 65 | addrb : IN std_logic_vector; |
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| 66 | dia : IN std_logic_vector; |
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| 67 | dob : OUT std_logic_vector |
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| 68 | ); |
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| 69 | END COMPONENT; |
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| 70 | COMPONENT mem8k8 |
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| 71 | PORT ( |
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| 72 | clka : IN STD_LOGIC; |
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| 73 | ena : IN STD_LOGIC; |
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| 74 | wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0); |
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| 75 | addra : IN STD_LOGIC_VECTOR(12 DOWNTO 0); |
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| 76 | dina : IN STD_LOGIC_VECTOR(7 DOWNTO 0); |
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| 77 | clkb : IN STD_LOGIC; |
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| 78 | enb : IN STD_LOGIC; |
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| 79 | addrb : IN STD_LOGIC_VECTOR(12 DOWNTO 0); |
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| 80 | doutb : OUT STD_LOGIC_VECTOR(7 DOWNTO 0) |
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| 81 | ); |
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| 82 | END COMPONENT; |
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| 83 | COMPONENT HT_process is |
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| 84 | generic (Task_Id : natural); |
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| 85 | Port ( clk : in STD_LOGIC; |
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| 86 | reset : in STD_LOGIC; |
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| 87 | en : in std_logic; -- active la tâche |
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| 88 | Interf_i : in core_i; --signaux pour l'interface I |
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| 89 | Interf_o : out core_o; --signaux pour l'interface IO |
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| 90 | mem_i : in typ_dpram_i; -- signaux pour l'accès à la mémoire |
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| 91 | mem_o : out typ_dpram_o -- signaux pour l'accès à la mémoire |
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| 92 | ); |
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| 93 | end COMPONENT HT_process; |
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| 94 | |
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| 95 | COMPONENT Hold_FSM is |
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| 96 | |
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| 97 | Port ( Hold_Req : in STD_LOGIC; |
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| 98 | Ram_busy : in STD_LOGIC; |
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| 99 | Clk : in STD_LOGIC; |
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| 100 | Reset : in STD_LOGIC; |
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| 101 | Ramsel : out STD_LOGIC; |
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| 102 | Hold_Ack : out STD_LOGIC); |
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| 103 | end COMPONENT Hold_FSM; |
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| 104 | --données du programme PE |
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| 105 | --signaux pour l'interconnexionsignal datain :std_logic_vector(word-1 downto 0):= (others => '0'); |
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| 106 | signal ram_we ,ram_ena,ram_enb,ramsel_i: std_logic:='0'; |
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| 107 | signal pe_ram_we ,pe_ram_ena,pe_ram_enb: std_logic; |
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| 108 | signal pe_instr_en,pe_hold_ack: std_logic:='0'; |
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| 109 | signal ram_do,ram_din:std_logic_vector(word-1 downto 0):= (others => '0'); |
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| 110 | signal pe_ram_do,pe_ram_din:std_logic_vector(word-1 downto 0):= (others => '0'); |
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| 111 | signal ram_addra,ram_addrb :std_logic_vector(ADRLEN-1 downto 0); |
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| 112 | signal pe_ram_addra,pe_ram_addrb :std_logic_vector(ADRLEN-1 downto 0); |
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| 113 | signal sram : typ_dpram; |
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| 114 | signal clk_ht : std_logic; |
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| 115 | signal MyGroup:mpi_group; |
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| 116 | signal MyWin : mpi_win; |
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| 117 | signal SrcAdr0,SrcAdr1,destAdr0,destAdr1,Datalen:std_logic_vector(word-1 downto 0); |
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| 118 | signal dpid,dpid_i : natural range 0 to 15:=DestId; |
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| 119 | signal MyRank :std_logic_vector(3 downto 0); |
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| 120 | signal Libr : Core_io; --regroupe tous les signaux IO de la bibliothèque |
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| 121 | signal Lib_Ready:std_logic; --indique que l'exécution de la fonction est terminée |
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| 122 | signal Lib_instr_ack : std_logic; -- l'instruction est copiée dans le tampon FIFO |
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| 123 | signal Lib_Init : std_logic; -- l'initialisation est terminée |
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| 124 | signal Lib_Enable : std_logic:='0'; |
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| 125 | signal Ex1_run,Ex4_run : std_logic:='0'; --indique que ces modules sont en fin d'exécution |
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| 126 | signal Hold_Ack : std_logic; |
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| 127 | signal en_task : std_logic; |
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| 128 | signal ht_reset :std_logic; |
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| 129 | --signaux pour la gestion de la MAE |
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| 130 | type typ_mae is (start,Fillmem,NextFill,InitApp,GetRank,WInCreate,WinStart, putdata,getdata,WinCompleted,finalize,st_timeout); |
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| 131 | type typ_Hld is (Ht_Lock,Core_Lock,Ht_free); |
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| 132 | signal dcount : natural range 0 to 255:=0; |
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| 133 | signal wea : std_logic_vector (0 downto 0); |
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| 134 | signal count,count_i : natural range 0 to 15:=0; |
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| 135 | |
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| 136 | |
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| 137 | signal RunState : typ_mae; |
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| 138 | signal Hld_state :typ_hld; |
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| 139 | signal Ram_busy :std_logic:='0'; |
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| 140 | begin |
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| 141 | --Inst_RAM_v: RAM_v generic map(width=>word,size=>ADRLEN) |
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| 142 | -- PORT MAP( |
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| 143 | -- clka =>clk , |
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| 144 | -- clkb => clk , |
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| 145 | -- wea => ram_we, |
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| 146 | -- ena => ram_ena, |
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| 147 | -- enb => ram_enb, |
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| 148 | -- addra => ram_addra, |
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| 149 | -- addrb =>ram_addrb, |
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| 150 | -- dia => ram_din, |
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| 151 | -- dob => ram_do |
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| 152 | -- ); |
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| 153 | wea(0)<=ram_we; |
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| 154 | Ram8k8 : mem8k8 |
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| 155 | PORT MAP ( |
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| 156 | clka => clk, |
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| 157 | ena => ram_ena, |
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| 158 | wea => wea, |
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| 159 | addra => ram_addra(12 downto 0), |
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| 160 | dina => ram_din, |
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| 161 | clkb => clk, |
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| 162 | enb => ram_enb, |
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| 163 | addrb => ram_addrb(12 downto 0), |
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| 164 | doutb => ram_do |
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| 165 | ); |
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| 166 | HT_task:HT_process generic map(Task_id =>DestId) |
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| 167 | port map ( |
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| 168 | clk=>clk, |
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| 169 | reset=>ht_reset, |
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| 170 | en=>en_task, |
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| 171 | Interf_i =>Libr.i, |
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| 172 | Interf_o=>Libr.o, |
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| 173 | mem_i =>sram.i, |
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| 174 | mem_o =>sram.o ); |
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| 175 | |
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| 176 | --================================================================ |
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| 177 | --MUX de la RAM |
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| 178 | |
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| 179 | Ram_mux: process (clk,ramsel_i,pe_ram_addra,pe_ram_addrb,Core_ram_address_rd,Core_ram_address_wr, |
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| 180 | Core_ram_en,Core_ram_we,Core_ram_data_in,pe_ram_ena,pe_ram_enb,Ram_do, |
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| 181 | Pe_ram_din,Pe_ram_we ) |
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| 182 | begin |
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| 183 | case ramsel_i is |
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| 184 | |
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| 185 | when '1' => |
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| 186 | ram_addra <= Core_ram_address_wr ; |
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| 187 | ram_addrb <= Core_ram_address_rd ; |
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| 188 | ram_ena <= Core_ram_en; |
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| 189 | ram_enb <= Core_ram_en; |
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| 190 | ram_we<= Core_ram_we; |
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| 191 | ram_din <= Core_ram_data_in; |
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| 192 | pe_ram_do<=(others=>'U'); |
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| 193 | Core_ram_data_out<=ram_do; |
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| 194 | |
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| 195 | when others => |
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| 196 | ram_addra <= pe_ram_addra; |
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| 197 | ram_addrb <= pe_ram_addrb; |
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| 198 | ram_ena <= pe_ram_ena; |
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| 199 | ram_enb <= pe_ram_enb; |
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| 200 | ram_we<= pe_ram_we; |
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| 201 | ram_din <=pe_ram_din; |
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| 202 | Core_ram_data_out<=(others=>'U'); |
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| 203 | pe_ram_do<=ram_do; |
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| 204 | end case ; |
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| 205 | end process ; |
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| 206 | |
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| 207 | |
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| 208 | |
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| 209 | Instruction_En<=PE_instr_EN; -- Libr.Instr_en; --********A changer ********** |
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| 210 | --=== !!!!! attention la suppression de la ligne ci-dessous empêche ce |
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| 211 | -- composant de bien fonctionner !!! !!!!!!!!!!!!!!!!!!!!!!! |
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| 212 | --instruction<=std_logic_vector(to_unsigned(Core_upper_adr,8)); |
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| 213 | |
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| 214 | dpid<=dpid_i; |
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| 215 | en_task<= CE or Lib_enable; --l'activation d'une HT peut être directe ou commandée |
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| 216 | Lib_Instr_ack<=Core_Pushout(0); --l'instruction a été copié |
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| 217 | Lib_init<=Core_Pushout(4); -- Initialized |
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| 218 | Lib_Enable<=Core_Pushout(6);-- HT activée par la Librairie. |
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| 219 | Ex1_Run<=Core_Pushout(5); -- fin de l'exécution de Ex1 |
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| 220 | Ex4_Run<=Core_pushout(7); -- fin de l'exécution de Ex4 pour Spawn |
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| 221 | horloge_ht:process (reset,en_task,clk) |
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| 222 | begin |
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| 223 | if reset='1' then |
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| 224 | clk_ht<='0'; |
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| 225 | count<=0; |
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| 226 | Ht_reset<='1'; |
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| 227 | else |
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| 228 | if en_task='1' then |
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| 229 | clk_ht<=clk; |
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| 230 | if count=10 then --circuit de reset pour la HT |
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| 231 | ht_reset<='0'; |
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| 232 | else |
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| 233 | if rising_edge(clk) then |
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| 234 | count<=count+1; |
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| 235 | end if; |
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| 236 | ht_reset<='1'; |
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| 237 | end if; |
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| 238 | else |
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| 239 | count<=0; |
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| 240 | clk_ht<='0'; |
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| 241 | Ht_reset<='1'; |
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| 242 | end if; |
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| 243 | end if; |
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| 244 | end process horloge_ht; |
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| 245 | |
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| 246 | Hold1: Hold_fsm port map ( |
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| 247 | clk=>clk , |
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| 248 | reset =>reset, |
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| 249 | Ram_Busy=>Ram_busy, |
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| 250 | Hold_Ack=>Hold_Ack, |
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| 251 | Hold_req =>Core_Hold_Req, |
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| 252 | RamSel => RamSel_i); |
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| 253 | Core_Hold_Ack<=Hold_Ack; |
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| 254 | |
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| 255 | --================RAM signals ====================== |
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| 256 | sram.I.data_out<=PE_ram_do; |
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| 257 | pe_Ram_addra<=sram.O.addr_wr; |
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| 258 | pe_Ram_addrb<=sram.O.addr_rd ; |
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| 259 | PE_Ram_we<=sram.O.we; |
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| 260 | PE_Ram_ena<=sram.O.ena; |
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| 261 | PE_Ram_enb<=sram.O.enb; |
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| 262 | PE_ram_din<=sram.O.data_in; |
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| 263 | --==========MPI HCL signals ============================ |
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| 264 | |
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| 265 | affect:process (clk,en_task,Lib_enable,Core_hold_req,RamSel_i,Core_pushout,Libr.O) |
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| 266 | begin |
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| 267 | --if (clk'event and clk='1') then |
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| 268 | if en_task='1' then |
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| 269 | Instruction<=Libr.O.Instruction; |
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| 270 | Ram_busy<=Libr.O.membusy; |
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| 271 | PE_Instr_EN<=Libr.O.instr_en; |
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| 272 | else --si le HT n'est pas activé ces valeurs sont à 0 ! |
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| 273 | Instruction<=(others=>'0'); |
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| 274 | Ram_busy<='0'; |
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| 275 | PE_Instr_EN<='0'; |
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| 276 | end if; |
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| 277 | Libr.I.Instr_ack<=Core_pushout(0); |
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| 278 | Libr.I.InitOk<=Core_pushout(4); |
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| 279 | if Lib_enable='1' then |
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| 280 | Libr.I.Spawned<='1'; |
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| 281 | else |
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| 282 | Libr.I.Spawned<='0'; |
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| 283 | end if; |
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| 284 | Libr.I.Hold_Req<=Core_Hold_req; |
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| 285 | --Libr.I.Hold_Ack<=Hold_Ack; |
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| 286 | Libr.I.RamSel<=RamSel_i; |
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| 287 | --end if; |
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| 288 | assert not(Lib_enable='1') |
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| 289 | report "Spawn Activé" |
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| 290 | severity WARNING ; |
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| 291 | |
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| 292 | end process affect; |
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| 293 | --======================================================================= |
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| 294 | --MAE du PE |
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| 295 | --======================================================================= |
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| 296 | |
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| 297 | |
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| 298 | end Behavioral; |
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| 299 | |
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