Rev | Line | |
---|
[115] | 1 | <?xml version="1.0" encoding="UTF-8"?> |
---|
| 2 | <!-- IMPORTANT: This is an internal file that has been generated |
---|
| 3 | by the Xilinx ISE software. Any direct editing or |
---|
| 4 | changes made to this file may result in unpredictable |
---|
| 5 | behavior or data corruption. It is strongly advised that |
---|
| 6 | users do not edit the contents of this file. --> |
---|
| 7 | <messages> |
---|
[137] | 8 | <msg type="info" file="sim" num="0" delta="new" >Generating component instance '<arg fmt="%s" index="1">mem8k8</arg>' of '<arg fmt="%s" index="2">xilinx.com:ip:blk_mem_gen:6.2</arg>' from '<arg fmt="%s" index="3">C:\Xilinx\13.3\ISE_DS\ISE\coregen\ip\xilinx\primary\com\xilinx\ip\blk_mem_gen_v6_2\component.xml</arg>'. |
---|
[115] | 9 | </msg> |
---|
| 10 | |
---|
[137] | 11 | <msg type="warning" file="sim" num="0" delta="new" ><arg fmt="%s" index="1">A core named 'mem8k8' already exists in the project. Output products for this core may be overwritten.</arg> |
---|
| 12 | </msg> |
---|
| 13 | |
---|
| 14 | <msg type="info" file="sim" num="0" delta="new" ><arg fmt="%s" index="1">Pre-processing HDL files for 'mem8k8'...</arg> |
---|
| 15 | </msg> |
---|
| 16 | |
---|
| 17 | <msg type="info" file="sim" num="0" delta="new" >Finished generation of ASY schematic symbol. |
---|
| 18 | </msg> |
---|
| 19 | |
---|
| 20 | <msg type="info" file="sim" num="0" delta="new" >Finished FLIST file generation. |
---|
| 21 | </msg> |
---|
| 22 | |
---|
[115] | 23 | </messages> |
---|
| 24 | |
---|
Note: See
TracBrowser
for help on using the repository browser.