source: PROJECT_CORE_MPI/MPI_HCL/TRUNK/Test_Timer/ipcore_dir/_xmsgs/cg.xmsgs @ 137

<?xml version="1.0" encoding="UTF-8"?>
<!-- IMPORTANT: This is an internal file that has been generated
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<messages>
<msg type="info" file="sim" num="0" delta="new" >Generating component instance &apos;<arg fmt="%s" index="1">mem8k8</arg>&apos; of &apos;<arg fmt="%s" index="2">xilinx.com:ip:blk_mem_gen:6.2</arg>&apos; from &apos;<arg fmt="%s" index="3">C:\Xilinx\13.3\ISE_DS\ISE\coregen\ip\xilinx\primary\com\xilinx\ip\blk_mem_gen_v6_2\component.xml</arg>&apos;.
</msg>

<msg type="warning" file="sim" num="0" delta="new" ><arg fmt="%s" index="1">A core named &apos;mem8k8&apos; already exists in the project. Output products for this core may be overwritten.</arg>
</msg>

<msg type="info" file="sim" num="0" delta="new" ><arg fmt="%s" index="1">Pre-processing HDL files for &apos;mem8k8&apos;...</arg>
</msg>

<msg type="info" file="sim" num="0" delta="new" >Finished generation of ASY schematic symbol.
</msg>

<msg type="info" file="sim" num="0" delta="new" >Finished FLIST file generation.
</msg>

</messages>