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1 | <?xml version="1.0" encoding="UTF-8"?> |
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2 | <!-- IMPORTANT: This is an internal file that has been generated |
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3 | by the Xilinx ISE software. Any direct editing or |
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4 | changes made to this file may result in unpredictable |
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5 | behavior or data corruption. It is strongly advised that |
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6 | users do not edit the contents of this file. --> |
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7 | <messages> |
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8 | <msg type="info" file="sim" num="0" delta="new" >Generating component instance '<arg fmt="%s" index="1">mem8k8</arg>' of '<arg fmt="%s" index="2">xilinx.com:ip:blk_mem_gen:6.2</arg>' from '<arg fmt="%s" index="3">C:\Xilinx\13.3\ISE_DS\ISE\coregen\ip\xilinx\primary\com\xilinx\ip\blk_mem_gen_v6_2\component.xml</arg>'. |
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9 | </msg> |
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10 | |
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11 | <msg type="warning" file="sim" num="0" delta="new" ><arg fmt="%s" index="1">A core named 'mem8k8' already exists in the project. Output products for this core may be overwritten.</arg> |
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12 | </msg> |
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13 | |
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14 | <msg type="info" file="sim" num="0" delta="new" ><arg fmt="%s" index="1">Pre-processing HDL files for 'mem8k8'...</arg> |
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15 | </msg> |
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16 | |
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17 | <msg type="info" file="sim" num="0" delta="new" >Finished generation of ASY schematic symbol. |
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18 | </msg> |
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19 | |
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20 | <msg type="info" file="sim" num="0" delta="new" >Finished FLIST file generation. |
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21 | </msg> |
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22 | |
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23 | </messages> |
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24 | |
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