1 | -------------------------------------------------------------------------------- |
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2 | -- This file is owned and controlled by Xilinx and must be used solely -- |
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3 | -- for design, simulation, implementation and creation of design files -- |
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4 | -- limited to Xilinx devices or technologies. Use with non-Xilinx -- |
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5 | -- devices or technologies is expressly prohibited and immediately -- |
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6 | -- terminates your license. -- |
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7 | -- -- |
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8 | -- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY -- |
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9 | -- FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY -- |
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10 | -- PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE -- |
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11 | -- IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS -- |
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12 | -- MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY -- |
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13 | -- CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY -- |
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14 | -- RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY -- |
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15 | -- DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE -- |
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16 | -- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR -- |
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17 | -- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF -- |
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18 | -- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A -- |
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19 | -- PARTICULAR PURPOSE. -- |
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20 | -- -- |
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21 | -- Xilinx products are not intended for use in life support appliances, -- |
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22 | -- devices, or systems. Use in such applications are expressly -- |
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23 | -- prohibited. -- |
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24 | -- -- |
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25 | -- (c) Copyright 1995-2014 Xilinx, Inc. -- |
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26 | -- All rights reserved. -- |
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27 | -------------------------------------------------------------------------------- |
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28 | |
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29 | -------------------------------------------------------------------------------- |
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30 | -- Generated from core with identifier: xilinx.com:ip:blk_mem_gen:6.2 -- |
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31 | -- -- |
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32 | -- The Xilinx LogiCORE IP Block Memory Generator replaces the Dual Port -- |
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33 | -- Block Memory and Single Port Block Memory LogiCOREs, but is not a -- |
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34 | -- direct drop-in replacement. It should be used in all new Xilinx -- |
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35 | -- designs. The core supports RAM and ROM functions over a wide range of -- |
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36 | -- widths and depths. Use this core to generate block memories with -- |
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37 | -- symmetric or asymmetric read and write port widths, as well as cores -- |
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38 | -- which can perform simultaneous write operations to separate -- |
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39 | -- locations, and simultaneous read operations from the same location. -- |
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40 | -- For more information on differences in interface and feature support -- |
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41 | -- between this core and the Dual Port Block Memory and Single Port -- |
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42 | -- Block Memory LogiCOREs, please consult the data sheet. -- |
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43 | -------------------------------------------------------------------------------- |
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44 | |
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45 | -- Interfaces: |
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46 | -- AXI_SLAVE_S_AXI |
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47 | -- AXILite_SLAVE_S_AXI |
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48 | |
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49 | -- The following code must appear in the VHDL architecture header: |
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50 | |
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51 | ------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG |
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52 | COMPONENT blk_mem_gen_v6_2 |
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53 | PORT ( |
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54 | clka : IN STD_LOGIC; |
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55 | ena : IN STD_LOGIC; |
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56 | wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0); |
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57 | addra : IN STD_LOGIC_VECTOR(12 DOWNTO 0); |
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58 | dina : IN STD_LOGIC_VECTOR(7 DOWNTO 0); |
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59 | clkb : IN STD_LOGIC; |
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60 | enb : IN STD_LOGIC; |
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61 | addrb : IN STD_LOGIC_VECTOR(12 DOWNTO 0); |
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62 | doutb : OUT STD_LOGIC_VECTOR(7 DOWNTO 0) |
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63 | ); |
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64 | END COMPONENT; |
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65 | -- COMP_TAG_END ------ End COMPONENT Declaration ------------ |
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66 | |
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67 | -- The following code must appear in the VHDL architecture |
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68 | -- body. Substitute your own instance name and net names. |
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69 | |
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70 | ------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG |
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71 | your_instance_name : blk_mem_gen_v6_2 |
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72 | PORT MAP ( |
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73 | clka => clka, |
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74 | ena => ena, |
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75 | wea => wea, |
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76 | addra => addra, |
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77 | dina => dina, |
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78 | clkb => clkb, |
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79 | enb => enb, |
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80 | addrb => addrb, |
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81 | doutb => doutb |
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82 | ); |
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83 | -- INST_TAG_END ------ End INSTANTIATION Template ------------ |
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84 | |
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85 | -- You must compile the wrapper file blk_mem_gen_v6_2.vhd when simulating |
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86 | -- the core, blk_mem_gen_v6_2. When compiling the wrapper file, be sure to |
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87 | -- reference the XilinxCoreLib VHDL simulation library. For detailed |
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88 | -- instructions, please refer to the "CORE Generator Help". |
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89 | |
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