Last change
on this file since 153 was
115,
checked in by rolagamo, 11 years ago
|
Ajout des Cores utilisés dans le projet
|
File size:
1.0 KB
|
Rev | Line | |
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[115] | 1 | |
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| 2 | rem Clean up the results directory |
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| 3 | rmdir /S /Q results |
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| 4 | mkdir results |
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| 5 | |
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| 6 | rem Synthesize the VHDL Wrapper Files |
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| 7 | |
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| 8 | |
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| 9 | echo 'Synthesizing example design with XST'; |
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| 10 | xst -ifn xst.scr |
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| 11 | copy blk_mem_gen_v6_2_top.ngc .\results\ |
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| 12 | |
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| 13 | |
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| 14 | rem Copy the netlist generated by Coregen |
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| 15 | echo 'Copying files from the netlist directory to the results directory' |
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| 16 | copy ..\..\blk_mem_gen_v6_2.ngc results\ |
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| 17 | |
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| 18 | |
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| 19 | rem Copy the constraints files generated by Coregen |
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| 20 | echo 'Copying files from constraints directory to results directory' |
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| 21 | copy ..\example_design\blk_mem_gen_v6_2_top.ucf results\ |
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| 22 | |
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| 23 | cd results |
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| 24 | |
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| 25 | echo 'Running ngdbuild' |
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| 26 | ngdbuild -p xc6slx45-csg324-3 blk_mem_gen_v6_2_top |
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| 27 | |
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| 28 | echo 'Running map' |
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| 29 | map blk_mem_gen_v6_2_top -o mapped.ncd -pr i |
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| 30 | |
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| 31 | echo 'Running par' |
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| 32 | par mapped.ncd routed.ncd |
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| 33 | |
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| 34 | echo 'Running trce' |
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| 35 | trce -e 10 routed.ncd mapped.pcf -o routed |
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| 36 | |
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| 37 | echo 'Running design through bitgen' |
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| 38 | bitgen -w routed |
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| 39 | |
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| 40 | echo 'Running netgen to create gate level VHDL model' |
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| 41 | netgen -ofmt vhdl -sim -tm blk_mem_gen_v6_2_top -pcf mapped.pcf -w routed.ncd routed.vhd |
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