source: PROJECT_CORE_MPI/MPI_HCL/TRUNK/Test_Timer/ipcore_dir/blk_mem_gen_v6_2_ste/implement/planAhead_rdn.tcl @ 115

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set device xc6slx45csg324-3
set projName blk_mem_gen_v6_2
set design blk_mem_gen_v6_2
set projDir [file dirname [info script]]
create_project $projName $projDir/results/$projName -part $device -force
set_property design_mode RTL [current_fileset -srcset]
set top_module blk_mem_gen_v6_2_top
add_files -norecurse {../../example_design/blk_mem_gen_v6_2_top.vhd}
add_files -norecurse {./blk_mem_gen_v6_2.edf}
import_files -fileset [get_filesets constrs_1] -force -norecurse {../../example_design/blk_mem_gen_v6_2_top.xdc}
set_property top blk_mem_gen_v6_2_top [get_property srcset [current_run]]
synth_design
opt_design 
place_design 
route_design 
set_param sta.dlyMediator true
write_sdf -rename_top_module blk_mem_gen_v6_2_top -file routed.sdf 
write_verilog -nolib -mode sim -sdf_anno false -rename_top_module blk_mem_gen_v6_2_top routed.vhd
report_timing -nworst 30 -path_type full -file routed.twr
report_drc -file routed.drc
#write_bitstream