source:
PROJECT_CORE_MPI/MPI_HCL/TRUNK/Test_Timer/ipcore_dir/coregen.cgp
@
116
Last change on this file since 116 was 115, checked in by , 11 years ago | |
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File size: 235 bytes |
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1 | SET busformat = BusFormatAngleBracketNotRipped |
2 | SET designentry = VHDL |
3 | SET device = xc6slx45 |
4 | SET devicefamily = spartan6 |
5 | SET flowvendor = Other |
6 | SET package = csg324 |
7 | SET speedgrade = -3 |
8 | SET verilogsim = false |
9 | SET vhdlsim = true |
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