[115] | 1 | -------------------------------------------------------------------------------- |
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| 2 | -- This file is owned and controlled by Xilinx and must be used solely -- |
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| 3 | -- for design, simulation, implementation and creation of design files -- |
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| 4 | -- limited to Xilinx devices or technologies. Use with non-Xilinx -- |
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| 5 | -- devices or technologies is expressly prohibited and immediately -- |
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| 6 | -- terminates your license. -- |
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| 7 | -- -- |
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| 8 | -- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY -- |
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| 9 | -- FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY -- |
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| 10 | -- PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE -- |
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| 11 | -- IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS -- |
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| 12 | -- MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY -- |
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| 13 | -- CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY -- |
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| 14 | -- RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY -- |
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| 15 | -- DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE -- |
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| 16 | -- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR -- |
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| 17 | -- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF -- |
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| 18 | -- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A -- |
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| 19 | -- PARTICULAR PURPOSE. -- |
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| 20 | -- -- |
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| 21 | -- Xilinx products are not intended for use in life support appliances, -- |
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| 22 | -- devices, or systems. Use in such applications are expressly -- |
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| 23 | -- prohibited. -- |
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| 24 | -- -- |
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| 25 | -- (c) Copyright 1995-2014 Xilinx, Inc. -- |
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| 26 | -- All rights reserved. -- |
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| 27 | -------------------------------------------------------------------------------- |
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| 28 | -------------------------------------------------------------------------------- |
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| 29 | -- You must compile the wrapper file mem8k8.vhd when simulating |
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| 30 | -- the core, mem8k8. When compiling the wrapper file, be sure to |
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| 31 | -- reference the XilinxCoreLib VHDL simulation library. For detailed |
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| 32 | -- instructions, please refer to the "CORE Generator Help". |
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| 33 | |
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| 34 | -- The synthesis directives "translate_off/translate_on" specified |
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| 35 | -- below are supported by Xilinx, Mentor Graphics and Synplicity |
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| 36 | -- synthesis tools. Ensure they are correct for your synthesis tool(s). |
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| 37 | |
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| 38 | LIBRARY ieee; |
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| 39 | USE ieee.std_logic_1164.ALL; |
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| 40 | -- synthesis translate_off |
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| 41 | LIBRARY XilinxCoreLib; |
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| 42 | -- synthesis translate_on |
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| 43 | ENTITY mem8k8 IS |
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| 44 | PORT ( |
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| 45 | clka : IN STD_LOGIC; |
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| 46 | ena : IN STD_LOGIC; |
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| 47 | wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0); |
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| 48 | addra : IN STD_LOGIC_VECTOR(12 DOWNTO 0); |
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| 49 | dina : IN STD_LOGIC_VECTOR(7 DOWNTO 0); |
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| 50 | clkb : IN STD_LOGIC; |
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| 51 | enb : IN STD_LOGIC; |
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| 52 | addrb : IN STD_LOGIC_VECTOR(12 DOWNTO 0); |
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| 53 | doutb : OUT STD_LOGIC_VECTOR(7 DOWNTO 0) |
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| 54 | ); |
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| 55 | END mem8k8; |
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| 56 | |
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| 57 | ARCHITECTURE mem8k8_a OF mem8k8 IS |
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| 58 | -- synthesis translate_off |
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| 59 | COMPONENT wrapped_mem8k8 |
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| 60 | PORT ( |
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| 61 | clka : IN STD_LOGIC; |
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| 62 | ena : IN STD_LOGIC; |
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| 63 | wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0); |
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| 64 | addra : IN STD_LOGIC_VECTOR(12 DOWNTO 0); |
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| 65 | dina : IN STD_LOGIC_VECTOR(7 DOWNTO 0); |
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| 66 | clkb : IN STD_LOGIC; |
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| 67 | enb : IN STD_LOGIC; |
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| 68 | addrb : IN STD_LOGIC_VECTOR(12 DOWNTO 0); |
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| 69 | doutb : OUT STD_LOGIC_VECTOR(7 DOWNTO 0) |
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| 70 | ); |
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| 71 | END COMPONENT; |
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| 72 | |
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| 73 | -- Configuration specification |
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| 74 | FOR ALL : wrapped_mem8k8 USE ENTITY XilinxCoreLib.blk_mem_gen_v6_2(behavioral) |
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| 75 | GENERIC MAP ( |
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| 76 | c_addra_width => 13, |
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| 77 | c_addrb_width => 13, |
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| 78 | c_algorithm => 1, |
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| 79 | c_axi_id_width => 4, |
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| 80 | c_axi_slave_type => 0, |
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| 81 | c_axi_type => 1, |
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| 82 | c_byte_size => 9, |
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| 83 | c_common_clk => 0, |
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| 84 | c_default_data => "0", |
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| 85 | c_disable_warn_bhv_coll => 0, |
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| 86 | c_disable_warn_bhv_range => 0, |
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[137] | 87 | c_family => "artix7", |
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[115] | 88 | c_has_axi_id => 0, |
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| 89 | c_has_ena => 1, |
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| 90 | c_has_enb => 1, |
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| 91 | c_has_injecterr => 0, |
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| 92 | c_has_mem_output_regs_a => 0, |
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| 93 | c_has_mem_output_regs_b => 0, |
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| 94 | c_has_mux_output_regs_a => 0, |
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| 95 | c_has_mux_output_regs_b => 0, |
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| 96 | c_has_regcea => 0, |
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| 97 | c_has_regceb => 0, |
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| 98 | c_has_rsta => 0, |
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| 99 | c_has_rstb => 0, |
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| 100 | c_has_softecc_input_regs_a => 0, |
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| 101 | c_has_softecc_output_regs_b => 0, |
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| 102 | c_init_file_name => "no_coe_file_loaded", |
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| 103 | c_inita_val => "0", |
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| 104 | c_initb_val => "0", |
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| 105 | c_interface_type => 0, |
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| 106 | c_load_init_file => 0, |
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| 107 | c_mem_type => 1, |
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| 108 | c_mux_pipeline_stages => 0, |
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| 109 | c_prim_type => 1, |
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| 110 | c_read_depth_a => 8191, |
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| 111 | c_read_depth_b => 8191, |
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| 112 | c_read_width_a => 8, |
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| 113 | c_read_width_b => 8, |
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| 114 | c_rst_priority_a => "CE", |
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| 115 | c_rst_priority_b => "CE", |
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| 116 | c_rst_type => "SYNC", |
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| 117 | c_rstram_a => 0, |
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| 118 | c_rstram_b => 0, |
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| 119 | c_sim_collision_check => "ALL", |
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| 120 | c_use_byte_wea => 0, |
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| 121 | c_use_byte_web => 0, |
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| 122 | c_use_default_data => 0, |
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| 123 | c_use_ecc => 0, |
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| 124 | c_use_softecc => 0, |
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| 125 | c_wea_width => 1, |
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| 126 | c_web_width => 1, |
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| 127 | c_write_depth_a => 8191, |
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| 128 | c_write_depth_b => 8191, |
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| 129 | c_write_mode_a => "WRITE_FIRST", |
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| 130 | c_write_mode_b => "WRITE_FIRST", |
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| 131 | c_write_width_a => 8, |
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| 132 | c_write_width_b => 8, |
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[137] | 133 | c_xdevicefamily => "artix7" |
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[115] | 134 | ); |
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| 135 | -- synthesis translate_on |
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| 136 | BEGIN |
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| 137 | -- synthesis translate_off |
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| 138 | U0 : wrapped_mem8k8 |
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| 139 | PORT MAP ( |
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| 140 | clka => clka, |
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| 141 | ena => ena, |
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| 142 | wea => wea, |
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| 143 | addra => addra, |
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| 144 | dina => dina, |
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| 145 | clkb => clkb, |
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| 146 | enb => enb, |
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| 147 | addrb => addrb, |
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| 148 | doutb => doutb |
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| 149 | ); |
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| 150 | -- synthesis translate_on |
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| 151 | |
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| 152 | END mem8k8_a; |
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